Session 2013-14

“NAND FLASH 101”

Submitted To- Submitted By-

Mr. Ashutosh Mishra Dhiraj Kumar

H.O.D 10ESIEC031

(E.C.E Department) B.Tech 4 th year

s.k.chaudhary educational trust’s

shankara institute of technology kukas, jaipur

Department of Electronics & Communincation Engineering

Introduction to Nand Flash 101;Flash Basics;NAND Vs NOR Comparison; NAND Flash Basics Benefits;NAND Flash Architecture;NAND Flash Commands;Storage Methods;

Contents -

The basics of NAND Flash and demonstrates its power, density, and cost advantages for embedded systems. It covers data reliability and methods for overcoming common interface design challenges, focusing on the actual hardware and software components necessary to enable designers to build complete and functional subsystems.

Embedded systems have traditionally utilized NOR Flash for nonvolatile memory. Many current designs are moving to NAND Flash to take advantage of its higher density and lower cost for high-performance applications.

Introduction to NAND Flash 101 [1,4]

Markets—solid

state drives, mobile

phones, Flash

memory cards,

USB Flash drives

and

MP3/PMP players.

Demand for NAND Flash has been driven primarily several major

The NAND Flash device is based on a 2Gb asynchronous SLC device and its parameters (unless otherwise noted).

Higher density devices and other more advanced NAND devices may have additional features and different parameters.

The NAND Flash array is grouped into a series of blocks, which are the smallest erasable entities in a NAND Flash device.

A NAND Flash block is 128KB. Erasing a block sets all bits to 1 (and all bytes to FFh).

Programming is necessary to change erased bits from 1 to 0. The smallest entity that can be programmed is a byte. Some NOR Flash memory can perform READ-While-WRITE operations. Although NAND FLASH cannot perform READs and WRITEs simultaneously, it is possible to accomplish READ/WRITE operations at the system level using a method called shadowing. Shadowing has been used on personal computers for many years to load the BIOS from the slower ROM into the higher-speed RAM .

Flash Basics[2,4]-

Figure 2 shows a comparison of NAND Flash and NOR Flash cells[1,5] -

Area Efficiency-

NAND Flash and NOR Flash[3,6]-

NAND Flash and NOR Flash Characteristic[2,4]-

The real benefits of NAND Flash are faster PROGRAM and ERASE times, as NAND Flash delivers sustained WRITE performance exceeding 7 MB/s. Block erase times are an impressive 500μs for NAND Flash compared with 1 second for NOR Flash.

Metal contacts in NOR cell are the limiting factor: 2.5X difference in area/cell.

NAND Flash Design Benefits[1,3]-

NAND Flash offers several structural advantages over NOR Flash, starting with the pin count. The hardware pin requirements for NAND Flash and NOR Flash interfaces differ markedly. NOR Flash requires approximately 44 I/O pins for a 16-bit device, while NAND Flash requires only 24 pins for a comparable interface.

Another advantage of NAND Flash is evident in the packaging options. For example, this NAND Flash device offers a monolithic 2Gb die or it can support up to four stacked die, accommodating an 8Gb device in the same package. This makes it possible for a single package and interface to support higher densities in the future.

Structural Differences[2,5]-

Required Hardware Pins-

Flash Operations – Read – Write or Program Changes a desired state from 1 to 0 – Erase Changes all the states from 0 to 1 • Unit – Page (sector) Read/Write unit (in NAND) – Block • Erase unit

NAND Flash Architecture and Basic SLC Operation[1,5]-

Architecture[2,4]-

The 2Gb NAND Flash device is organized as 2048 blocks, with 64 pages per block . Each page is 2112 bytes, consisting of a 2048-byte data area and a 64-byte spare area. The spare area is typically used for ECC, wear-leveling, and other software overhead functions, although it is physically the same as the rest of the page.

Many NAND Flash devices are offered with either an 8- or a 16-bit interface. Host data is connected to the NAND Flash memory via an 8-bit- or 16-bit-wide bidirectional data bus. For 16-bit devices, commands and addresses use the lower 8 bits (7:0). The upper 8 bits of the 16-bit data bus are used only during data-transfer cycles.

Erasing a block requires approximately 500μs. After the data is loaded in the register, programming a page requires approximately 220μs. A PAGE READ operation requires approximately 25μs, during which the page is accessed from the array and loaded into the 16,896-bit (2112-byte) register. The register is then available for the user to clock out the data.

In addition to the I/O bus, the NAND Flash interface consists of six major control signals

Data is shifted into or out of the NAND Flash register 8 or 16 bits at a time, In a PROGRAM operation, the data to be programmed.

When any NAND Flash command is issued, CE# and ALE must be LOW, CLE must be asserted, and write clocks (WE#) must be provided. When any NAND Flash address is issued, CE# and CLE must be LOW, ALE must be asserted, and write clocks (WE#) must be provided. While the device is busy, only two commands can be issued: RESET and READ STATUS.

NAND Flash Commands[3,4]-

Command Cycles for NAND Flash Operations-

The two common methods for storing data and spare information is. The first method shows a data area of 512 bytes plus the 16-byte spare area directly adjacent to it; 528 bytes for the combined areas. A 2112-byte page can contain four of these 528-byte elements. The second implementation involves storing the data and spare information separately. The four 512-byte data areas are stored first, and their corresponding 16-byte spare areas follow, in order, at the end of the page.

Storage Methods-

NAND Flash provides the power, density, and cost advantages essential for embedded systems in high-performance applications such as digital cameras and navigational devices, solid state drives, mobile phones, Flash memory cards, and USB Flash drives.

As the major markets relying on NAND Flash continue to expand, NAND Flash technology will continue to evolve and claim additional market share, providing the higher densities, lower costs, and added functionality necessary to support these advanced designs.

Conclusion-

[1].www.wikipedia.com[2].www.slideshare.net [3].www.flashmemorysummit.com [4].www.micron.com[5]. Web.arrownac.com[6].cal.postech.ac.kr

Refrences-

QUERIES ,………??THANK YOU