news from icemos
DESCRIPTION
News from IceMOS. Alessandro Mapelli CERN PH-DT. frame. baseline. Schedule update December 3 rd. today. Done.. First wafers sent to CERN. Bulk Si vs SOI flows. Silicon Etching. Etch measurements from the first 9 bulk silicon wafers. Channels etch 70um +/- 7um. - PowerPoint PPT PresentationTRANSCRIPT
GTK Collaboration meeting 1
News from IceMOS
11/12/12
Alessandro MapelliCERN PH-DT
baseline
frame
GTK Collaboration meeting 2
Schedule update December 3rd
11/12/12
CERN NA62 Project ScheduleWeek 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1301 1302 1303 1304 1305Date week ending 12/10/12 19/10/12 26/10/12 02/11/12 09/11/12 16/11/12 23/11/12 30/11/12 07/12/12 14/12/12 21/12/12 28/12/12 04/01/13 11/01/13 18/01/13 25/01/13 01/02/13Project weeks 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Christmas Project plan & schedule
Mask design and procurementGDS received from customer 23/10/12
Masks arrived 12/11/12
Raw material Procurement BOM build Development of fluid channel & Via etch in combination Cavity Bonding Photo & Etch development of front and back side port opening Photo & Etch of via opening Bulk option versus SOI for wafer stability Bulk lot 1
A B C D E F
Bulk lot 2 B C D E F SOI lot 1
A B C D E F G
SOI lot 2 B C D E F G SOI lot 3 B C D E F GDevices for cavity join
Tests
Poly/Oxide etch test completeChannels etch test completeCombined etch test completeDS Photo test in progress, first results due this week
Bulk lot 1 on schedule Issue with bow/warp on devices, trying to rectify this with rework, handles @ channels & manifolds etch, running few more test wafers before product, potential bow /warp issue with handles at join
Bulk lot 2 ahead of schedule Issue with bow/warp on devices, trying to rectify this with rework, handles trying different option to reduce potential for bow issue at join, wafers @ photo before channels & manifold etch
SOI lot 1all batches in oxidation before poly then Channels and manifolds photo, 1st lot approx 1 week behind
SOI lot 2SOI lot 3
today
Done.. First wafers sent to CERN
GTK Collaboration meeting 3
Bulk Si vs SOI flows
11/12/12
Bulk flow Device weeks Handle & AM manufacture 2 1 week AFluid photo & etch, Via photo 1 BVia etch 1 CBond 1 DPhoto & etch Ports 1 EPhoto & etch Via opening 1 F
SOI flow Device weeks SOI & AM manufacture 3 1 week AFluid photo & etch, Via photo 1 BVia etch 1 CBond 1 DPhoto& etch transfer AM & FS Port 1 EHandle removal 1 FPhoto & etch BS Port & Via opening 1 G
GTK Collaboration meeting 4
Silicon Etching
• Etch measurements from the first 9 bulk silicon wafers
11/12/12
Fluid Channels
Scribe T M B L R AVE
1211-092672.9
0 70.08 72.90 73.73 75.8373.0
9
1211-091073.7
6 71.12 75.01 75.65 75.6274.2
3
1211-092567.4
6 65.25 68.44 70.28 68.4967.9
8
1211-091368.3
3 65.99 68.29 70.69 70.7768.8
1
1211-091968.3
0 65.54 69.14 72.08 69.7268.9
6
1211-092468.8
9 67.02 70.95 72.77 71.2070.1
7
1211-092367.7
8 65.98 69.01 69.69 71.4868.7
9
1211-091768.4
4 66.70 70.16 70.42 72.1469.5
7
1211-092169.3
0 66.86 68.83 69.97 71.9569.3
8 IceMOS CONFIDENTIAL
Top Manifold Bottom Manifold
Scribe L M R AVE L M R AVE
1211-0926285.4
0 274.51 285.48 281.80290.7
3283.7
3283.8
1 286.09
1211-0910294.1
9 283.35 292.81 290.12303.4
3290.4
1297.9
7 297.27
1211-0925288.5
0 283.21 286.42 286.04300.0
4290.6
0293.5
0 294.71
1211-0913288.0
7 277.53 275.05 280.22296.8
3286.1
0290.8
6 291.26
1211-0919280.3
7 274.04 281.57 278.66289.4
0277.5
9282.8
8 283.29
1211-0924286.0
6 279.60 287.86 284.51296.9
1285.6
2288.4
3 290.32
1211-0923278.0
7 271.69 279.27 276.34287.1
6278.5
9280.6
0 282.12
1211-0917281.2
2 275.00 281.53 279.25290.1
4279.1
7282.5
0 283.94
1211-0921291.3
2 288.50 295.48 291.77302.7
8293.0
6295.6
2 297.15
Channels etch 70um +/- 7um Manifolds etch – total depth 285um +/- 25um
GTK Collaboration meeting 5
Silicon Etching
11/12/12
IceMOS CONFIDENTIAL
GTK Collaboration meeting 6
First wafers have been shipped..
• 3 bulk silicon wafers have been shipped on December 10th from IceMOS to CERN.
• These wafers will be used to validate the last step of the fabrication process at EPFL with wafers from IceMOS.
• It consists of the silicon etching with KOH to thin the acceptance area of the cooling plate.
11/12/12