Laboratoire de l’Accélérateur Linéaire (IN2P3-CNRS) Orsay, France

24 February 2003

News about News about SPECSSPECS system system

SPECS systemSPECS-SLAVE chipSPECS-SLAVE mezzanine boardGround isolationDevelopment schedule

LHCb week February 2003LHCb week February 2003 D.CharletD.Charlet

PCI PCI SPECSSPECS Master Board Master Board

PCI connector

PC mother board

PCI SPECS Master board

LVDS drivers

4 SPECS Masters +

1 SPECS Slave APEX 20K200E

PQFP 240

PCI targetinterface

PLX 9030PQFP 176

RJ45SPECS or JTAG LVDS bus

SPECS or I2C LVDS bus

SPECSLVDS bus

PCI bus

PLX local busSPECS bus

RJ45

RJ45

RJ45

LVDS drivers

LVDS drivers

LVDS drivers

SPECSLVDS bus

Firmware version 2.0Firmware version 2.0

LHCb week February 2003LHCb week February 2003 D.CharletD.Charlet

SPECS new implementationSPECS new implementation

RJ45

Differential to TTL

MS_SDA

MS_SCL

SM_SDA

SM_SCL

RJ45

Differential to TTL

MS_SDA

MS_SCL

SM_SDA

SM_SCL

SPECS bus(4 diff pairs)

(up to 100m)

SPECS slave

Mezzanine board

SPECS master

PCI board

LHCb week February 2003LHCb week February 2003 D.CharletD.Charlet

On detector I2C On detector I2C implementationimplementation

SDA

SCL

On detectorRemote board

OC

SPECS slaveMezzanine board

Detector board

On detector

chips

RJ45

I2C master side

12

34

56

78

I2C slave side

SDA +

SDA -

SDA return +

SDA return -

SDA +

SCL +

SCL -

SDA -

SDA return +

SDA return -

SCL return +

SCL return -

SCL +

SCL -

SCL return -

SCL return +

RJ45

I2C master side

12

34

56

78

I2C slave side

SDA +

SDA -

SDA return +

SDA return -

SDA +

SCL +

SCL -

SDA -

SDA return +

SDA return -

SCL return +

SCL return -

SCL +

SCL -

SCL return -

SCL return +vcc

DS92LV010A

LHCb week February 2003LHCb week February 2003 D.CharletD.Charlet

SPECS-SLAVE chipSPECS-SLAVE chip

Data [7:0]

REG_OUT [31:0]

Subadd [7:0]

SDA_MS

L0reset/TestPulse

Broadcast [7:0]

Read*

Write*

User Interrupt

40 MHz ClkReset*

Slave Address [7:0]

PBA [3:0](Partial Broadcast Address)

SCL_MS

SDA_SM

SCL_SM

SPECSslave

Serial out enable Reset_out *

TDO

TMS

TCK

TDI

JTAG

SPECSbus

Parallelbus

I2C

SDASDAreturn

SCL

Bus_CS/DIR[15:0]SCLreturn

Channel B

Cde register

Serial prom Access

Global ctrl

SPECS identification Data [7:0]

REG_OUT [31:0]

Subadd [7:0]

SDA_MS

L0reset/TestPulse

Broadcast [7:0]

Read*

Write*

User Interrupt

40 MHz ClkReset*

Slave Address [7:0]

PBA [3:0](Partial Broadcast Address)

SCL_MS

SDA_SM

SCL_SM

SPECSslave

Serial out enable Reset_out *

TDO

TMS

TCK

TDI

JTAG

SPECSbus

Parallelbus

I2C

SDASDAreturn

SCL

Bus_CS/DIR[15:0]SCLreturn

Channel B

Cde register

Serial prom Access

Global ctrl

SPECS identification

LHCb week February 2003LHCb week February 2003 D.CharletD.Charlet

Architecture of SPECS slave FPGAArchitecture of SPECS slave FPGA

RE

CE

PT

ION

CO

NT

RO

L B

US

R EC EI V ERB L O C K

S ER I A LPR O MI NTER FA C E

EM I TTERB L O C K

R EG I S TERB L O C K &C H A NNEL BD EC O D ER

PA R A L L ELB USC O NTR O LB L O C K

EM

ET

TE

R

C

ON

TR

OL

BU

S

DA

TA

BU

S

G L O B A LC O NTR O LB L O C K

S M _ S D A

S M _ S C L

M S _ S D A

M S _ S C L

I 2 C _ S D A

EN_ D R I V [7 :0 ]

D A TA [7 :0 ]

A D D [7 :0 ]

C TR L

J TA GC O NTR O LB L O C K

J TA GI 2 CC O NTR O LB L O C K

R EG _ O UT[3 1 :0 ]

C H A NNEL B [9 :0 ] ]S C L /S D A

C L K /R S T

D I R [7 :0 ]

LHCb week February 2003LHCb week February 2003 D.CharletD.Charlet

SPECS slave chip SPECS slave chip pinoutpinout 1 1

OutWhen high this output holds the PROM address counter reset and 3states the data output.RESET/OE*

InSerial Data coming from the identification PROM.SER_DATA

OutSerial Clk for PROM identification.SER_CLK

InSerial SPECS data : Master SlaveSDA_MS

InSerial SPECS clock : Master SlaveSCL_MS

OutSerial SPECS data : Slave MasterSDA_SM

OutSerial SPECS data : Slave MasterSCL_SM

OutStatic register. This register is protected by triple voting logics.EXT_REG [31:0]

InInput from channel B of TTCrxBRCST [7:0]

OutDecoded function of the Brcst [7:0]TEST_PULSE

OutDecoded function of the Brcst [7:0]L0_RESET

Data bus directionRD/WR*

InputIndividual address of the SPECS slave chip. This address is provided by external switches.SLAVE_ADD[7:0]

InputPartial broadcast address. Allows to define a group of SPECS slaves for broadcast commands.PBA[3:0]

Pin description

General chip reset

Slave input clock

OutParallel Address bus [7:0]ADDR[7:0]

InUser interruptINTERRUPT

Parallel Data bus [7:0]

Output reset that can be generated even without Clk40. This output pin is controlled by a specific SPECS address.

Command for the SPECS bus external output buffer. For backplane use of SPECS.

Pin numberI/O defPin Name

InRESET_IN*

OutSER_OUT_EN

OutRESET_OUT*

In/0utDATA[7:0]

InCLK40

OutWhen high this output holds the PROM address counter reset and 3states the data output.RESET/OE*

InSerial Data coming from the identification PROM.SER_DATA

OutSerial Clk for PROM identification.SER_CLK

InSerial SPECS data : Master SlaveSDA_MS

InSerial SPECS clock : Master SlaveSCL_MS

OutSerial SPECS data : Slave MasterSDA_SM

OutSerial SPECS data : Slave MasterSCL_SM

OutStatic register. This register is protected by triple voting logics.EXT_REG [31:0]

InInput from channel B of TTCrxBRCST [7:0]

OutDecoded function of the Brcst [7:0]TEST_PULSE

OutDecoded function of the Brcst [7:0]L0_RESET

Data bus directionRD/WR*

InputIndividual address of the SPECS slave chip. This address is provided by external switches.SLAVE_ADD[7:0]

InputPartial broadcast address. Allows to define a group of SPECS slaves for broadcast commands.PBA[3:0]

Pin description

General chip reset

Slave input clock

OutParallel Address bus [7:0]ADDR[7:0]

InUser interruptINTERRUPT

Parallel Data bus [7:0]

Output reset that can be generated even without Clk40. This output pin is controlled by a specific SPECS address.

Command for the SPECS bus external output buffer. For backplane use of SPECS.

Pin numberI/O defPin Name

InRESET_IN*

OutSER_OUT_EN

OutRESET_OUT*

In/0utDATA[7:0]

InCLK40

LHCb week February 2003LHCb week February 2003 D.CharletD.Charlet

SPECS slave chip pinout 2SPECS slave chip pinout 2

OutLocal JTAG clock.TCK

InLocal JTAG data out . TDO

OutLocal JTAG mode selectTMS

OutLocal JTAG data in . TDI

OutCommand for I2C external output buffer. It allows to drive up to 8 I2C differential busses from the same SPECS slave chip.

OUT_EN[7:0]

TriI2C data. Local I2C busI2C_SDA

OutI2C clock. Local I2C busI2C_SCL

OutJTAG clock. Long distance JTAG bus.TCK_EXT

InJTAG data out . Long distance JTAG bus.TDO_EXT

OutJTAG mode select . Long distance JTAG bus.TMS_EXT

OutJTAG data in . Long distance JTAG bus.TDI_EXT

OutCommand to invert direction of the driver we need to invert when we choose I2C or JTAGDIR_JTAG[7:0]

OutI2C data : Master Slave. Long distance I2C busI2C_SDA_MS

OutI2C clock : Master Slave. Long distance I2C busI2C_SCL_MS

InI2C data : Slave Master. Long distance I2C busI2C_SDA_SM

InI2C clock : Slave Master. Long distance I2C busI2C_SCL_SM

Pin description

Local JTAG reset

Pin numberI/O def

Pin Name

OutTRST

OutLocal JTAG clock.TCK

InLocal JTAG data out . TDO

OutLocal JTAG mode selectTMS

OutLocal JTAG data in . TDI

OutCommand for I2C external output buffer. It allows to drive up to 8 I2C differential busses from the same SPECS slave chip.

OUT_EN[7:0]

TriI2C data. Local I2C busI2C_SDA

OutI2C clock. Local I2C busI2C_SCL

OutJTAG clock. Long distance JTAG bus.TCK_EXT

InJTAG data out . Long distance JTAG bus.TDO_EXT

OutJTAG mode select . Long distance JTAG bus.TMS_EXT

OutJTAG data in . Long distance JTAG bus.TDI_EXT

OutCommand to invert direction of the driver we need to invert when we choose I2C or JTAGDIR_JTAG[7:0]

OutI2C data : Master Slave. Long distance I2C busI2C_SDA_MS

OutI2C clock : Master Slave. Long distance I2C busI2C_SCL_MS

InI2C data : Slave Master. Long distance I2C busI2C_SDA_SM

InI2C clock : Slave Master. Long distance I2C busI2C_SCL_SM

Pin description

Local JTAG reset

Pin numberI/O def

Pin Name

OutTRST

LHCb week February 2003LHCb week February 2003 D.CharletD.Charlet

SPECS slave mezzanine boardSPECS slave mezzanine board

JTAG or I2C Bus

Dir[7:0]En[7..0]

SPECS SLAVE MEZZANINE BOARD

SPECSSLAVE

ActelAX-125

JTAG Bus

I2C Bus

POWERREGULATOR

SERIALPROMAddress switches

JTAG or I2C

DIFFERENTIAL LINK

JTAG or I2C

DIFFERENTIAL LINK

8 B

US

SE

S

Outputregister

32

SPECS

bus

Cmd &

Ctrl I/Os

Channel B

Parallel Bus

ADC ?

JTAG or I2C Bus

Dir[7:0]En[7..0]

SPECS SLAVE MEZZANINE BOARD

SPECSSLAVE

ActelAX-125

JTAG Bus

I2C Bus

SPECSSLAVE

ActelAX-125

JTAG Bus

I2C Bus

POWERREGULATOR

POWERREGULATOR

SERIALPROM

SERIALPROMAddress switchesAddress switches

JTAG or I2C

DIFFERENTIAL LINK

JTAG or I2C

DIFFERENTIAL LINK

8 B

US

SE

S

Outputregister

32

SPECS

bus

Cmd &

Ctrl I/Os

Channel B

Parallel Bus

ADC ? ADC ?

LHCb week February 2003LHCb week February 2003 D.CharletD.Charlet

Functionalities of the Functionalities of the mezzaninemezzanine

                  8 switches will be available to fix the SPECS slave 8 switches will be available to fix the SPECS slave address and 4 for the broadcast group address (one by type of address and 4 for the broadcast group address (one by type of board for instance).board for instance).                  One PROM will allow the ECS system to get information One PROM will allow the ECS system to get information about the concerned front-end element. It will be mounted on about the concerned front-end element. It will be mounted on a socket.a socket.                  8 software programmable I2C/JTAG differential outputs. 8 software programmable I2C/JTAG differential outputs. Each of them can individually be dedicated to one type of bus. Each of them can individually be dedicated to one type of bus.                   One local I2C bus and one local JTAG bus.One local I2C bus and one local JTAG bus.                  One parallel bus.One parallel bus.                  One decoder for the channel B of the TTCrx will be One decoder for the channel B of the TTCrx will be implemented within the SPECS slave chip. It will decode the implemented within the SPECS slave chip. It will decode the necessary functions (currently L0 counter reset and Test necessary functions (currently L0 counter reset and Test pulse). Others ?pulse). Others ?                  One 32-bit static register to control the local One 32-bit static register to control the local environment (would 16 be enough ? ).environment (would 16 be enough ? ).We are looking at the possibility to put an 8 bit ADC on this We are looking at the possibility to put an 8 bit ADC on this board, for slow measurements like temperature, etc ... The board, for slow measurements like temperature, etc ... The problem is actually to find a sufficiently rad-hard one …problem is actually to find a sufficiently rad-hard one …

LHCb week February 2003LHCb week February 2003 D.CharletD.Charlet

SPECS slave mezzanine board SPECS slave mezzanine board implentationimplentation

LHCb week February 2003LHCb week February 2003 D.CharletD.Charlet

Ground isolation implementation Ground isolation implementation proposalproposal

Baracks100m

Top of detector

Crate"Controller"

Specsslave

21 boards

Point to pointClock distribution

Optional insulation crate

Optical link ?

LHCb week February 2003LHCb week February 2003 D.CharletD.Charlet

SSchedule for the SPECS systemchedule for the SPECS system

Firmware version 2.0 BetaPCI Master board vesrsion 1

Firmware version 2.0

Windows Software

February March April

Version 2.1 Documentation

Linux Software

May

PCI Master board version 2

June July

SPECS-Slave mezzanine board