new low-voltage class ab

8/7/2019 New Low-Voltage Class AB

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NEW LOW-VOLTAGE CLASS AB/AB CMOS

OPAMP WITH RAIL-TO-RAIL INPUT/OUTPUT

SWING

Presented by,Anjith George

10EE64R03

M Tech Instrumentation

IIT Kharagpur


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CONTENTS

Introduction

Previous low voltage OPAMPS

Proposed circuit-advantages

Floating gate transistors

OPAMP architecture

Simulation results

Experimental results

Conclusion

References


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INTRODUCTION

Applying simple topologies in order to obtain high efficiency is the keydesign technique for future analog cells in mixed-mode very-large-scale-integration (VLSI) circuits.

With the reduction in feature size of complementary metaloxidesemiconductor (CMOS) processes continues steadily, the supply voltagehas to be reduced while the higher integration density enforces lowerpower consumption per cell

Analog cells benefit marginally because minimum size transistorscannot be used due to noise and offset requirements

The only way for analog cells to keep up with the digital performance

and the supply-voltage reduction is by using very efficient topologiesthat combine low-voltage operation with high power efficiency andsmall die area.


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PREVIOUS LOW VOLTAGE OPAMPS

For low supply , two stage fully differential class AB topology is used

Pseudo differential

Problems

1) the opamp has very limited input

signal swing

2) both the pseudo-differential input stage

and the CMFN require sensing of the common input and

output voltages. This is done in using large valued silicon

area intensive resistors that degrade input impedance and

gain,


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PROPOSED CIRCUIT

A new low-voltage CMOS Class AB/AB fully differential opamp with rail-to-rail input/output swing and supply voltage lower than 2Vgs drops ispresented.

Avoids the mentioned drawback and features rail to rail input/outputswings

Here multiple input floating gate transistors are used (MIFG)

MIFG circuits achieve low voltage operation with Vdd


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ADVANTAGES

Low voltage less than 2Vgs

Based on floating gate transistors

Have class AB input and output stages

Low static power consumption

High slew rates upto 20V/s

Reliable (no initial charge on gate problem)

Rail to rail input and output swing


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FLOATING GATE TRANSISTORS

Floating-gate MOS transistor is

generated by forming an additional

conductive layer, between control

terminal G and channel DS isolated

from the environment, called floating gate.

For transistors equipped with larger quantity of control terminals Githan one (MIFGMOS), they are contacting with that gate through thecapacities Ci created between them.

Floating gate is contacting with the channel CH through the capacity ofoxide layer COX and with source, drains and bulks through the capacitiesCFS , CFD and CFB .

Values of those capacities depend on the area of input gates Gi, floatinggate FG and channel as well as on thickness of oxide layer betweenthem.


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FLOATING GATE TRANSISTORS


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DIFFERENTIAL PAIR WITH FLOATING GATE

For low-voltage applications a relatively large valued capacitor CBIAS connected to adc voltage VBIAS This can be used in order to bring the quiescent floating-gate voltages VQFG1,2 closeto one of the supply rails(VDD for nMOS transistors, VSS for pMOS transistors).This reduces the supply requirements


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loop gain [and the gain bandwidth product (GBW)] is reduced by thefactor C/(C+CBIAS)

In order to avoid a large degradation factor for GBW it is convenient toset C=CBIAS

VinQ =VDD/2, VBIAS=VDD We get, VQFG1,2 =3/4VDD , closer to supply rail

Advantages

1) a modest reduction of GBW

results in improved phase margin, and

2) the attenuation of input

signals at the FG inputs yields increased input swing


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Operating in single supply voltage VDD (VSS =0) With common mode input voltage VinQ.C

Under quiescent conditions voltage at floating gates VQFG1= VQ

FG2

This due to capacitive voltage divider openl oop gain reduced by factorK=C/(C+ CBIAS )


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VDD =1.8V , VTHN=0.7V, VDSAT=0.125V, CBIAS=C,Vip=0.8V then Vfg=1.35V,Vfg

max=1.75V, Vfgmin=0.95V

The minimum value of the floating-gate voltage still leaves enough room

for the nMOS differential pair to remain functional with close to rail-to-rail input swing,

The maximum input voltage still allows the differential

pair to operate in saturated mode


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COMMON MODE SENSING USING FLOATING

GATES

Floating gate transistors can be used for sensing common mode signals

The class AB used requires sensing of the common mode input voltagein order to achieve class AB operation and high CMRR

This is done using capacitive division


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CLASS AB/AB OPAMP IMPLEMENTATION USING

MIFGS


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OPAMPARCHITECTURE

The input stage consists of transistors M1-M4 , M1P-M4P , MFVF-MBFVF ,and MSENSE

It includes a flipped-voltage follower (FVF) Formed by , MFVF-MBFVF ,and MSENSE

It has a high CMRR since common-mode input voltages do not changeVGS 1or VGS2 Sensing of the common-mode input voltage required at the input stage

is achieved by implementing MFVF also as a three input floating-gatetransistor. In this case inputs Vi+ , Vi- , are coupled to the floating gate ofusing equal valued capacitors(C/2) . An additional terminal is coupled

to VDD through a capacitor CBIAS to bias the transistor . No reference VinCM voltage is needed and that with this simple scheme

the common mode of Vi+ , Vi- , appears at the gate of MFVF (shiftedToward VDD)


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The dynamic currents generated in the input stage are used to drive theinternal terminals of the compensation capacitors at nodes A and B.

The bias current of the input stage is the limiting factor for slew rate ofconventional Class A/AB opamps.

currents at nodes A and B can take much larger values than theirquiescent value and for this reason this circuit shows an enhancedslewrate with respect to conventional ClassA/ABopamps.


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OUTPUT STAGE

The Class AB output stage shown in Fig. 4(a) (transistorsM5-M8andM5i-M8i ) has following advantages:

a) It does not require a separate quiescent current control circuit,

b) it can operate at very low supply voltages VDDmin=VGS +VDSSAT

c) it has rail-to-rail output swing. The value of the output Currents can be essentially larger than the quiescent drain current

of , M7, M5 .

The output stage can deliver large dynamic output currents both, tothe external terminal of the compensation capacitors , to the

floating-gate capacitors as well as to the load capacitors .


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INPUT AB STAGE

The FVF cell creates a very low impedance

node at the common source of M1,M2,

M1P and M2P (node x ).

This sets the quiescent gate-source voltage

of these transistors and the corresponding

quiescent current in all transistors. Matched transistors MFVF and M1, M2,

M1P, M2P a quiescent current in M1-M2 and

M1P-M4P with value ID1Q=ID2Q=Ibias

results If voltage Vcminp equals the common

mode of input voltages V1 and V2.

The low impedance node causes transistors M1-M2 (and M1P, M2P) to operate as a voltage

biased differential pairs.

Transistors M3, M4, M3P and M4P form current mirrors that generate complementarycurrents

Ia=ID1-ID2 and Ib=ID2-ID1 (Ia=-Ib) at the input stageoutput nodes a and b


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OUTPUT STAGE

Under quiescent conditions the voltages

Va=Vb=VGS3 Q=VGS4 Q lead to equal

currents in M7 and M7i ID7 Q=ID7i

Q=Ibias (W/L)7 / (W/L)3. Since

M5, M5i form a unity gain current mirrorthe quiescent current in M5 has the same

value as in M7: ID7 Q=ID5

Q and zero output current results

under quiescent conditions.

For positive variations in Va (and

corresponding negativevariations in Vb)

the current in M7 increases

while that in M7i decreases. This leads to

A negative output current Iout =Io- flowing out of terminal Vo-.


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CMFN

CMFN used to control the common-mode output voltage

It consists of a differential amplifier (MCMF1 , MCMF2, MCMP1, MCMP2, MCMN2)with three-input floating-gate transistors MCMF1 and MCMF2 with couplingcapacitors C1=C/2,C2=C/2 and CCM=C

The capacitive MIFG voltage division is used to shift both the referencecommon-mode voltage VrefCM and the output common-mode voltagevery close to the positive rail.

This is done to minimize the supply requirements and to provide rail-to-rail operation to the CMFN amplifier.

The voltage VcntCM drives transistors MCMT0- and MCMT0+ .These are

connected directly to the opamp output nodes in order to control thecommon-mode output voltage


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CMFN USING MIFGS


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SIMULATION RESULTS

The opamp was simulated using BSIM3v3 models for 0.5- m CMOSAMI-MOSIS parameters with nominal nMOS and pMOS thresholdvoltages of 0.67 V a nd0.96V, respectively.

an amplifier with nominal gain A=5(using

resistors Rf=50k , R1=10k ). A single supply voltage Vdd=1.8V(Vss=0)was used.


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SIMULATION RESULTS

The output swing of the proposed opamp is close to rail-to-rail.


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TRANSIENT RESPONSE

The transient response of the gain-5 inverting amplifier was

simulated, using a 500-kHz, 1.6 Vpp periodic square waveforminput and with a 50-pF capacitive load.. The slew rate was 20 V / s. The simulated AC response led to a bandwidthof 2.4 MHz. This value corresponds to a gain-bandwidth productGBW=12MHz CMRR at 10 kHz was 90 dB.


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EXPERIMENTAL RESULTS

Test chip was made

using 0.5 m CMOS technology

with sizes as in table 1

Circuit was tested with

voltage follower and inverting

configurations using +_9Vsupplies

The gain-5 inverting amplifier showed the expected

gain within less than 2% error and with mid supply

common-mode input voltage V in=0V.

The gain error can be attributed to mismatch errors in the gain settingresistors Rf and Ri and to the loss of open loop gain due to resistiveloading of opamp terminals


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EXPERIMENTAL RESULTS

Measured output dc offset voltages in five fabricated samples ranged from 3.2 to28 mV. This corresponds to input offset voltages from 0.64 to 5.6 mV.Measured CMRR values were between 4550 dB.Experimental slew rate and bandwidth were 16 V/s and 1.8 MHz, respectively


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CONCLUSION

The supply requirements are lower than traditional opamps.

The proposed circuit provides slew rate enhancement at the expense ofvery modest increase in circuit complexity.

It achieves high CMRR and rail-to-rail input/output signal swing

by means of floating-gate transistors. The proposed circuit can operate with a single sub-volt supply Vdd


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REFERENCES

[1] New Low-Voltage Class AB/AB CMOS Opamp With Rail-to-Rail Input/OutputSwing

Jaime Ramrez-Angulo, Fellow, IEEE, Milind-Subhash Sawant, Shanta Thoutam,Student Member, IEEE,Antonio J. Lpez-Martn, Member, IEEE, and Ramon G.Carvajal, Senior Member, IEEE.IEEE TRANSACTIONS ON CIRCUITS AND

SYSTEMSII: EXPRESS BRIEFS, VOL. 53, NO. 4, APRIL 2006 [2] Multiple-input floating-gate MOS transistor in analogue electronics circuit L.

TOPOR-KAMISKI and P. HOLAJN

BULLETIN OF THE POLISH ACADEMY OF SCIENCES TECHNICAL SCIENCES Vol.52, No. 3, 2004

[3] S. Thoutam, J. Ramrez-Angulo, A. Lopez-Martin, and R. G. Carvajal, Power

efficient fully differential low-voltage two stage Class AB/AB opamparchitectures, in Proc. ISCAS, vol. I, Vancouver, QC, Canada, May 2326, 2004, pp.733736.

[4] J. Ramirez-Angulo, R. G. Carvajal, J. Tombs, and A. Torralba, LowvoltageCMOS opamp with rail-to-rail input and output signal swing for continuous-timesignal processing using multiple-input floating-gate transistors, IEEE Tran.Circuits Syst. II, Analog Digit. SignalProcess., vol. 48, no. 1, pp. 111116, Jan. 2001.


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THANK YOU..

new low-voltage class ab

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