new coupling the agata demonstrator to other detectors: the … · 2017. 10. 14. · coupling the...
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Piotr BednarczykInstytut Fizyki Jądrowejim. Henryka NiewodniczańskiegoPolskiej Akademii Nauk
Electronics and interfacing do DAQElectronics and interfacing do DAQ
Coupling the AGATA Coupling the AGATA Demonstrator to other Demonstrator to other
detectors: the detectors: the AGAVAAGAVA GTS GTS interfaceinterface
An ancillary detector for AGATA, a model caseAn ancillary detector for AGATA, a model case
Fully digital, triggerFully digital, trigger--less system: less system: detector data timedetector data time--stamped and stored in stamped and stored in a pipelinea pipeline
Analogue VME electronics Analogue VME electronics with a trigger, with a trigger, data organized in events data organized in events
ANCILLARY detectors:ANCILLARY detectors:•• beam trackersbeam trackers•• particle, HI detectorsparticle, HI detectors•• γγ--detectorsdetectors
interaction pointinteraction pointoutgoing particle outgoing particle velocity vector velocity vector complementary complementary informationinformation
RecoilFilterDetector
AG
ATA
impulsupróbkowanie
DataMerging
Analogue VME
rekonstrukcja przypadkuTracking
GTS -Time stampstamp
digitizers + PSA …,Eγ1,Eγ2,…Eγn,…
{dE/dx, ToF, θ, φ}
EB + RFD example
EB + RFD example
Merging ancillaries to AGATA DAQ through Merging ancillaries to AGATA DAQ through AGAAGATATAVVMEMEAADAPTERDAPTER
Event Builder
PSA
Ancillary Merge
LLP
Digitizer
Tracking
Data analysis
GTS tr.
DATA Clock counterEvent Number
Ancillary Analogue FEE
AGAVA
GTS supervisor
prompt trigger <500ns
Ancillary VME
Ancillary readout
GTS tr.
Req.Trig-Val/Rej
Req.
Pre-processing
Slow control:Kmax, Labview, Midas, etc.
VME processor, DSP software
NARVAL producer:filtering, kinematics reconstr.
USER provided:USER provided:
AGAVAAGAVA-- the block diagramthe block diagram
AA carrier forcarrier for the GTS mezzanine the GTS mezzanine cardcard
Delivers path forDelivers path for signals signals from/to the GTS mezzaninefrom/to the GTS mezzanineandand thethe VME VME P1, P2 connectors P1, P2 connectors
Delivers 10W power @ 3.3 V Delivers 10W power @ 3.3 V to the GTS moduleto the GTS module
DeliversDelivers thethe Ethernet link Ethernet link to to the GTS modulethe GTS module
IInterfacenterface to the Metronome to the Metronome unit andunit and the Sharkthe Shark--Link moduleLink module(TDR JYFL)(TDR JYFL)
StandardStandard VME VME modulemodule (slave)(slave) compatible withcompatible with VXIVXI
GTS Trigger request and validation timing diagramGTS Trigger request and validation timing diagram
6μs1μs
AGAVA respects the GTS protocol:AGAVA respects the GTS protocol:
busy active till the next trigger request can be accepted by AGAVA
Data readyVME readout
requestsrequestsinternal (test)internal (test)external from FEEexternal from FEE
receivesreceives
AGAVAAGAVA operating modesoperating modesIMPLEMENTEDIMPLEMENTED ::
SLOWSLOW
--Standard VME access Standard VME access
--CBLT VME; LNL, (GSI ?)CBLT VME; LNL, (GSI ?)
--CBLT VXI; GANILCBLT VXI; GANIL
FORESEENFORESEEN::FAST FAST ––parallelparallelTDR; JYFL,TDR; JYFL,
Chained Chained BLockBLock TransferTransferefficient method to read sparse dataefficient method to read sparse data
A master CPU addresses several slaves at onceA master CPU addresses several slaves at once
The slaves determine who is to drive the data bus in The slaves determine who is to drive the data bus in response to a data strobe by passing a token via a daisy response to a data strobe by passing a token via a daisy chainchain
Special attention:Special attention:
The slow operation modeThe slow operation mode
Trigger req.Trigger req.
Local TriggerLocal TriggerValidation TriggerValidation Trigger
Data readyData ready
timetime--out if no Val/out if no Val/RejRej
successfully tested successfully tested in the LNLin the LNL--VME and VME and GANILGANIL--VXI VXI environmentsenvironments
The fast operation modeThe fast operation mode
Idea: Idea: Do not wait for the whole Do not wait for the whole Loc_TrigLoc_Trig--Val./RejVal./Rej. sequence. sequenceRead out the two Tags independently Read out the two Tags independently Synchronize and filter data stored in a memorySynchronize and filter data stored in a memory
Connection to TDRConnection to TDR
Hardware prepared, but not testedHardware prepared, but not tested
TDRTDR
Idea: insert the AGATA Idea: insert the AGATA timestamp into the TDR data streamtimestamp into the TDR data stream
The TDR data acquisition and The TDR data acquisition and Software Event builder will treat Software Event builder will treat the GTS timestamp data items in the GTS timestamp data items in the same way as TDR ADC data the same way as TDR ADC data items. items.
Proposed by P.J.Coleman-Smith
AGAVA registersAGAVA registersAddress (hex) Inhalt Type
Base Addr + 008000
Agava Status Register R/W1
Base Addr + 008004
Local Trigger Counter R/clr2
Base Addr + 008008
Validation Trigger Counter R/clr2
Base Addr + 00800C
Rejection Trigger Counter R/clr2
Base Addr + 008010
Local Tag bits 24 - 47 R
Base Addr + 008014
Local Tag bits 00 - 23 R
Base Addr + 008018
Validation Tag bits 47 – 24 R
Base Addr + 00801C
Validation Tag bits 00 - 23 R
Base Addr + 008020
Event Number bits 00 - 23 R
Base Addr + 008024
Rejection Tag bits 47 – 24 R
Base Addr + 008028
Rejection Tag bits 00 – 23 R
Base Addr + 00802C
LLP Status bits 0 – 7 R/W
Base Addr + 008030
GTS Status bits 0 - 7 R
Base Addr + 008034
MSG IN bits 0 - 7 R/
Base Addr + 008038
CBLT Status Control Register bits 0 – 1 R/W
Base Addr + 00803C
CBLT Address Register bits 0 –7 R/W
Base Addr + 008040
CBLT Header R/W
Base Addr + 008044
CBLT Trailer R/W
Base Addr + 008048
Trigger Input Counter R/clr2
Base Addr + 00804C
Timeout Counter R/clr2
Base Addr + 008050
Fast Clear Delay R/W
Base Addr + 008054- 0080BC
VXI related R/W3
Base Addr + 0080B0)
Inspection Lines Control Register R/W
Status Reg.Status Reg.GTS relatedGTS relatedCBLT relatedCBLT relatedVXI relatedVXI relatedinspection lineinspection linesparespare
The block control:The block control:--operation modeoperation mode--trig. typetrig. type--clear flagsclear flags
The The AGAVAAGAVA front panelfront panel
Input signals: back pressure, Trig. request
fixed inspection lines:• Loc_trig., Rej., Val. • busy, timeoutprogrammable inspection lines
GTS optical clock lines
control LEDs:DATA-ready, Val., Rej., busy, Loc_Trig.
connectors to TDR
Ethernet link to GST mezzanine
AGAVAAGAVA production statusproduction status
10 boards electronically assembled 10 boards electronically assembled (ordered from: LNL, Milan, GANIL)(ordered from: LNL, Milan, GANIL)corresponding GTS mezzanine boards are not availablecorresponding GTS mezzanine boards are not available
ongoing quality tests ongoing quality tests front panel finishing front panel finishing manual under preparationmanual under preparation
a first complete board will be available a first complete board will be available for collaborators very soonfor collaborators very soon
PRISMA with AGATA DAQ schemePRISMA with AGATA DAQ scheme
GTS
VMEADC
CPUSETUP +
CONTROL
Pre-preccessing & Narval Producer
Narval Narval Narval...
PRISMAPRISMAEvent rate:~20kHz (5Mb/sek)
CBLTCBLT
E.Calore
AGAVA
The AGAVA interface historyThe AGAVA interface history
AGATA Ancillary Detectors and Ancillary Detector Integration Working Group Specifications of the AGAVA (AGata Ancillary Vme Adapter) Ancillary Detector GTS Interface
Work DocumentVersion 1.2, July 2005
Contributors: D. Bazzacco, P. Bednarczyk, M. Bellato, P.J. Coleman-Smith, A. Czermak, B. Dulny, A. Gadea, Ch. Houarner, R. Isocrate, P. Jones, W. Meczyński, L. Olivier, V. Pucknell, Ch. Theisen, Ch. Weber, G. Wittwer, M. Ziębliński.
Specification:Specification:
Design and production: Design and production: B.Dulny, A.Czermak,
W.Męczyński, B.Sowicki, M.ZięblińskiIFJ-PAN Kraków
Tests Tests ((KrakKrakóów, LNL, GANIL): w, LNL, GANIL): B.Dulny,J.Grębosz,
IFJ-PAN Kraków, S.Brambilla,INFN-Milano
F. Saillant, G. WittwerGANIL
At work with At work with AGAVAAGAVA