netfpga informational tutorial
DESCRIPTION
Presented by: Adam Covington (Stanford University) César Guerrero (Universidad Autónoma de Bucaramanga) IEEE LATINCOM 2012 Cuenca, Ecuador November 7, 2012 http://NetFPGA.org. NetFPGA Informational Tutorial. Tutorial Outline. Motivation Introduction The NetFPGA Platform - PowerPoint PPT PresentationTRANSCRIPT
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NetFPGA InformationalTutorial
Presented by: Adam Covington(Stanford University)
César Guerrero(Universidad Autónoma de Bucaramanga)
IEEE LATINCOM 2012Cuenca, EcuadorNovember 7, 2012
http://NetFPGA.org
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Tutorial Outline
• Motivation– Introduction– The NetFPGA Platform
• Hardware Overview– NetFPGA 1G– NetFPGA 10G
• The Stanford Base Reference Router– Motivation: Basic IP review– Example: Reference Router running on the NetFPGA
• Extending the Reference Router– Motivation: Buffer Sizing– Example: Buffer Sizing Experiment running using the NetFPGA
• Community Contributions• Concluding Remarks
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Section I: Motivation
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NetFPGA = Networked FPGA
A line-rate, flexible, open networking platform for teaching and research
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NetFPGA 1G Board
NetFPGA consists of…
Four elements:
• NetFPGA board
• Tools + reference designs
• Contributed projects
• CommunityNetFPGA 10G Board
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NetFPGA 1G NetFPGA 10G
4 x 1Gbps Ethernet Ports 4 x 10Gbps SFP+
4.5 MB ZBT SRAM64 MB DDR2 SDRAM
27 MB QDRII-SRAM288 MB RLDRAM-II
PCI PCI Express x8
Virtex II-Pro 50 Virtex 5 TX240T
NetFPGA Board Comparison
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FPGAFPGA
MemoryMemory
1GE1GE
1GE1GE
1GE1GE
1GE1GE
NetFPGA board
PCI
CPUCPU MemoryMemory
NetFPGA Board
PC with NetFPGA
NetworkingSoftwarerunning on a standard PC
A hardware acceleratorbuilt with Field Programmable Gate Arraydriving Gigabit network links
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FPGAFPGA
MemoryMemory
1GE1GE
1GE1GE
1GE1GE
1GE1GE
Running the Router Kit
User-space development, 4x1GE line-rate forwarding
PCI
CPUCPU MemoryMemory
OSPFOSPF BGPBGP
My ProtocolMy Protocoluser
kernelRouting
Table
Usage #1
IPv4RouterIPv4
Router
1GE1GE
1GE1GE
1GE1GE
1GE1GE
FwdingTable
FwdingTable
PacketBuffer
PacketBuffer
“Mirror”
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FPGAFPGA
MemoryMemory
1GE1GE
1GE1GE
1GE1GE
1GE1GE
Enhancing Modular Reference Designs
PCI
CPUCPU MemoryMemory
Usage #2
NetFPGA DriverNetFPGA Driver
Java GUIFront Panel(Extensible)
Java GUIFront Panel(Extensible)
PW-OSPFPW-OSPF
In QMgmtIn Q
Mgmt
IPLookup
IPLookup
L2Parse
L2Parse
L3Parse
L3Parse
Out QMgmtOut QMgmt
1GE1GE
1GE1GE
1GE1GE
1GE1GE
Verilog modules interconnected by FIFO interfaces
MyBlockMy
Block
VerilogEDA Tools
(Xilinx, Mentor, etc.)
VerilogEDA Tools
(Xilinx, Mentor, etc.)
1. Design2. Simulate3. Synthesize4. Download
1. Design2. Simulate3. Synthesize4. Download
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FPGAFPGA
MemoryMemory
1GE1GE
1GE1GE
1GE1GE
1GE1GE
Creating new systems
PCI
CPUCPU MemoryMemory
Usage #3
NetFPGA DriverNetFPGA Driver
1GE1GE
1GE1GE
1GE1GE
1GE1GE
My Design
(1GE MAC is soft/replaceable)
My Design
(1GE MAC is soft/replaceable)
VerilogEDA Tools
(Xilinx, Mentor, etc.)
VerilogEDA Tools
(Xilinx, Mentor, etc.)
1. Design2. Simulate3. Synthesize4. Download
1. Design2. Simulate3. Synthesize4. Download
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Tools + Reference Designs 1G
Tools:• Compile designs• Verify designs• Interact with hardware
Reference designs:• Router (HW)• Switch (HW)• Network Interface Card (HW)• Router Kit (SW)• SCONE (SW)
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Contributed Projects
More projects:http://netfpga.org/foswiki/NetFPGA/OneGig/ProjectTable
Project Contributor
OpenFlow switch Stanford University
Packet generator Stanford University
NetFlow Probe Brno University
NetThreads University of Toronto
zFilter (Sp)router Ericsson
Traffic Monitor University of Catania
DFA UMass Lowell
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Community
Wiki• Documentation
– User’s Guide– Developer’s Guide
• Encourage users to contribute
Forums• Support by users for users• Active community - 10s-100s of posts/week
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International Community
Over 1,000 users, using 2,000 cards at150 universities in 40 countries
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NetFPGA’s Defining Characteristics
• Line-Rate– Processes back-to-back packets
• Without dropping packets • At full rate of Gigabit Ethernet Links
– Operating on packet headers • For switching, routing, and firewall rules
– And packet payloads• For content processing and intrusion prevention
• Open-source Hardware – Similar to open-source software
• Full source code available • BSD-Style License
– But harder, because • Hardware modules must meeting timing• Verilog & VHDL Components have more complex interfaces • Hardware designers need high confidence in specification of modules
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Test-Driven Design
• Regression tests– Have repeatable results – Define the supported features– Provide clear expectation on functionality
• Example: Internet Router– Drops packets with bad IP checksum– Performs Longest Prefix Matching on destination address– Forwards IPv4 packets of length 64-1500 bytes– Generates ICMP message for packets with TTL <= 1– Defines how packets with IP options or non IPv4
… and dozens more … Every feature is defined by a regression test
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Who, How, Why
Who uses the NetFPGA?– Teachers– Students– Researchers
How do they use the NetFPGA?– To run the Router Kit– To build modular reference designs
• IPv4 router• 4-port NIC• Ethernet switch, …
Why do they use the NetFPGA?– To measure performance of Internet systems– To prototype new networking systems
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Section II: Hardware Overview
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NetFPGA-1G
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Xilinx Virtex II Pro 50
• 53,000 Logic Cells• Block RAMs• Embedded PowerPC
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Network and Memory
• Gigabit Ethernet– 4 RJ45 Ports– Broadcom PHY
• Memories– 4.5MB Static RAM– 64MB DDR2 Dynamic
RAM
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Other IO
•PCI– Memory Mapped
Registers– DMA Packet Transferring
•SATA– Board to Board
communication
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NetFPGA-10G
• A major upgrade• State-of-the-art technology
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NetFPGA 1G NetFPGA 10G
4 x 1Gbps Ethernet Ports 4 x 10Gbps SFP+
4.5 MB ZBT SRAM64 MB DDR2 SDRAM
27 MB QDRII-SRAM288 MB RLDRAM-II
PCI PCI Express x8
Virtex II-Pro 50 Virtex 5 TX240T
Comparison
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10 Gigabit Ethernet
• 4 SFP+ Cages• NetLogic PHY• 10G Support
– Direct Attach Copper– 10GBASE-R Optical
Fiber
• 1G Support– 1000BASE-T Copper– 1000BASE-X Optical
Fiber
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Others
• QDRII-SRAM– 27MB– Storing routing tables,
counters and statistics
• RLDRAM-II– 288MB– Packet Buffering
• PCI Express x8– PC Interface
• Expansion Slot
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Xilinx Virtex 5 TX240T
• Optimized for ultra high-bandwidth applications
• 48 GTX Transceivers• 4 hard Tri-mode
Ethernet MACs• 1 hard PCI Express
Endpoint
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Beyond Hardware
• NetFPGA-10G Board• Xilinx EDK based IDE• Reference designs with
ARM AXI4• Software (embedded and
PC)• Public Repository
(GitHub)• Public Wiki
Reference DesignsReference Designs AXI4 IPsAXI4 IPs
Xilinx EDKXilinx EDK
MicroBlaze SWMicroBlaze SW PC SWPC SW
PBWorks, GitHub, User CommunityPBWorks, GitHub, User Community
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NetFPGA-1G Cube Systems
• PCs assembled from parts– Stanford University– Cambridge University
• Pre-built systems available – Accent Technology Inc.
• Details are in the Guidehttp://netfpga.org/static/guide.html
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Rackmount NetFPGA-1G Servers
NetFPGA inserts in PCI or PCI-X slot
2U Server (Dell 2950)
Thanks: Brian Cashman for providing machine
1U Server (Accent Technology Inc.)
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Stanford NetFPGA-1G Cluster
Statistics• Rack of 40
• 1U PCs with NetFPGAs
• Managed • Power• Console• LANs
• Provides 4*40=160 Gbps of full line-rate processing bandwidth
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Section III: Network review
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Internet Protocol (IP)
Data
DataIP
Hdr
Eth Hdr
DataIP
Hdr
Data to betransmitted:
IP packets:
EthernetFrames:
DataIP
HdrData
IP Hdr
Eth Hdr
DataIP
HdrEth Hdr
DataIP
Hdr
…
…
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Internet Protocol (IP)
Data
DataIP
Hdr…
16 3241
Options (if any)
Destination Address
Source Address
Header ChecksumProtocolTTL
Fragment OffsetFlagsFragment ID
Total Packet LengthT.ServiceHLenVer
20 b
ytes
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Basic operation of an IP router
R3
A
B
C
R1
R2
R4 D
E
FR5
R5F
R3E
R3D
Next HopDestination
D
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Basic operation of an IP router
A
B
C
R1
R2
R3
R4 D
E
FR5
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Forwarding tables
Entry Destination Port
12⋮ 232
0.0.0.00.0.0.1⋮
255.255.255.255
12⋮12
~ 4 billion entries
Naïve approach:One entry per address
Improved approach:Group entries to reduce table sizeEntry Destination Port
12⋮50
0.0.0.0 – 127.255.255.255128.0.0.1 – 128.255.255.255
⋮248.0.0.0 – 255.255.255.255
12⋮12
IP address 32 bits wide → ~ 4 billion unique address
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IP addresses as a line
0 232-1
Entry Destination Port
12345
StanfordBerkeley
North AmericaAsia
Everywhere (default)
12345
All IP addresses
North AmericaAsia
BerkeleyStanford
Your computer My computer
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Longest Prefix Match (LPM)
Entry Destination Port
12345
StanfordBerkeley
North AmericaAsia
Everywhere (default)
12345
Universities
Continents
Planet
DataTo:
Stanford
Matching entries:•Stanford•North America•Everywhere
Most specific
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Longest Prefix Match (LPM)
Entry Destination Port
12345
StanfordBerkeley
North AmericaAsia
Everywhere (default)
12345
Universities
Continents
Planet
DataTo:
Canada
Matching entries:•North America•Everywhere
Most specific
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Implementing Longest Prefix Match
Entry Destination Port
12345
StanfordBerkeley
North AmericaAsia
Everywhere (default)
12345
Most specific
Least specific
Searching
FOUND
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Basic components of an IP router
Control Plane
Data Planeper-packet processing
SwitchingForwarding
Table
Routing Table
Routing Protocols
Management& CLI
Softw
areH
ardware
Queuing
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IP router components in NetFPGA
SCONE
Routing Table
Routing Protocols
Management& CLI
Output PortLookup
ForwardingTable
InputArbiter
OutputQueues
Switching Queuing
Linux
Routing Table
Routing Protocols
Management& CLI
Router Kit
OR
Softw
areH
ardware
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Section IV: Example I
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Operational IPv4 router
Control Plane
Data Planeper-packet processing
Softw
areH
ardware
Routing Table
Routing Protocols
Management& CLI
SCONE
SwitchingForwarding
TableQueuing
Reference router
Java GUI
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Streaming video
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Streaming video
PC & NetFPGA(NetFPGA in PC)
NetFPGA runningreference router
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Streaming video
Video streaming over shortest path
Videoclient
Videoserver
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Streaming video
Videoclient
Videoserver
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Observing the routing tables
Columns:•Subnet address•Subnet mask•Next hop IP•Output ports
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Demo
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Review
NetFPGA as IPv4 router:•Reference hardware + SCONE software•Routing protocol discovers topology
Demo:•Ring topology•Traffic flows over shortest path•Broken link: automatically route around failure
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Section V: Example II
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Buffers in Routers
• Internal Contention
• Congestion
• Pipelining
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Buffers in Routers
Rx Rx
Rx Rx
Rx Rx
Tx Tx
Tx Tx
Tx Tx
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Extending the Reference Pipeline
MACRxQMACRxQ
CPURxQCPURxQ
MACRxQMACRxQ
CPURxQCPURxQ
MACRxQMACRxQ
CPURxQCPURxQ
MACRxQMACRxQ
CPURxQCPURxQ
Input ArbiterInput Arbiter
Output Port LookupOutput Port Lookup
MACTxQMACTxQ
CPUTxQCPUTxQ
MACTxQMACTxQ
CPUTxQCPUTxQ
MACTxQMACTxQ
CPUTxQCPUTxQ
MACTxQMACTxQ
CPUTxQCPUTxQ
Output QueuesOutput Queues
RateLimiterRate
Limiter
Event CaptureEvent Capture
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Topology
PC & NetFPGA(NetFPGA in PC)
NetFPGA runningextended reference router
nf2c2
eth1
nf2c1
eth2
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Demo
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Section V: Community Contributions
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FPGAFPGA
MemoryMemory
1GE1GE
1GE1GE
1GE1GE
1GE1GE
Running the Router Kit
User-space development, 4x1GE line-rate forwarding
PCI
CPUCPU MemoryMemory
OSPFOSPF BGPBGP
My ProtocolMy Protocoluser
kernelRouting
Table
Usage #1
IPv4RouterIPv4
Router
1GE1GE
1GE1GE
1GE1GE
1GE1GE
FwdingTable
FwdingTable
PacketBuffer
PacketBuffer
“Mirror”
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FPGAFPGA
MemoryMemory
1GE1GE
1GE1GE
1GE1GE
1GE1GE
Enhancing Modular Reference Designs
PCI
CPUCPU MemoryMemory
Usage #2
NetFPGA DriverNetFPGA Driver
Java GUIFront Panel(Extensible)
Java GUIFront Panel(Extensible)
PW-OSPFPW-OSPF
In QMgmtIn Q
Mgmt
IPLookup
IPLookup
L2Parse
L2Parse
L3Parse
L3Parse
Out QMgmtOut QMgmt
1GE1GE
1GE1GE
1GE1GE
1GE1GE
Verilog modules interconnected by FIFO interfaces
MyBlockMy
Block
VerilogEDA Tools
(Xilinx, Mentor, etc.)
VerilogEDA Tools
(Xilinx, Mentor, etc.)
1. Design2. Simulate3. Synthesize4. Download
1. Design2. Simulate3. Synthesize4. Download
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FPGAFPGA
MemoryMemory
1GE1GE
1GE1GE
1GE1GE
1GE1GE
Creating new systems
PCI
CPUCPU MemoryMemory
Usage #3
NetFPGA DriverNetFPGA Driver
1GE1GE
1GE1GE
1GE1GE
1GE1GE
My Design
(1GE MAC is soft/replaceable)
My Design
(1GE MAC is soft/replaceable)
VerilogEDA Tools
(Xilinx, Mentor, etc.)
VerilogEDA Tools
(Xilinx, Mentor, etc.)
1. Design2. Simulate3. Synthesize4. Download
1. Design2. Simulate3. Synthesize4. Download
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Section VI: What to do next?
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To get started with your project
1. Get familiar with hardware description languagehttp://www-netfpga.cl.cam.ac.uk/
Support provided by Redgate Software
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To get started with your project
2. Prepare for your project
b) Complete a hands-on tutorial
a) Learn NetFPGA by yourself
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Learn by Yourself
Users Guide
NetFPGA website (www.netfpga.org)
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Learn by Yourself
Developers Guide
NetFPGA website (www.netfpga.org)
Forums
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Attend (or host) a hands-on tutorial
Stanford
Cambridge
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Attend a hands-on tutorial
Events
NetFPGA website (www.netfpga.org)
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Section VII: Conclusion
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Conclusions
• NetFPGA Provides– Open-source, hardware-accelerated Packet Processing– Modular interfaces arranged in reference pipeline – Extensible platform for packet processing
• NetFPGA Reference Code Provides– Large library of core packet processing functions– Scripts and GUIs for simulation and system operation– Set of Projects for download from repository
• The NetFPGA Base Code– Well defined functionality defined by regression tests– Function of the projects documented in the Wiki Guide
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Nick McKeown, Glen Gibb, Jad Naous, David Erickson, G. Adam Covington, John W. Lockwood, Jianying Luo, Brandon Heller, Paul
Hartke, Neda Beheshti, Sara Bolouki, James Zeng, Jonathan Ellithorpe, Sachidanandan Sambandan, Eric Lo
Acknowledgments
NetFPGA Team at Stanford University (Past and Present):
NetFPGA Team at University of Cambridge (Past and Present):
Andrew Moore, David Miller, Muhammad Shahbaz, Martin Zadnik
All Community members (including but not limited to):
Paul Rodman, Kumar Sanghvi, Wojciech A. Koszek, Yahsar Ganjali, Martin Labrecque, Jeff Shafer,
Eric Keller , Tatsuya Yabe, Bilal Anwer,Yashar Ganjali, Martin Labrecque
Kees Vissers, Michaela Blott, Shep Siegel
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Special thanks to our Partners:
Other NetFPGA Tutorial Presented At:
SIGMETRICS
Ram Subramanian, Patrick Lysaght, Veena Kumar, Paul Hartke, Anna Acevedo
Xilinx University Program (XUP)
See: http://NetFPGA.org/tutorials/
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Thanks to our Sponsors:
• Support for the NetFPGA project has been provided by the following companies and institutions
Disclaimer: Any opinions, findings, conclusions, or recommendations expressed in these materials do not necessarily reflect the views of the National Science Foundation or of any other sponsors supporting this project.
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Tutorial Survey
www.netfpga.org/tutorial_survey.html
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Group Discussion• Your plans for using the NetFPGA
– Teaching– Research– Other
• Resources needed for your class– Source code– Courseware– Examples
• Your plans to contribute– Expertise – Capabilities– Collaboration Opportunities