Nectar F2F, Barcelona 2013-0904/19/23 K.-H. Sulanke, DESY 1

The Digital Trigger Backplane Rev. 2

power

ethernet

L0 in /out and ...connectors to neighbor clusters

RJ-45

RJ-45

Xilinx

FPGA

vreg

flash

24V

ethernetpower

CLKPPS

L0_triggertriggerIP_addrHV_ena

SPI / JTAGcalib_cycreserved

flashosc

clock (opt.+power)PPSL1_trigger_outL2_trigger_in

FE-board interface,compliant toFE_BP_interface_v6.d

oc by Gustavo M.

Nectar F2F, Barcelona 2013-0904/19/23 K.-H. Sulanke, DESY 2

Digital Trigger Backplane, cont.

Clock_inPPS_inL1_outL2_in

Hexadez.switches

local clock osc.

FE-boardGigabit ethernet

FPGA PROM

24VPower

DC-DC power supply

Xilinx JTAG conn.

64 bit ID ROM

FE-board connectors

50 pin flat cable

Xilinx FPGA

temp. sensor

Nectar F2F, Barcelona 2013-0904/19/23 DESY 3

The DTB-FPGA‘s Functionality

delay

delay

delay

delay

delay

delay

delay

37 pixeltriggerfabric

fanout

progr. delays

PLL

Xilinx Spartan 6 FPGA

trigger

pix_[0][6..0]

pix_[1][4..0]

pix_[6][4..0]

clock

from center cluster

from surrounding clusters

to surrounding clusters

pix*_[0][4..0]

calibrate STM

to L2_trigger board

FPGA

FPGA

FPGA

FPGA

FPGA

FPGA

FPGA

Nectar F2F, Barcelona 2013-0904/19/23 K.-H. Sulanke, DESY 4

Three New Boards DevelopedDigitalTriggerBackplane

L0Mezzanine

L0 Testboard

Nectar F2F, Barcelona 2013-0904/19/23 K.-H. Sulanke, DESY 5

The Cluster Service Board (CSB)

Backplane

connector

XilinxFPGA

vreg

flash

24VCLKPPSL2L3sdat

JTAG

Clock_PPS_24VGND

L1_triggerL3_trigger

RJ45

RJ45

RJ45

RJ45RJ45

RJ45

RJ45

RJ45

RJ45

RJ45

RJ45

RJ45RJ45

RJ45

RJ45

RJ45

Cur_mon 16 x switch16 xCat5ecable

sClock

PPSL1_triggerL3_trigger

Or optional,including

24V

Nectar F2F, Barcelona 2013-0904/19/23 K.-H. Sulanke, DESY 6

The Centralized Trigger Schema with L2

• L2 also based on Xilinx-Spartan 6 FPGAs

• L2 is a crate, ~ 50 x 20 x 20 cm, ~ 11 kg

– 18 x CSB (Cluster Service Board)

– 1 x L2CB (L2 Controller Board)

• Ethernet interface

• Optical / electrical camera trigger output

PMT = Photomultiplier TubeFEB = Frontend BoardDTB = Digital Trigger Backplane CSB = Cluster Service BoardL2CB = L2 Controller Board

L0FEB

DTB

FPGAPMT

L1 CSBL2

#01

…

#16L0FEB

FPGA

L1

Sector_trig

#01

…

#18FPGA

FPGA

Camera_trig

GPS_clock

PMT

ethernet

L2CB7 7

77

L0_neighbor

L0_neighbor

24V (optional)