Natalie Enright Jerger

ContactInformation

The Edward S. Rogers Department of Electrical Voice: (416) 978-5056and Computer Engineering Fax: (416) 971-232610 King’s College Rd E-mail: enright@ece.utoronto.caUniversity of Toronto Webpage: www.eecg.toronto.edu/~enrightToronto, ON M5S 3G4 Canada

Education University of Wisconsin, Madison, Wisconsin USAPh.D., Electrical Engineering, December 2008

Dissertation: “Chip Multiprocessor Coherence and Interconnect System Design”Advisors: Mikko H. Lipasti and Li-Shiuan Peh

M.S., Electrical and Computer Engineering, May 2004

Purdue University, West Lafayette, Indiana USAB.S., Computer Engineering, May 2002

Appointment University of Toronto, Electrical and Computer Engineering, Toronto, Ontario, CanadaProfessor July 2017 - PresentAssociate Professor July 2014 - July 2017Assistant Professor January 2009 - July 2014

ResearchInterests

Computer architecture, many-core architectures, approximate computing, on-chip networks, cachecoherence protocols, interconnection networks, emerging applications for many-core architectures.

IndustrialExperience

Advanced Micro Devices Visiting ScholarBellevue, WA July 2015-December 2016IBM InternRochester, MN June 2006 - Oct 2006Intel Intern, Microarchitecture Research LabSanta Clara, CA May 2004 - December 2004Hewlett Packard InternVancouver, WA May 2001 - August 2001Hewlett Packard InternVancouver, WA May 2000 - August 2000

Honors andAwards

McLean Senior Fellow, 2019Canada Research Chair in Computer Architecture, 2019ACM Distinguished Scientist, 2018Gordon R. Slemon Teaching of Design Award, 2017IEEE MICRO Top Picks Honorable Mention for “The Anytime Automaton”, 2017Percy Edward Hart Professor in Electrical and Computer Engineering, 2016-2019125 People of Impact from University of Wisconsin, Department of Electrical and Computer Engi-neering, 2016IEEE MICRO Top Picks from Computer Architecture for “Enabling Interposer-based Disintegrationof Multi-core Processors”, 2016

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Borg Early Career Award, 2015Sloan Research Fellow, 2015-2017IEEE MICRO Top Picks Honorable Mention for “NoC Architectures for Silicon Interposer System”, 2015Ontario Professional Engineers Young Engineer Medal, 2014Ministry of Research and Innovation Early Researcher Award, 2012IBM Ph.D. Fellowship, 2007, 2008Peter R. Schneider Distinguished Graduate Fellowship, University of Wisconsin-Madison, 2002University of Wisconsin Teaching Academy Future Faculty Partner, 2004-2008

PublicationsPeer-ReviewedConferences

[C1] Mayank Parasar, Natalie Enright Jerger, Paul Gratz, Joshua San Miguel and Tushar Kr-ishna, “SWAP: Synchronized Weaving of Adjacent Packets for Network Deadlock Prevention.”In Proceedings of the ACM/IEEE International Symposium on Microarchitecture (MICRO),October 2019.1

[C2] Hossein Farrokhbakht, Haid Mardani Kamali and Natalie Enright Jerger, “Muffin: Minimally-Buffered Zero-Delay Power-Gating Technique in On-Chip Routers.” In Proceedings of theACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July2019.

[C3] Karthik Ganesan, Joshua San Miguel and Natalie Enright Jerger. “The What’s NextIntermittent Computing Architecture.” In Proceedings of the IEEE International Symposiumon High Performance Computer Architecture (HPCA), 2019 (acceptance rate: 21%).

[C4] Joshua San Miguel, Karthik Ganesan, Mario Badr, Chunqiu Xia, Rose Li, HsuanHsiao, and Natalie Enright Jerger, “An Analytical Model for Early Design Space Explorationof Intermittent Processor Architectures.” In Proceedings of the ACM/IEEE InternationalSymposium on Microarchitecture (MICRO), October 2018 (acceptance rate: 21%).

[C5] Hossein Farrokhbakht, Hadi Mardani Kamali, Natalie Enright Jerger, and Shaahin Hessabi,“SPONGE: A Scalable Pivot-based On/Off Gating Engine for Reducing Static Power in NoCRouters.” In Proceedings of the ACM/IEEE International Symposium on Low Power Electronicsand Design (ISLPED), July 2018.

[C6] Jieming Yin, Zhifeng Lin, Onur Kayiran, Matthew Poremba, Muhammad Shoaib Bin Altaf,Natalie Enright Jerger and Gabriel H. Loh. “Modular Routing Design for Chiplet-based Systems.”In Proceedings of the IEEE/ACM International Symposium on Computer Architecture (ISCA),June 2018 (acceptance rate: 17%.).

[C7] Joshua San Miguel, Jorge Albericio, Natalie Enright Jerger and Aamer Jaleel. “TheBunker Cache for Spatio-Value Approximation.” In Proceedings of the IEEE/ACM InternationalSymposium on Microarchitecture (MICRO), October 2016 (acceptance rate: 22%).

[C8] Patrick Judd, Jorge Albericio, Tayler Hetherington, Tor Aamodt, Natalie EnrightJerger and Andreas Moshovos. “Proteus: Exploiting Numerical Precision Variability in DeepNeural Networks.” In Proceedings of the ACM International Conference on Supercomputing(ICS), 2016.

[C9] Jorge Albericio, Patrick Judd, Tayler Hetherington, Tor Aamodt, Natalie EnrightJerger and Andreas Moshovos. “Cnvlutin: Zero-Neuron-Free Deep Convolutional NeuralNetwork Computing.” In Proceedings of the IEEE/ACM International Symposium on ComputerArchitecture (ISCA), June 2016, pp. 1-13 (acceptance rate: 19%).

[C10] Joshua San Miguel and Natalie Enright Jerger. “The Anytime Automaton.” In Proceedingsof the IEEE/ACM International Symposium on Computer Architecture (ISCA), June 2016, pp.545-557 (acceptance rate: 19%).

1Student authors identified in bold.

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[C11] Zimo Li, Joshua San Miguel and Natalie Enright Jerger. “The Runahead Network-on-Chip.” In Proceedings of the IEEE International Symposium on High Performance ComputerArchitecture (HPCA), February 2016, pp. 333-344 (acceptance rate: 22%).

[C12] Jieming Yin, Onur Kayiran, Matthew Poremba, Natalie Enright Jerger and Gabriel H. Loh.“Efficient Synthetic Traffic Models for Large, Complex SoCs.” In Proceedings of the IEEEInternational Symposium on High Performance Computer Architecture (HPCA), February 2016,pp. 297-308 (acceptance rate: 22%).

[C13] Ajaykumar Kannan, Natalie Enright Jerger and Gabriel H. Loh. “Enabling Interposer-based Disintegration of Multi-core Processors” In Proceedings of the IEEE/ACM InternationalSymposium on Microarchitecture (MICRO), December 2015, pp. 546-558 (acceptance rate:21%).

[C14] Joshua San Miguel, Jorge Albericio, Andreas Moshovos and Natalie Enright Jerger.“Doppelganger: A Cache for Approximate Computing” In Proceedings of the IEEE/ACMInternational Symposium on Microarchitecture (MICRO), December 2015, pp. 50-61 (acceptancerate: 21%).

[C15] Gabriel H. Loh, Natalie Enright Jerger, Ajaykumar Kannan and Yasuko Eckert. “Interconnect-Memory Challenges for Multi-Chip, Silicon Interposer Systems” In Proceedings of the ACM Interna-tional Symposium on Memory Systems (MEMSYS), October 2015, pp. 3-10.

[C16] Robert Hesse and Natalie Enright Jerger. “Improving DVFS in NoCs with CoherencePrediction” In Proceedings of the IEEE/ACM International Symposium on Networks on Chip(NOCS), September 2015.

[C17] Joshua San Miguel and Natalie Enright Jerger. “Data Criticality in Network-on-Chip Design”In Proceedings of the IEEE/ACM International Symposium on Networks on Chip (NOCS),September 2015. (Best paper nominee).

[C18] Jorge Albericio, Joshua San Miguel, Natalie Enright Jerger and Andreas Moshovos.“Wormhole: Wisely predicting multidimensional branches.” In Proceedings of the IEEE/ACMInternational Symposium on Microarchitecture (MICRO), December 2014, pp. 509-520 (accep-tance rate: 19%).

[C19] Natalie Enright Jerger, Ajaykumar Kannan, Zimo Li and Gabriel H. Loh. “NoC Ar-chitectures for Silicon Interposer Systems.” In Proceedings of the IEEE/ACM InternationalSymposium on Microarchitecture (MICRO), December 2014, pp. 458-470 (acceptance rate:19%).

[C20] Joshua San Miguel, Mario Badr and Natalie Enright Jerger. “Load Value Approximation”In Proceedings of the IEEE/ACM International Symposium on Microarchitecture (MICRO),December 2014 (acceptance rate: 19%), pp. 127-139.

[C21] Haofan Yang, Jyoti Tripathi, Natalie Enright Jerger and Dan Gibson. “Dodec: Random-Link, Low-Radix On-Chip Networks.” In Proceedings of the IEEE/ACM International Sympo-sium on Microarchitecture (MICRO), December 2014 (acceptance rate: 19%), pp 496-508.

[C22] Andrew Bitar, Jeffrey Cassidy, Natalie Enright Jerger and Vaughn Betz. “Efficientand Programmable Ethernet Switching with a NoC-Enhanced FPGA.” In Proceedings of theACM/IEEE Symposium on Architectures for Networking and Communication Systems (ANCS),October 2014 (acceptance rate: 34%).

[C23] Wenbo Dai and Natalie Enright Jerger. “Sampling-based Approaches to Accelerating Network-on-Chip Simulation.” In Proceedings of the IEEE/ACM International Symposium on Networkson Chip (NOCS), September 2014 (acceptance rate: 26%).

[C24] Parisa Khadem Hamedani, Natalie Enright Jerger and Shaahin Hessabi. “QuT: A Low-Power All-Optical Architecture for a Next Generation of Network-on-Chip.” In Proceedingsof the IEEE/ACM International Symposium on Networks on Chip (NOCS), 2014 (acceptancerate: 26%).

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[C25] Goran Narancic, Patrick Judd, Di Wu, Islam Atta, Michel El Nacouzi, JasonZebchuk, Natalie Enright Jerger, Serag Gadelrab, Kyros Kutulakos, Andreas Moshovosand Jorge Albericio. “Evaluating Memory System Behavior of Smartphone Workloads.” InProceedings of the International Conference on Embedded Computer Systems: Architectures,Modeling and Simulation (SAMOS), 2014.

[C26] Mario Badr and Natalie Enright Jerger. “SynFull: Synthetic Traffic Models Capturing aFull Range of Cache Coherence Behaviour.” In Proceedings of the IEEE/ACM InternationalSymposium on Computer Architecture (ISCA), June 2014 (acceptance rate: 18%).

[C27] Tahir Diop, Steven Gurfinkel, Jason Anderson and Natalie Enright Jerger. “DistCL: AFramework for Distributed Execution of OpenCL Kernels.” In Proceedings of the IEEE Interna-tional Symposium on Modeling, Analysis and Simulation of Computer and TelecommunicationSystems (MASCOTS). August 2013 (acceptance rate: 27%).

[C28] John Matienzo and Natalie Enright Jerger. “Performance Analysis of Broadcasting Algo-rithms on the Intel Single Chip Cloud Computer.” In Proceedings of the IEEE InternationalSymposium on Performance Analysis of Systems and Software (ISPASS), April 2013, pp.163-172. (acceptance rate: 26%).

[C29] Michel El Nacouzi, Islam Atta, Myrto Papadopoulou, Jason Zebchuk, Natalie En-right Jerger and Andreas Moshovos. “A Dual-Grain Hit/Miss Detector for Large Stacked DieDRAM Caches.” In Proceedings of the Conference on Design, Automation and Test in Europe(DATE), March 2013, pp. 89-92. (acceptance rate: 36%).

[C30] Robert Hesse, Jeff Nicholls and Natalie Enright Jerger. “Fine-Grained Bandwidth Adap-tivity in Networks-on-Chip Using Bidirectional Channels.” In Proceedings of the IEEE/ACM6th International Network on Chip Symposium (NOCS), May 2012, pp. 132-141. (acceptancerate: 30%).

[C31] Sheng Ma, Natalie Enright Jerger and Zhiying Wang. “Whole Packet Forwarding: EfficientDesign of Fully Adaptive Routing Algorithms for Networks-on-Chip.” In Proceedings of the18th IEEE International Symposium on High Performance Computer Architecture (HPCA).Feb. 2012, pp. 467-479. (acceptance rate: 17%).

[C32] Sheng Ma, Natalie Enright Jerger and Zhiying Wang. “Supporting Efficient CollectiveCommunication in NoCs.” In Proceedings of the 18th IEEE International Symposium on HighPerformance Computer Architecture (HPCA). Feb. 2012, pp. 165-177. (acceptance rate:17%).

[C33] Parisa Khadem Hamedani, Shaahin Hessabi, Hamid Sarbazi-Azad and Natalie Enright Jerger.“Exploration of Temperature Constraints for Thermal Aware Mapping of 3D Networks on Chip.”In Proceedings of the 20th Euromicro International Conference on Parallel, Distributed, andNetwork-Based Processing (PDP). Feb. 2012, 499-506. (acceptance rate: 34%).

[C34] Sheng Ma, Natalie Enright Jerger, and Zhiying Wang. “DBAR: An Efficient RoutingAlgorithm to Support Multiple Concurrent Applications in Networks-on-Chip.” In Proceedingsof the 38th ACM/IEEE International Symposium on Computer Architecture (ISCA). June 2011,pp. 413-424. (acceptance rate: 19%).

[C35] Danyao Wang, Natalie Enright Jerger, and J. Gregory Steffan. “DART: A Programmable Ar-chitecture for NoC Simulation on FPGAs.” In Proceedings of the 5th IEEE/ACM InternationalNetwork on Chip Symposium (NOCS). May 2011, pp 145-152. (acceptance rate: 25%).

[C36] Natalie Enright Jerger. “SigNet: Network-on-Chip Filtering for Coarse Vector Directories.” InProceedings of the International Conference on Design Automation and Test in Europe (DATE).March 2010, pp. 1378-1383. (acceptance rate: 26%).

[C37] Mitch Hayenga, Natalie Enright Jerger and Mikko Lipasti. “SCARAB: A Single CycleAdaptive Routing and Bufferless Network.” In Proceedings of the 42nd IEEE/ACM InternationalSymposium on Microarchitecture (MICRO). New York, New York. Dec. 2009, pp. 244-254.(acceptance rate: 25%).

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[C38] Dennis Abts, Natalie Enright Jerger, John Kim, Dan Gibson, and Mikko Lipasti. “AchievingPredictable Performance through Better Memory Controller Placement in Many-Core CMPs.”In Proceedings of the 36th IEEE/ACM International Symposium on Computer Architecture(ISCA). June 2009, pp. 451-461. (acceptance rate: 20%).

[C39] Natalie Enright Jerger, Li-Shiuan Peh and Mikko H. Lipasti. “Virtual Tree Coherence: Lever-aging Regions and In-Network Multicast Trees for Scalable Cache Coherence.” In Proceedingsof the 41st IEEE/ACM International Symposium on Microarchitecture (MICRO). Nov. 2008,pp. 35-46. (acceptance rate: 19%).

[C40] Natalie Enright Jerger, Li-Shiuan Peh and Mikko H. Lipasti. “Virtual Circuit Tree Multicasting:A Case for On-Chip Hardware Multicast Support.” In Proceedings of the 35th IEEE/ACMInternational Symposium on Computer Architecture (ISCA). Beijing, China. June 2008, pp.229-240. (acceptance rate: 14%).

[C41] Natalie Enright Jerger, Li-Shiuan Peh and Mikko H. Lipasti. “Circuit-Switched Coherence.” InProceedings of the 2nd IEEE/ACM International Symposium on Networks on Chip(NOCS).April 2008, pp. 193-202. (acceptance rate: 32%).

[C42] Natalie Enright Jerger, Dana Vantrease and Mikko Lipasti. “An Evaluation of Server ConsolidationWorkloads for Multi-Core Designs.” In Proceedings of IEEE International Symposium on WorkloadCharacterization (IISWC). Sept. 2007, pp. 47-56. (acceptance rate: 40%).

[C43] Natalie Enright Jerger, Eric Hill, and Mikko Lipasti. “Friendly Fire: Understanding the Effectsof Multiprocessor Prefetches.” In Proceedings of IEEE International Symposium on PerformanceAnalysis of Systems and Software (ISPASS). March 2006, pp. 177-188. (acceptance rate: 30%).

PublicationsPeer-ReviewedJournals

[J1] Xia Zhao, Sheng Ma, Zhiying Wang, Natalie Enright Jerger and Lieven Eeckhout, “CD-Xbar:A Converge-Diverge Crossbar Network for High-Performance GPUs,” IEEE Transactions onComputers, accepted March 2019.

[J2] Mario Badr and Natalie Enright Jerger, “A High-Level Model for Exploring Multi-CoreArchitectures,” Elsevier Journal on Parallel Computing, 2018.

[J3] Andreas Moshovos, Jorge Albericio, Patrick Judd, Alberto Delmas Lascorz, SayehSharify, Zissis Poulos, Tayler Hetherington, Tor Aamodt and Natalie Enright Jerger,“Exploiting Typical Values to Accelerate Deep Learning,” IEEE Computer, vol. 51, no. 5, pp18-30, May 2018.

[J4] Andreas Moshovos, Jorge Albericio, Patrick Judd, Alberto Lascorz, Sayeh Sharify,Tayler Hetherington, Tor Aamodt, Natalie Enright Jerger, “Value-Based Deep LearningHardware Accelerators,” IEEE Micro, 2018.

[J5] Joshua San Miguel, Karthik Ganesan, Mario Badr, and Natalie Enright Jerger, “TheEH Model: Analytical Exploration of Energy-Harvesting Architectures,” IEEE ComputerArchitecture Letters, 2017.

[J6] Thierry Moreau, Joshua San Miguel, Mark Wyse, James Bornholt, Luis Ceze, NatalieEnright Jerger and Adrian Sampson, “A Taxonomy of Approximate Computing Techniques,”IEEE Embedded Systems Letters, 2017.

[J7] Patrick Judd, Jorge Albericio, Tayler Hetherington, Tor Aamodt, Natalie EnrightJerger, Raquel Urtasun and Andreas Moshovos. “Proteus: Exploiting Precision Variability inDeep Neural Networks.” Elsevier Journal on Parallel Computing, 2017.

[J8] Ajaykumar Kannan, Natalie Enright Jerger and Gabriel H. Loh. “Exploiting InterposerTechnologies to Disintegrate and Reintegrate Multi-core Processors.” IEEE Micro Top Picksfrom Computer Architecture, May-June 2016.

[J9] Sheng Ma, Zhiying Wang, Zonglin Liu and Natalie Enright Jerger. “Leaving One Slot Empty:Flit Bubble Flow Control for Torus Cache-coherent Networks-on-Chip.” IEEE Transactions onComputers, vol. 64, no. 3, pp. 763-777, March 2015.

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[J10] Sheng Ma, Zhiying Wang, Natalie Enright Jerger, Li Shen and Nong Xiao. “Novel FlowControl for Fully Adaptive Routing in Cache-coherent NoCs.” IEEE Transactions on Paralleland Distributed Computing, vol. 25, no. 9, pp. 2397-2407, September 2014.

[J11] Parisa Khadem Hamedani, Shaahin Hessabi, Hamid Sarbazi-Azad and Natalie EnrightJerger. Exploration of Temperature Constraints for Thermal Aware Mapping of 3D Networkson Chip. International Journal of Adaptive, Resilient and Autonomic Systems, Special issue onNetworked Embedded Systems, vol, 4, no. 3, pp. 42-60, July-September 2013

[J12] Sheng Ma, Natalie Enright Jerger, Zhiying Wang, Mingche Lai, and Libo Huang. HolisticRouting Algorithm Design to Support Workload Consolidation in NoCs. IEEE Transactionson Computers, vol. 63, no. 3, pp. 529-542, March 2014.

[J13] Danyao Wang, Charles Lo, Jasmina Vasiljevic, Natalie Enright Jerger and J. GregorySteffan. DART: A Programmable Architecture for NoC Simulation on FPGAs. IEEE Transac-tions on Computers, vol. 63, no. 3, pp. 664-678, March 2014.

[J14] Matthew Misler and Natalie Enright Jerger. Moths: Mobile Threads for On-Chip Networks.In ACM Transactions on Embedded Computing. (manuscript submitted: March 2011, revised:August 2011, accepted: December 2011, published: March 2013).

[J15] Radu Marculescu, Umit Ogras, Li-Shiuan Peh, Natalie Enright Jerger and Yatin Hoskote.Outstanding Research Problems in NoC Design: Circuit-, Microarchitecture- and System-LevelPerspective. In IEEE Transactions on Computer-Aided Design, vol. 28, no. 1, pp. 3-21, 2009.(Most downloaded article in Transactions on Computer-Aided Design of 2009.)

[J16] Natalie Enright Jerger, Mikko Lipasti and Li-Shiuan Peh. Circuit-Switched Coherence. IEEEComputer Architecture Letters, vol. 6, no. 1, Mar. 2007.

[J17] Elizabeth M. O’Callaghan and Natalie Enright Jerger. Women and Girls in Science andEngineering: Understanding the Barriers to Recruitment, Retention and Persistence across theEducational Trajectory. Journal of Women and Minorities in Science and Engineering, vol. 12,no. 2-3, pp. 209–232, 2006.

PublicationsBook

[P1] Natalie Enright Jerger, Joshua San Miguel, “Approximate Cache Architectures”, In ApproximateCircuits and Methodologies, Springer, 2018, p. 18.

[P2] Natalie Enright Jerger, Tushar Krishna and Li-Shiuan Peh. “On-Chip Networks, 2nd Edition”,Synthesis Lecture in Computer Architecture. (Editor: Margaret Martonosi). Morgan &Claypool Publishers. June 2017, 212 pages.

[P3] Natalie Enright Jerger and Li-Shiuan Peh. “On-Chip Networks”, Synthesis Lecture in ComputerArchitecture. (Editor: Mark Hill). Morgan & Claypool Publishers. July 2009, 142 pages.(downloaded over 4700 times as of December 2016).

PublicationsRefereedWorkshop &Posters

[P4] Karthik Ganesan, Joshua San Miguel and Natalie Enright Jerger, “The What’s NextComputing Architecture,” Workshop on Approximate Computing Across the Stack, 2018.

[P5] Mario Badr and Natalie Enright Jerger, “On the Evaluation of Computer Architectures,”Proceedings of the Second Workshop on Pioneering Processor Paradigms, 2018.

[P6] Mario Badr and Natalie Enright Jerger, “Fast and Accurate Performance Analysis of Syn-chronization.” Proceedings of the 9th International Workshop on Programming Models andApplications for Multicores and Manycores, 2018.

[P7] Mark Sutherland and Natalie Enright Jerger. “Near Data Processing at Runtime.” 1stInternational Workshop on Architecture for Graph Processing, 2017.

[P8] Robert Hesse and Natalie Enright Jerger. “Hierarchical Clustering for On-Chip Networks”.1st International Workshop on Advanced Interconnect Solutions and Technologies for EmergingComputing Systems, 2016.

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[P9] Patrick Judd, Jorge Albericio, Tayler Hetherington, Tor Aamodt, Natalie EnrightJerger and Andreas Moshovos. “Proteus: Exploiting Numerical Precision Variability in DeepNeural Networks.” 2nd Workshop on Approximate Computing, 2016.

[P10] Mark Sutherland, Joshua San Miguel, Natalie Enright Jerger. “Texture Cache Approximationon GPUs.” Workshop on Approximate Computing Across the Stack, 2015.

[P11] Ajaykumar Kannan, Mario Badr, Parisa Khadem Hamedani, Natalie Enright Jerger.“Offloading to the GPU: An Objective Approach.” In the 3rd Annual Workshop on Parallelismin Mobile Platforms, 2015.

[P12] Mark Sutherland, Ajaykumar Kannan, Natalie Enright Jerger. “Not quite my tempo:Matching Prefetches to Memory Access Time.” In Workshop for 2nd Data Prefetching Compe-tition, 2015.

[P13] Jorge Albericio, Joshua San Miguel, Natalie Enright Jerger and Andreas Moshovos.“Wormhole Branch Prediction Using Multi-dimensional Histories.” In the 4th ChampionshipBranch Prediction Workshop, 2014.

[P14] Joshua San Miguel and Natalie Enright Jerger. “Load Value Approximation: Approachingthe Ideal Memory Access Latency” Workshop on Approximate Computing Across the SystemStack (WACAS), 2014.

[P15] Tahir Diop, Natalie Enright Jerger and Jason Anderson. “Power Modeling for HeterogeneousProcessors.” Workshop on General Purpose Processing using GPUs, 2014.

[P16] Wenbo Dai and Natalie Enright Jerger. “Accelerating Network-on-Chip Simulation viaSampling”. In International Symposium on Performance Analysis of Systems and Software(poster). March 2014.

[P17] Sam Vafaee and Natalie Enright Jerger. “C++ Front-End for Distributed TransactionalMemory.” In the Intel Symposium on Single-Chip Cloud Computing. March 2011

[P18] Matthew Misler and Natalie Enright Jerger. “Moths: Mobile Threads for On-Chip Network”, IntlConf. on Parallel Architectures and Compilation Techniques (poster). Sept 2010.

[P19] Danyao Wang, Natalie Enright Jerger, J. Gregory Steffan. “DART: Fast and Flexible NoCSimulation Using FPGAs,” 5th Annual Workshop on Architectural Research Prototyping, June2010.

PublicationsNon-Reviewed

[P20] Daniel J. Sorin and Natalie Enright Jerger, “Save IEEE Computer Architecture Letters.”Computer Architecture Today (Editor: Alvin Lebeck), July 16, 2019, https://www.sigarch.org/save-ieee-computer-architecture-letters/.

[P21] Natalie Enright Jerger and Kelly Shaw, “Chilly Climate in Computer Architecture?,” ComputerArchitecture Today (Editor: Alvin Lebeck), August 23, 2018, https://www.sigarch.org/chilly-climate-in-computer-architecture/.

[P22] Natalie Enright Jerger, David Kaeli, Christos Kozyrakis, Gabriel Loh, Thomas Wenisch, DavidWood, “R2: The Future of ISCA, or not,” Computer Architecture Today (Editor: AlvinLebeck), May 31, 2018, https://www.sigarch.org/r2-the-future-of-isca-or-not/.

[P23] Natalie Enright Jerger, “Welcome to the Women in Computer Architecture (WICARCH)community,” Computer Architecture Today (Editor: Alvin Lebeck), May 7, 2018, https://www.sigarch.org/welcome-to-the-women-in-computer-architecture-wicarch-community/.

[P24] Natalie Enright Jerger and Kim Hazelwood, “Gender Diversity in Computer Architecture,”Computer Architecture Today (Editor: Alvin Lebeck), September 28, 2017, https://www.sigarch.org/gender-diversity-in-computer-architecture/.

[P25] Patrick Judd, Jorge Albericio, Tayler Hetherington, Tor Aamodt, Natalie EnrightJerger, Raquel Urtasun and Andreas Moshovos, “Reduced-Precision Strategies for BoundedMemory in Deep Neural Nets”, Tech report, 2015.

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[P26] Natalie Enright Jerger, “Explaining Parallel Architecture Design”, Book Review: ParallelComputer Organization and Design, Computing in Science and Engineering, 2013.

[P27] Natalie Enright Jerger and Mikko Lipasti, “Systems for Very Large-Scale Computing,” IEEEMICRO Special Issue (guest editors’ introduction), Vol. 31, No. 3, pp. 4-7, 2011.

PublicationsPatent

[P28] Natalie D. Enright2, Jamison Collins, Perry Wang, Hong Wang, Xinmin Tran, John Shen,Gad Sheaffer, Per Hammarlund. Mechanism to exploit synchronization overhead to improvemultithread performance. Patent no: 7487502. Sept 2009. Assignee: Intel Corporation.

SoftwareArtifactsReleased

DART: An FPGA Network-on-Chip Simulation Acceleration EngineReleased: May 2011Downloads to date: 341.

DistCL: A Framework for Distributed Execution of OpenCL KernelsReleased: August 2013Downloads to date: 84.

Power Modeling for Heterogeneous Processors FrameworkReleased: April 2014Downloads to date: 26.

SynFull: Synthetic Traffic Models Capturing Cache Coherent BehaviourReleased: May 2014Downloads to date: 146.

Invited Talks Architecting Chiplet-based SystemsCS Distinguished Lecture, Purdue University, October 2019Carnegie Mellon University, August 2019Keynote at International Conference on Parallel Architectures and Compilation Techniques(PACT), November 2018

Error-Efficient Architectures for Machine LearningECE Distinguished Lecture, Ohio State University, April 2019

Rapid Design Space Exploration of Interconnection NetworksInvited Talk at Workshop on Modeling and Simulation of Systems and Applications, August 2018

Architectural Techniques to Efficiently Handle Big Data ChallengesPrinceton University, January 2018

Hardware Software Co-Design for Approximate ComputingBrown University, October 2017

Exploiting Approximate Value LocalityAMD Research, July 2015

Energy-Efficient Communication in Many-Core ArchitecturesAMD (Markham), August 2015University of Rochester, October 2014

Accelerating Network-on-Chip Simulation with SynFull2Issued under maiden name

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PACT 2014 Tutorial: Advanced Design, Analysis and Verification of NoC Architectures

Designing High Performance, Energy-Efficient Networks-on-ChipUniversity of Wisconsin-Madison, November 2013Google (Madison), November 2013

Optimizations for Cache-Coherent Networks-on-ChipUniversity of Washington, April 2013AMD Research, April 2013MIT, April 2013Texas A&M University, March 2013Cornell University, March 2013University of Illinois, March 2013University of Michigan, February 2013Northwestern University, January 2013

Accelerating Many-Core Network-on-Chip SimulationIntel Corporation, January 2014Intel Corporation, January 2013

Reactive Coherence-based Traffic ModelsIntel Corporation, January 2012

Towards Application-Aware Network-on-Chip ArchitecturesMcMaster University, March 2012Intel Corporation, November 2011IBM T.J. Watson, June 2011University of Waterloo, ECE Department, March 2011Qualcomm, November 2010

On-Chip Network Research: Opportunities to Leverage Platform 2012Research Workshop on STMicroelectronics Platform 2012 (organized by CMC Microsystems),November 2010

Outstanding Research Challenges in On-Chip NetworksAltera Corporation, Toronto ON, June 2009.

Virtual Tree Coherence: Leveraging Regions and In-Network Multicast Trees for Scal-able Cache Coherence

International Symposium on Microarchitecture, November 2008.12th Annual Wisconsin Architecture Industrial Affiliates Meeting, October 2008.Gigascale Systems Research Center, Quarterly Concurrent Theme Meeting, June 2008.

Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast SupportInternational Symposium on Computer Architecture, June 2008

Harnessing Computing Power through CommunicationComputer Science and Engineering Colloquium, Washington University in St. Louis, April 2008Computer Engineering Group, University of Toronto, March 2008

Virtual Proximity: Interconnect Support for Flexible Scheduling of Server Consolida-

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tion Workloads in CMPsIBM Research Triangle Park, October 200711th Annual Wisconsin Architecture Industrial Affiliates Meeting, October 2007

An Evaluation of Server Consolidation Workloads for Multi-Core DesignsIEEE International Symposium on Workload Characterization, Boston MA, September 2007

Circuit-Switched Coherence2nd Annual IEEE Network on Chip Symposium, April 200810th Annual Wisconsin Architecture Industrial Affiliates Meeting, October 2006IBM Austin Research Lab, October 2006

Friendly Fire: Understanding the Effects of Multiprocessor PrefetchesIEEE Symposium on Performance Analysis of Systems and Software, March 20068th Annual Wisconsin Architecture Industrial Affiliates Meeting, October 2004

Press “How Chip Makers Are Circumventing Moore’s Law to Build Super-Fast CPUs of Tomorrow” https://gizmodo.com/how-chip-makers-are-circumventing-moores-law-to-build-s-1831268322

“Inside AMD’s Quest to Build Chips That Can Beat Intel”https://gizmodo.com/inside-amds-quest-to-build-chips-that-can-beat-intel-1824064984

Funding andSupport

McLean Senior Fellow 2019Source of support: University of Toronto (sole PI)Total amount: $125,000Annual amount: $125,000Annual amount/PI: $125,000

Canada Research Chair in Computer Architecture 2019-2024Source of support: Canada Research Chairs (sole PI)Total amount: $500,000Annual amount: $100,000Annual amount/PI: $100,000

Design exploration of an ASIC for Blockchain Processing 2019Source of support: NSERC Engage Grant (sole PI)Total amount: $25,000Annual amount: $25,000Annual amount/PI: $25,000

NSERC COHESA: Computing Hardware for Emerging Intelligent Sensory Applica-tions 2017-2022Source of support: Natural Science and Engineering Research Council, Strategic Network Grant(co-PI, PI: Andreas Moshovos)Total amount: $5,500,000Annual amount: $1,100,000Annual amount/PI: $55,000

Percy Edward Hart Chair 2016Source of support: University of Toronto (sole PI)Total amount: $225,000Annual amount: $75,000Annual amount/PI: $75,000

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Sloan Research Fellowship 2015Source of support: Alfred P. Sloan Foundation (sole PI)Total amount: $50,000 (USD)Annual amount: $25,000 (USD)Annual amount/PI: $25,000 (USD)

Power and Performance Characterization of Embedded GPUs 2014Source of support: NSERC Engage Grant (sole PI)Total amount: $25,000Annual amount: $25,000Annual amount/PI: $25,000

Intelligently Orchestrating Communication in Many-Core Architectures 2014Source of support: Natural Sciences and Engineering Research Council, Discovery (sole PI)Total amount: $186,000Annual amount: $31,000Annual amount/PI: $31,000

Evaluation of Direct Interconnect Architectures for Datacenters 2013Source of support: Natural Sciences and Engineering Research Council, Engage Grant (sole PI)Total amount: $25,000Annual amount: $25,000Annual amount/PI: $25,000

Power-Efficient Heterogeneous Architectures 2012Source of support: Ontario Centres of Excellence (OCE) and AMD (PI w/ J. Anderson)Total amount: $25,000 (OCE) + $20,000 (AMD)Annual amount: $45,000Annual amount/PI: $22,500

High Performance Many-Core Architectures and Interconnection Networks 2012-2017Source of support: Ministry of Research and Innovation, Early Researcher Award (sole PI)Total amount: $140,000Annual amount: $28,000Annual amount/PI: $28,000

Data Supply Architectures for Smartphone and Tablet Devices 2011-2014Source of support: Natural Sciences and Engineering Research Council, Collaborative Researchand Development Grant (co-PI w/ A. Moshovos and T. Aamodt (UBC))Total amount: $171,212Annual amount: $57,070Annual amount/PI: $19,023

Data Supply Architectures for Smartphone and Tablet Devices 2011-2014Source of support: Qualcomm (co-PI w/ A. Moshovos and T. Aamodt (UBC))Total amount: $150,000Annual amount: $50,000Annual amount/PI: $16,667

Developing, Analyzing and Accelerating Smartphone Workloads 2011-2014Source of support: Natural Science and Engineering Research Council (co-PI w/ A. Moshovosand K. Kutulakos)Total amount: $507,590Annual amount: $169,196Annual amount/PI: $56,399

On-Chip Networks to Enable Exascale Computing 2011-2012Source of support: Connaught New Researcher Award (sole PI)Total amount: $50,000

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Annual amount: $25,000Annual amount/PI: $25,000

Next Generation FPGA Platforms 2011-2013Source of support: Fujitsu Labs (co-PI w/ A. Sheikholeslami and J. Anderson)Total amount: $297,000Annual amount: $148,500Annual amount/PI: $49,500

Early-Stage Coherence Modeling for On-Chip Network Performance & Power Analysis2011-2014Source of support: Intel University Research Office (sole PI)Total amount: $171,000 (USD)Annual amount: $57,000 (USD)Annual amount/PI: $57,000 (USD)

Applications Exploiting Heterogeneous Processor Architectures for Improved Through-put and Energy-Efficiency 2011Source of support: Natural Sciences and Engineering Research Councile, Engage Grant (PI w/J. Anderson)Total amount: $24,940Annual amount: $24,940Annual amount/PI: $12,470

Multi-core applications, architectures and algorithms for complex systems 2011-2016Source of support: Canadian Foundation for Innovations (co-PI w/ Z. Tate and J. Anderson)Total amount: $291,789Annual amount: $58,357Annual amount/PI: $19,452

Multi-core applications, architectures and algorithms for complex systems 2011-2016Source of support: Ministry of Research and Innovation, Ontario Research Fund (co-PI, w/ Z.Tate and J. Anderson)Total amount: $291,785Annual amount: $58,356Annual amount/PI: $19,452

Heterogeneous Multi-Core Architectures 2010Source of support: AMD (PI w/ J. Anderson)Total amount: $20,000 + Donation of 2 ATI Graphics CardsAnnual amount: $20,000Annual amount/PI: $10,000

Exploiting Efficient Communication in the SCC 2010Source of support: Intel Corporation (PI w/ G. Steffan)In-Kind Contribution: Access to the Intel Single-Chip Cloud Computer (consists of 48 IA-32cores on a single die with 4 memory controllers and a 4×6 mesh on-chip network)

Hybrid NoC/Crossbar Designs for SoC Fabrics 2010Source of support: Natural Sciences and Engineering Research Council, Engage Grant (sole PI)Total amount: $23,580Annual amount: $23,580Annual amount/PI: $23,580

Integrated Photonics for Energy-Efficient Multi-Core Processors 2010-2013Source of support: Natural Science and Engineering Research Council, Strategic Project Grant(co-PI w/ J. Poon, A. Moshovos, A. Leon-Garcia)Total amount: $533,100Annual amount: $177,700Annual amount/PI: $44,425

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Semantically Rich Networks for Many-Core Architectures 2009-2014Source of support: Natural Sciences and Engineering Research Council, Discovery (sole PI)Total amount: $135,000Annual amount: $27,000Annual amount/PI: $27,000

Communication-centric Many-Core Computing Architectures 2009Source of support: Connaught Fund (sole PI)Total amount: $10,000Annual amount: $10,000Annual amount/PI: $10,000

Start-Up Funds 2009Source of support: University of Toronto (sole PI)Total amount: $100,000

Teaching Instructor ratings below refer to the “Overall Rating as an Instructor” question on the anonymouscourse evaluations filled out by students at the end of the semester.

ECE253 – Digital and Computer Systems 2019

– A second year EngSci course on digital logic, assembly language and computer organization.– Fall 2019 enrollment: –; Instructor rating: –/5 (Dept. average: –/5).

ECE342 – Computer Hardware 2017-2019

– Course covers arithmetic circuits, digital system design, asynchronous logic, testing of logiccircuits.

– Winter 2019 enrollment: 74; Instructor rating: 4.4/5 (Dept. average: 3.9/5).– Winter 2018 enrollment: 87; Instructor rating: 3.7/5 (Dept. average: 3.6/5).– Winter 2017 enrollment: 94; Instructor rating: 3.8/5 (Dept. average: 3.8/5).

ECE1755 – Parallel Computer Architecture and Programming 2017-2019

– Course covers topics in parallel architecture including cache coherence, memory consistency,interconnection networks, etc.

– Winter 2019 enrollment: 12; Instructor rating: 4.8/5 (Dept. average: 4.2/5).– Winter 2018 enrollment: 22; Instructor rating: 3.8/5 (Dept. average: 4.1/5).– Winter 2017 enrollment: 13; Instructor rating: 4.6/5 (Dept. average: 4.4/5).

ECE552 – Computer Architecture 2009-2014, 2018-2019

– Course covers traditional and advanced topics on computer architecture: pipelining, caches,dynamic scheduling, multiprocessors and multi-threading.

– Fall 2019 enrollment: –; Instructor rating: –/5 (Dept. average: –/5).– Fall 2018 enrollment: 70; Instructor rating: 4.6/5 (Dept. average: 3.9/5).– Fall 2014 enrollment: 90; Instructor rating: 4.5/5 (Dept. average: 3.9/5).– Fall 2013 enrollment: 90; Instructor rating: 4.6/5 (Dept. average: 3.8/5).– Fall 2012 enrollment: 85; Instructor rating: 6.33/7 (Dept. average: 5.72/7).– Fall 2011 enrollment: 69; Instructor rating: 6.07/7 (Dept. average: 5.86/7).– Fall 2010 (as ECE452/1718) enrollment: 82; Instructor rating: 5.62/7 (Dept. average: 5.79/7).– Fall 2009 (as ECE452) enrollment: 34; Instructor rating: 4.61/7 (Dept. average: 5.74/7).

ECE352 – Computer Organization 2017

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– Course covers arithmetic circuits, digital system design, assembly language programming,I/O interfaces, processor design, memory systems.

– Fall 2017 enrollment: 51; Instructor rating: 4.1/5 (Dept. average: 3.9/5).

ECE243 – Computer Organization 2011-2015

– A second year course on assembly language and computer organization.– Winter 2015 enrollment: 117; Instructor rating: 4.1/5 (Dept. average: 3.8/5).– Winter 2014 enrollment: 90; Instructor rating: 4.1/5 (Dept. average: 3.6/5).– Winter 2013 enrollment: 114; Instructor rating: 6.00/7 (Dept. average: 5.61/7).– Winter 2012 enrollment: 110; Instructor rating: 5.62/7 (Dept. average: 5.61/7).– Winter 2011 enrollment: 91; Instructor rating: 5.44/7 (Dept. average: 5.71/7).

ECE1749 – Interconnection Networks for Parallel Computer Architectures 2010-2014

– Course covers fundamental concepts related to interconnection networks: topology, routingalgorithms, flow control and router microarchitecture. The course also exposes studentsto cutting-edge research in this field.

– Fall 2014 enrollment: 8; Instructor rating: 4.1/5 (Dept. average: 4.2/5).– Spring 2014 enrollment: 8; Instructor rating: 5.92/7 (Dept. average: 6.14/7).– Fall 2012 enrollment: 24; Instructor rating: 5.92/7 (Dept. average: 6.14/7).– Fall 2011 enrollment: 21; Instructor rating: 6.52/7 (Dept. average: 6.09/7).– Winter 2011 enrollment: 10; Instructor rating: 6.60/7 (Dept. average: 6.23/7).– Winter 2010 enrollment: 8; Instructor rating: 6.75/7 (Dept. average: 6.07/7).

StudentSupervision

Graduated Ph.D. Students

Wenbo Dai 9/2011 – 7/2017Thesis: Network Improvement and Evaluation in Datacenters andChip-MultiprocessorsFirst Employment: Intel

Robert Hesse 8/2009 – 12/2015Thesis: Fine-Grained Adaptivity For Dynamic On-Chip NetworksFirst Employment: Intel

Parisa Khadem Hamedani 1/2012 – 4/2017Thesis: Improving Communication in Chip Multiprocessors UsingEmerging Technologies and Machine LearningFirst Employment: Intel

Joshua San Miguel 5/2012 – 8/2017Thesis: Reading Between the Bits: Uncovering New Insights inData for Efficient Processor DesignFirst Employment: Assistant Professor, University of Wisconsin-Madison

Graduated M.A.Sc. Students

Mario Badr 5/2011 – 1/2014Thesis: Synthetic Traffic Models That Capture Cache Coherent BehaviourFirst Employment: PhD student, University of Toronto

Tahir Diop 9/2011 – 9/2013Co-supervised ∼50% by Prof. J. Anderson

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Thesis: Regression Modelling of Power Consumption for Heterogeneous ProcessorsFirst Employment: Software engineer, TXIO

Kai Feng 9/2010 – 9/2012Thesis: Quality-of-Service for NoC-based Smartphone/Tablet Systems-on-ChipFirst Employment: China Electronics Corporation

Karthik Ganesan 1/2016 – 1/2018Thesis: Sporadic: An Anytime Architecture for Intermittent ComputingFirst Employment: PhD student, University of Toronto

Steven Gurfinkel 5/2011 – 4/2014Co-supervised ∼50% by Prof. J. AndersonThesis: The Distribution of OpenCL Kernel Execution Across Multiple DevicesFirst Employment: Engineer, NVIDIA

Ajaykumar Kannan 9/2013 – 9/2015Thesis: Enabling Interposer-Based Disintegration of Multi-Core ProcessorsFirst Employment: Engineer, Altera

Zimo Li 9/2013 – 9/2016Thesis: The Runahead Network on ChipFirst Employment: Engineer, Amazon

Matthew Misler 1/2009 – 6/2010Thesis: An Exploration of On-Chip Network Based Thread MigrationFirst Employment: IT Analyst, TD Bank Financial Group

Mark Sutherland 9/2014 – 8/2016Thesis: Co-Locating Code and Data for Energy-Efficient CPUsFirst Employment: PhD Student, EPFL

Danyao Wang 1/2009 – 9/2010Co-supervised ∼50% by Prof. J. G. SteffanThesis: DART: An FPGA-based Accelerator Platform for Network-on-Chip SimulationFirst Employment: Software Engineer, Google

Haofan Yang 9/2011 – 9/2013Thesis: Dodec: A Random-Link Approach for Low-Radix On-Chip NetworksFirst Employment: Engineer, NVIDIA

Post-Doctoral Researchers

Jorge Albericio Latorre 7/2013 – 8/2016Co-supervised ∼50% by Prof. A. MoshovosTopic: Hardware Acceleration for Machine LearningFirst Employment: NVIDIA

Current Ph.D. Students

Mario Badr 1/2014 – PresentTopic: New Tools for Evaluating Parallel and Heterogeneous Architectures

Shehab Elsayed 9/2012 – PresentTopic: Quality of Service for Smartphone Networks-on-Chip

Hossein Farrokbakht 9/2018 – PresentTopic: Efficient Deadlock Avoidance in NoCs

Karthik Ganesan 1/2018 – PresentTopic: Energy Harvesting IoT Architectures

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Current M.A.Sc. Students

Kamran Hasan 7/2018 – PresentTopic: Security for Machine Learning Accelerators

Henry Kao 9/2017 – PresentTopic: Coherence optimization

Victor Kariofillis 9/2017 – PresentTopic: Cache compression

Rose Li 9/2017 – PresentTopic: Evaluation of Intermittent Computing Architectures

Evey Liu 1/2019 – PresentTopic: Architectures for Distributed Machine Learning

Farhad Yusufali 9/2019 – PresentTopic: Approximate Computing

Visiting International Ph.D. Students

Thierry Moreau 9/2015 – 7/2016Current Position: PhD Student, University of Washington

Sheng Ma 9/2010 – 9/2012Current Position: Assistant ProfessorNational University of Defense Technology, China

M.Eng. Students Supervised

Remi Dufour 1/2013 – 9/2013Topic: Multi-core Prefetching AlgorithmsCurrent Position: Apple

Xiaoyin Liu 1/2012 – 6/2012Topic: Simulation Visualization for Networks-on-Chip

John Matienzo 1/2012 – 10/2012Topic: Optimized Broadcast Algorithms for the Intel SCCCurrent Position: Apple

Undergraduate Research Students

Sophie Mao (NSERC Undergraduate Summer Research Award) 5/2019 – 8/2019Charley Xu (NSERC Undergraduate Summer Research Award) 5/2019 – 8/2019Steven Xia 5/2018 – 8/2018Ziang (Bill) Xing (University of Toronto Excellence Award) 5/2013 – 8/2013Victor Zhang (NSERC Undergraduate Summer Research Award) 5/2012 – 8/2012Md Hasan Imam 5/2012 – 8/2012Daniel Lee 5/2011 – 8/2011Yifei Liu (ECE Entrance Research Award) 5/2011 – 8/2011Jeff Nicholls (NSERC Undergraduate Summer Research Award) 5/2011 – 8/2011

Current Position: M.A.Sc. student, University of TorontoJyoti Tripathi 5/2011 – 8/2011Camille Wingson 5/2011 – 8/2011Tian Fang Yu 5/2011 – 8/2011Victor Feng (NSERC Undergraduate Summer Research Award) 5/2010 – 8/2010Ruolong Lian (NSERC Undergraduate Summer Research Award) 5/2010 – 8/2010

Current Position: M.A.Sc. student, University of Toronto

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Thierry Moreau (NSERC Undergraduate Summer Research Award) 5/2009 – 8/2009Current Position: Ph.D. student, University of Washington

Graduate Student PhD Defence CommitteesAlex Rodionov (Supervisor: Jonathan Rose), 2019Mostafa Mahmoud (Supervisor: Andreas Moshovos), 2019Patrick Judd (Supervisor: Andreas Moshovos), 2018Myrto Papadopoulou (Supervisor: Andreas Moshovos), 2017Jasmina Vasiljevic (Supervisor: Paul Chow), 2017Henry Wong (Supervisors: Vaughn Betz and Jonathan Rose), 2017Mohammed Abdelfattah (Supervisor: Vaughn Betz), 2016Islam Atta (Supervisor: Andreas Moshovos), 2015Marcel Gort (Supervisor: Jason Anderson), 2014Jason Zebchuk (Supervisor: Andreas Moshovos), 2013Ioana Burcea (Supervisor: Andreas Moshovos), 2012Utku Aydonat (Supervisor: Tarek Abdelrahman), 2011Peter Yiannacouras (Supervisors: Jonathan Rose and Greg Steffan), 2009

Mentoringand Outreach

Panelist“After Tenure”, MIT EECS Rising Stars Workshop, October 2018.“Work-Life Balance”, hosted by the University of Toronto Prospective Professor in TrainingProgram, March 2018.“3rd year review and tenure process”, workshop organized by the Office of the Vice-Provost,University of Toronto, 2015.“Career Workshop for Women and Minorities in Computer Architecture”, held in conjunctionwith MICRO, 2014.“Academia and Industry Crossroads” at the University of Toronto ECE Connections Symposium,2014.“Being an Engineering Professor” hosted by the University of Toronto Prospective Professor inTraining Program, April 2013.“What if... You Thrived on the Tenure Track?” at Grace Hopper Celebraton of Women inComputing, 2011.“Campus visit, interview and more” at Positioning Yourself for a Career in Academia hosted bythe Status of Women Office at the University of Toronto, April 2010.

Chair: Women in Computer Architecture Group (WICARCH), 2011-PresentInternational membership consisting of professors, industry researchers and students in the field ofcomputer architecture.Organize annual networking events at major computer architecture conferences (ISCA and MI-CRO).Organize monthly webinar featuring prominent and emerging female researchers in computerarchitecture.Run online mentoring and community-building platform.http://www.sigarch.org/wicarch

ECE Representative: Girls Leadership in Engineering Experience (GLEE) Dinner for prospectiveundergraduate students, 2013, 2014, 2018, 2019.

Speaker: CRA-W Graduate Cohort, April 2013

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Co-Organizer: CRA-W/CDC Computer Architecture Discipline Specific Mentoring Workshop, August2012

Co-Organizers: Hillery Hunter (IBM), Russ Joseph, (Northwestern), Li-Shiuan Peh (MIT), KellyShaw (University of Richmond)Received funding support from CRA-W/CDC and ACM SIGARCH, ACM SIGMICRO, AMD,IBM, Intel, Microsoft, Google, Oracle Labs, and VMware

High School OutreachSpeaker, Fall Campus Day, October 2014Speaker, Fall Campus Day, October 2013Lester B. Pearson Collegiate Institute: Presentation on ECE to Grade 10 Computer Science class,April 2012Bishop Strachan School: Presentation on ECE to Grade 11 Physics class, March 2012.Bishop Strachan School: Presentation on ECE to Grade 11 Physics class, January 2011.

CRA-W/CDC Distinguished Lecture Series Organizer for University of Toronto, 2010Speakers: Margaret Martonosi (Princeton) and Jaime Moreno (IBM)

ProfessionalService

Co-ChairACM Council on Diversity and Inclusion, 2019-Present

Executive CommitteeACM Special Interest Group on Architecture (SIGARCH), Vice Chair, 2019-PresentACM Special Interest Group on Architecture (SIGARCH), 2015-2019IEEE Technical Committee on Computer Architecture (TCCA), 2015-2018ACM Special Interest Group on Microarchitecture (SIGMICRO), Vice Chair, 2017-Present

Co-EditorMorgan Claypool Synthesis Lectures on Computer Architecture, 2019–Present

Program Chair20th International Symposium on High Performance Computer Architecture (HPCA), 2014

Program Co-Chair7th ACM/IEEE International Symposium on Networks-on-Chip, 2013

Steering Committee MemberInternational Symposium on Microarchitecture (MICRO), 2018–PresentInternational Symposium on High Performance Computer Architecture (HPCA), 2014–2018International Symposium on Networks-on-Chip (NOCS), 2013–Present

Discovery Grant Evaluation Group Member: Electrical and Computer Engineering, 2016-2019Natural Sciences and Engineering Research Council of CanadaSection Chair, 2018, 2019

Associate Editor in ChiefIEEE Computer Architecture Letters, 2019-Present

Associate EditorACM Transactions on Architecture and Code Optimization, 2013-2018IEEE Computer Architecture Letters, 2014-2019

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IEEE Transactions on Computers, 2015-Present

Guest Co-EditorIEEE MICRO Special Issue on Approximate Computing, July/August 2018 (w/ Joshua SanMiguel, University of Wisconsin-Madison)IEEE MICRO Special Issue on Systems for Very Large Scale Computing, May/June 2011 (w/Mikko Lipasti, University of Wisconsin-Madison)

Committee MemberIEEE Computer Society Awards Committee, 2017-PresentIEEE Computer Society B. Ramakrishna Rau Award Committee, 2017-2018

ChairACM SIGARCH/IEEE CS TCCA Outstanding Dissertation Award, 2019

Track Co-ChairInternational Conference on Computer Design, Computer Systems and Applications Track, 2013Canadian Conference on Electrical and Computer Engineering, Computer, Software and Applica-tions Track, 2011

Student Travel Grants Co-ChairInternational Symposium on Computer Architecture, 2017

Industrial LiaisonInternational Symposium on Computer Architecture, 2016

Finance ChairInternational Symposium on Computer Architecture, 2015

Workshop/Tutorials ChairInternational Conference on Parallel Architecture and Compilation Techniques, 2013International Symposium on Performance Analysis of Systems and Software, 2013

Publicity ChairInternational Symposium on Computer Architecture (ISCA), 2014International Symposium on Code Generation and Optimization (CGO), 2010

Instructor, 8th International Summer School on Advanced Computer Architecture and Compilationfor High-Performance and Embedded Systems, 2012

4-day course: Networks-on-Chip: Communication challenges for many-core architectures

Workshop Co-Organizer11th Workshop on Duplicating, Deconstructing and Debunking (held with ISCA-41)10th Workshop on Duplicating, Deconstructing and Debunking (held with ISCA-39)9th Workshop on Duplicating, Deconstructing and Debunking (held with ISCA-38)8th Workshop on Duplicating, Deconstructing and Debunking (held with ISCA-36)

Session ChairInternational Symposium on Computer Architecture (ISCA), June 2018International Symposium on Computer Architecture (ISCA), June 2017International Symposium on Computer Architecture (ISCA), June 2015International Symposium on Microarchitecture (MICRO), December 2014

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International Symposium on Networks on Chip (NOCS), September 2014International Conference on Parallel Architectures and Compilation Techniques (PACT), August2014International Symposium on Computer Architecture (ISCA), June 2013International Symposium on High Performance Computer Architecture (HPCA), February 2012

External ReviewerNSERC Discovery Grants, Electrical and Computer Engineering Committee: 2011, 2012, 2013,2015

PanelistNational Science Foundation (US), Computing and Communication Foundations (CCF) GrantReview Panel, 2012National Science Foundation (US), Joint Computing and Communication Foundations (CCF)/Computer and Network Systems (CNS) Grant Review Panel, 2011

Program Committee (Conferences)Intl. Symposium on Computer Architecture (ISCA) 2013, 2015, 2017, 2018Intl. Conference on Architectural Support for Programming Languages and Operating Systems(ASPLOS) 2017, 2018Intl. Symposium on Microarchitecture (MICRO) 2011, 2016, 2017, 2019Intl. Symposium on Workload Characterization (IISWC) 2016IEEE Micro Top Picks 2013, 2015, 2019Intl. Symposium on High Performance Computer Architecture (HPCA) 2012, 2013, 2015, 2016Intl. Symposium on Networks-on-Chip (NOCS) 2014, 2015, 2016, 2017Intl. Conference for High Performance Computing, Networking, Storage and Analysis (SC) 2014Intl. Conference on Parallel Architectures and Compilation Techniques (PACT) 2010, 2014Intl. Conference on Supercomputing (ICS) 2011, 2014Intl. Conference on Parallel Processing (ICPP) 2010, 2013Intl. Parallel and Distributed Processing Symposium (IPDPS) 2011, 2012, 2013Intl. Conference on Computer Design (ICCD) 2009, 2010, 2011, 2012Intl. Symposium on Performance Analysis of Software and Systems (ISPASS) 2011, 2012Intl. Conference on Computer Aided Design (ICCAD) 2009, 2010Intl. Conference on Design Automation and Test in Europe (DATE) 2010

Program Committee (Workshops)General Purpose Processing Using GPUs (at ASPLOS) 2013Interconnection Network Architectures: On-Chip, Multi-Chip (at HiPEAC) 2011, 2012, 2013Communication Architecture for Scalable Systems (CASS) (at IPDPS) 2011, 2012, 2013Network on Chip Architectures (at MICRO) 2009, 2010, 2011, 2012, 2013Chip Multiprocessor Memory Systems and Interconnects (at ISCA, HPCA) 2009, 2010

External Review CommitteeInternational Symposium on Computer Architecture (ISCA) 2019International Conference o Parallel Architecture and Compilation Techniques (PACT) 2018International Symposium on High Performance Computer Architecture (HPCA) 2017International Conference on Architectural Support for Programming Languages and OperatingSystems (ASPLOS) 2010, 2013, 2015, 2016Internationl Symposium on Microarchitecture (MICRO) 2014

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Intl. Conf. on High-Performance and Embedded Architectures and Compilers (HiPEAC) 2012,2013

Reviewer for Conference and JournalsJournals: IEEE Micro, ACM Transactions on Computers, IEEE Transactions on Computers,IEEE Transactions in VLSI, IEEE Computer Architecture Letters, ACM Transactions on Embed-ded Computing Systems, ACM Transactions on Architecture and Code Optimization, Journal ofParallel and Distributed Computing, IEEE Journal of Emerging and Selected Topics in Circuitsand Systems, Transactions on Computer Aided Design, ACM Computing Surveys, ACM Transac-tions on Design Automation of Electronic Systems, IEEE Systems Journal, Canadian Journal ofElectrical and Computer Engineering, Journal of Optical Communications and Networking, IEEETransactions on Parallel and Distributed Computing

Cited as a ‘Top Reviewer’ in 2013 for IEEE Transactions on ComputersConferences: International Symposium on Microarchitecture, International Symposium onComputer Architecture, International Conference on Architectural Support for ProgrammingLanguages and Operating Systems, International Conference on Parallel Architectures and Com-pilation Techniques, International Conference on Supercomputing, International Symposium onParallel Algorithms and Architectures, International Conference on Parallel Processing, Interna-tional Conference on Computer Design, International Conference on Computer Aided Design,International Symposium on High Performance Computer Architecture, International Symposiumon Performance Analysis of Systems and Software, International Symposium on Circuits andSystems, Grace Hopper Celebration

Professional MembershipsIEEE, IEEE Computer Society, Technical Commitee on Computer Architecture (TCCA)

Senior MemberACM, SIGARCH, SIGMICRO

Distinguished Member (2018)Licensed Professional Engineer (P.Eng.) in Ontario

UniversityService

MemberECE Director of Faculty Recruiting 2019-2023ECE Faculty Search Committee (Chair), 2019Advisory Committee on the Appointment of ECE Chair, 2019Advisory Committee for the Dean of the Faculty of Applied Science & Engineering, 2018-2019ECE Advisory Committee (Computer Group Chair), 2018-PresentECE Faculty Search Committee (Chair), 2018ECE Promotion Through the Ranks (PTR) Committee, 2016-2019ECE Department Space Committee, 2014-2015Advisory Committee on the Appointment of ECE Chair, 2013Community Affairs and Gender Issues Committee, Faculty of Applied Science and Engineering,2010-2014

Vice-ChairCommunity Affairs and Gender Issues Committee, Faculty of Applied Science and Engineering,2010-2011, 2012-2013, 2013-2014 (acting chair)

Faculty AdvisorMechatronics Design Association, 2014-2016

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