nanoscale silicon based nonvolatile memory...2003/10/14 · of technology drain source gate sonos...
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Chungwoo Kim, [email protected]
N anoscale N anoscale Silicon B asedSilicon B ased N onvolatile M em ory N onvolatile M em ory
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
AcknowledgementsAcknowledgements
Seoul Nantional University (SNU)
Prof. Park, Byung-GooK
Korea Institute for Advanced Study
(KIAS)
Prof. Kim, Dae Mann
Kwangju Institute of Science andTechnology (KJIST)
Prof. Hwang, Hyun sang
Sungkyunkwan University
Prof. Chung Ilsub
Cornell University, USAProf. Sandip Tiwari
Institute of Semiconductor Physics,RussiaProf. Vlradmir Gritsenko
Collaboration
Funding
Tera-level Nanodevices21st Century Frontier R&D Program,Ministry of Science and Technology
SEC and SAIT
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
Introduction
Current research status– Nano fabrication Process
• Nanoscale patterning• SiN thin film• Si Nanoparticle
– Nano devices• Nanoscale SONOS memory• Vertical channel memory
Future Work
OutlineOutline
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
New application, unification – Diversfied from PC into digital application – Increasing capacity of voice, motion picture information ➙ Need higher density of memory – Increasing demand for unified memory
Uncertainty of DRAM & Flash Memory scalability
Memory Market: $35 billion (2001), $72 billion (2010), 8.3% increase/year
Environment of MemoryEnvironment of Memory
Settopbox
PDAHHP Internet
PC
DigitalTV
GamePlayer
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
Flash Memory RoadmapFlash Memory Roadmap(Source: ITRS 2001)
nm
1995 2000 2005 2010 2015
100
30
Feat
ure
Siz
e
Year
Unit CellProduction
Uncertain Stage
Research Stage
64-512MDevelop. Stage
130
180
70
50
150
10
128-512M
128M-1G256M-1G
256M-2G512M-4G
512M-4G
2G-16G
4G-64G
Scale limit ?
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
참고자료 : ITRS 2001
Year of Production
Flash tech. Node, F[nm]
NAND highest W/E Voltage[V]
NOR highest W/E Voltage[V]
NOR tunnel dielectric thickness[nm]
NAND tunnel dielectric thickness[nm]
NOR interpoly dielectric thickness[nm]
NAND interpoly dielectric thickness[nm]
2001 2002 2003 2004 2005 2006 2007
150 130 115 100 90 80 70
8-10 8-10 7-9 7-9 7-9
19-21 18-20 17-1918-20 18-20 18-20 17-19
8-10 8-10
9.5-10.5 9.5-10 9-10 9-10 8.5-9.5 8.5-9.5 8.5-9.5
8.5-9.5 8.5-9 8-9 8-9 8-9 7.5-8 7.5-8
13-15 12-14 11-13 11-13 10-12 9-11 9-11
14-16 13-15 12-14 12-14 12-14 11-13 10-12
Solutions ExistSolutions are Known
Solutions are NOT Known
Flash Technology RequirementsFlash Technology Requirements
(Source: ITRS 2001)
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
What’s the limits of flash scaling ?
Floating poly Stack
Active (STI)
Problems of conventional technologies
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
OvercomeOvercomeControl GateBlocking oxide
eTunnel Oxide
eeee
Discrete traps
n+ n+
p-well
SONOS Memory
Control GateBlocking oxide
n+ n+
p-well
Tunnel Oxide
Floating gate
ee e
기존 Flash memory
e ee ee e
☞ Discrete traps (SiN traps or Nanocrystal)
Discrete trapsDiscrete traps
* SONOS (Silicon-Oxide-Nitride-Oxide-Silicon)
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
< Advantages >• Compatibility of SONOS with CMOS with the use of thin nitride
• Lower programming voltage
• Smaller dimension capability than FG EEPROM
• Longer retention & low defect induced tunneling leakage
(Nitride instead of poly Si )
• Higher programming speed (depends on ONO thickness)
Trap sites
p-Si
Gate
30nm
S D
30 nm
US Patent # 6313503 (2001.11.6)
Motivation for SONOSMotivation for SONOS
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
4~10 F2
20~120 ns
1 µs ~ 1 ms
>10년
> 1E5
6 F2
10~100 ns
10~100 ns
> 10년
> 10E13
8~9 F2
10~100 ns
10~15 ns
> 10년
> 1E13
FRAM
8~25 F2
30~200 ns
30 ns
> 10년
> 10E12
Cell size
Read time
Write time
Retention
Endurance
Thin Oxide filmFaster P/E time
Power consumption
Etching processUniform thin filmsCost
Issues
MRAM PRAM SONOS
LowHighHighLowCurrent/Power
LowLowHighHighCost
CMOSSpecialSpecialSpecialProcess
Etching processCostRetention, Fatigue
Comparison of Memory TechnologiesComparison of Memory Technologies
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
2001
ChannelLength
130 nm130 nm
70 nm70 nm
30 nm30 nm
2002 2003
Source
DrainGate
70nm
SONOS Memory DevelopmentSONOS Memory Development
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
Nano Nano LithographyLithography
20nm 60nm
21 nm
32 nm
Sidewall Patterning
Positive Resist : PMMA
Negative Resist : Calixarene
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
Si Nanoparticle Si Nanoparticle Fabrication by Aerosol Laser AblationFabrication by Aerosol Laser Ablation
0 10 20 30 40 50 60 70 800
1x104
2x104
3x104
4x104
5x104
6x104
C
once
ntra
tion
(/cm
3 )
Nanoparticle Size (nm)
• D <10nm
• ρ ~ 1×1011 /cm2
5nm 5nm
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
3030nm SONOS Memory by SWPnm SONOS Memory by SWP
10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101 102 103-2.0-1.5-1.0-0.50.00.51.01.52.02.53.0
Vg=10
Vg=-10/Vd=4Vg=-10/Vd=3Vg=-10/Vd=2Vg=-10/Vd=1
ONO=23/120/45 Å
Vg=-10
Thr
esho
ld V
olta
ge [V
]
Write/Erase Time [Sec]
Key Features of SONOS CellMemory Node Size: 30 x 30 nm2
Write/ Erase Voltage: <10V
Write/Erase Time: 1 msec
Endurance: >106 cycles
Retention = 1year @T=85℃
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
Key Characteristics of SONOS MemoryKey Characteristics of SONOS Memory
-1.0 -0.5 0.0 0.5 1.01E-14
1E-13
1E-12
1E-11
1E-10
1E-9
1E-8
1E-7
1E-6
Vth=-0.05V
W/L=30nm/30nmONO=23/120/45 A
VDS=1V
VDS=0.1V
S.S = 89mV/decDIBL = 105mV
Drai
n Cu
rren
t [A]
Vgs [V]
0.0 0.2 0.4 0.6 0.8 1.00.00E+000
4.00E-008
8.00E-008
1.20E-007
1.60E-007
2.00E-007
2.40E-007
2.80E-007
3.20E-007
3.60E-007
ONO=23/120/45 Å 1.0V0.8V
0.6V
0.4V
0.2V
VGS=0V
Drai
n Cu
rren
t [A]
Vds [V]
10-2 10-1 100 101 102 103 104 105 106 107 108-2
-1
0
1
2
3
1.4 [V]
Time [sec]
Vth
[V] At 85C
@ Program state @ Erase state
100 101 102 103 104 105 106
-1.0
-0.5
0.0
0.5
1.0
1.5
Programmed @10V/1ms Erased @-10V/10ms
Vth
(V)
Cycles (number)
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
Drain
Source
Gate
SONOS Memory by E-beam LithographySONOS Memory by E-beam Lithography
SONOS Cell by E-beam Lithography
W/L : 33nm / 46nm
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
20Å / 70Å / 90Å
SiO2= 20ÅSi3N4= 70Å
SiO2=90Å
• TEM of the ONO (2 nm/7 nm/9 nm) stack• Auger profile showing the stoichiometric of ONO layer.
ONO layer TEM & AES AnalysisONO layer TEM & AES Analysis
0 3000 6000 9000 12000 15000 18000
0
20
40
60
80
100
Rel
ativ
e AC
P(%
)
Si N O
Sputter Time [sec.]
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
Th
resh
old
Vo
ltag
e[V
]
Write Time[sec]
|9V| |10V| |11V| |12V| |13V|
1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Th
resh
old
Vo
ltage
[V]
Erase Time[sec]
|9V| |10V| |11V| |12V| |13V|
∆Vth ~ 2.4V
Trapped Charge density = 4.1 ~ 5.9 x 1012 cm –2
No. of e- = 61 ~ 88 for 33nm x 46nm node size
∆Vth ~ 2.4V
Trapped Charge density = 4.1 ~ 5.9 x 1012 cm –2
No. of e- = 61 ~ 88 for 33nm x 46nm node size
Program & Erase Program & Erase CharacterisicsCharacterisics
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
• Memory window is nearly similar for SONOS devices with different memory node areas
Memory Window ComparisonMemory Window Comparison
-2 -1 0 1 2 3 4 5 6 7 8 9 1010-15
1x10-14
1x10-13
1x10-12
1x10-11
1x10-10
1x10-9
1x10-8
1x10-7
1x10-6
1x10-5
Wg/L
g=90nm / 100nm
Id
[A]
Vg [V]
Wg/Lg=90nm/100nm
-2 -1 0 1 2 3 4 5 6 7 8 9 1010-15
1x10-14
1x10-13
1x10-12
1x10-11
1x10-10
1x10-9
1x10-8
1x10-7
1x10-6
1x10-5
Wg/L
g=75nm / 100nm
Id [A
]
Vg [V]
Wg/Lg=75nm/100nm
-2 -1 0 1 2 3 4 5 6 7 8 9 1010-15
1x10-14
1x10-13
1x10-12
1x10-11
1x10-10
1x10-9
1x10-8
1x10-7
1x10-6
1x10-5
Wg/L
g=62nm / 60nm
Id [A
]
Vg [V]
Wg/Lg=62nm/60nm
-2 -1 0 1 2 3 4 5 6 7 8 9 1010-15
1x10-14
1x10-13
1x10-12
1x10-11
1x10-10
1x10-9
1x10-8
1x10-7
1x10-6
1x10-5
Wg/L
g=33nm / 46nm
Id [A
]
Vg [V]
Wg/Lg=33nm/46nm
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
• Retention time is good with 75nm width and 100 nm length at 85℃.
Retention TimeRetention Time EnduranceEndurance
10-1 100 101 102 103 104 105 106 107 108 1090.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Wg/Lg=75nm / 100nm
Temp=85C
Thre
shol
d Vo
ltage
[V]
Retention Time[sec]
Write 10V, 10msec Erase -10V, 1msec
101 102 103 104 105 1060.6
0.8
1.0
1.2
1.4
1.6
1.8
Temp=85C
Wg/L
g=33nm / 46nm
Thre
shol
d Vo
ltage
[V]
Write/Erase Cycle
Write 12V/10msec Erase -10V/1msec
• It remains unchanged up to 105
cycles, indicating superior endurance characteristics at 85℃.
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
• Single electron charging effect at 30 nm dimensions.
Memory Effect at 30 nm dimensionsMemory Effect at 30 nm dimensions
Wg = 35.4 nm Lg = 39 nm-1 0 1 2 3 40.0
2.0x10-10
4.0x10-10
6.0x10-10
8.0x10-10
1.0x10-9
1.2x10-9
1.4x10-9
Wg/Lg=35nm / 39nm
Before write After write(10ms,|10V|)
ID [A
]
VG [V]
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
Vertical Channel SONOS
N+ N+
Poly Silcon
BOX
Schematic of VC SONOS
1E-41E-3 0.01 0.1-0.8
-0.4
0.0
0.4
0.8
1.2
1.6
2.0
0.001
Vg 6/7/8V
Erased Cell
Programmed Cell
Vg -6/-7/-8V
V th (V
)Write/Erase Time(sec)
Id=1nA, Vd=0.5V
• ∆Vth=1.6V @ 8/-8V &10ms
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
TEM images
Gate
CVD oxide
Verticalchannel
O/N/O
ContactVertical channel
bulk
Drain
Source
Gate
source draingate
C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 ADVANCED INSTITUTEOF TECHNOLOGY
Nano fabrication process for Integration
Improvement of SONOS memory characteristics
– High-k materials
– New memory cell structure
– Optimal bias conditions
Device physics– Single electron effect
– Reliability failure mechanism
– Memory cell Modeling/Simulation
Future WorkFuture Work