nanometer-scale iii-v cmos slides.pdf · 10/14/2012 · 1. the cmos revolution 2. materials...
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1
Nanometer-Scale III-V CMOS
J. A. del AlamoMicrosystems Technology Laboratories, MIT
Acknowledgements:
• D. Antoniadis, D.-H. Kim, T.-W. Kim, D. Jin, J. Lin, N. Waldron, L. Xia
• Sponsors: Intel, FCRP-MSD
• Labs at MIT: MTL, NSL, SEBL
Short Course on The Future of Semiconductor Devices and Integrated Circuits
34th IEEE Compound Semiconductor IC SymposiumOct. 14th, 2012
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1. The CMOS revolution2. Materials options for post-Si CMOS3. What have we learned from III-V HEMTs?4. III-V CMOS device design and challenges
– Critical issue #1: the gate stack– Critical issue #2: the ohmic contacts– Critical issue #3: the p-channel device– Critical issue #4: non-planar MOSFET designs– Critical issue #5: co-integration of nFETs and pFETs
5. Concluding remarks
2
Outline
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1. The CMOS Revolution: Smaller is Better!
Virtuous cycle of scaling exponential improvements in:– Transistor density (“Moore’s law”)– Performance – Power efficiency
Intel microprocessors Intel microprocessors
3
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The Si CMOS Revolution: Smaller is Better!
4
Koomey, Ann. Hist.
Computing 2011
Year of introduction
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CMOS scaling in the 21st century
Si CMOS has entered era of “power-constrained scaling”:– Microprocessor power density saturated at ~100 W/cm2
– Microprocessor clock speed saturated at ~ 4 GHz
5
Intel microprocessors
Pop, Nano Res 2010
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Transistor scaling requires reduction in supply voltage
Consequences of Power Constrained Scaling
Power = active power + stand-by power
PA~ f CVDD2N N ↑ VDD ↓
6
#1 goal!clock frequency
transistor capacitance
operating voltage
transistor count
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CMOS power supply scaling
7
40 nm strained-Si MOSFET (Intel)
Dewey, IEDM 2009
Recently, VDD scaling very weakly…
… because Si performance degrades as VDD↓
Need scaling approach that allows VDD reduction while enhancing performance
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• Goals of scaling: – reduce transistor footprint – extract maximum ION
for given IOFF
How to enable further VDD reduction?
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How to enable further VDD reduction?
• Goals of scaling: – reduce transistor footprint – extract maximum ION
for given IOFF
• The path forward:– increasing electron velocity ION ↑ – tighter carrier confinement S ↓
VDD ↓
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2. Materials options for post-Si CMOS
Ideally want:• High electron and hole velocity
• Si: ve~1.5x107 cm/s, vh~1.2x107 cm/s
• High sheet-carrier concentration at low voltage
• Si: ~6x1012 cm-2 @1 V
• High enough bandgap energy
• Si: Eg=1.1 eV
• High-quality, reliable MOS gate stack
• Si: Dit~1011 eV-1.cm-2
• Same material for n-channel and p-channel device
• Easily integrable on Si substrate
• Manufacturable technology (top down, ex-situ dielectrics)
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Bandgap energy
~2x Si
~2x Si
InAs, InSb problematic but strong quantum confinement can be used to enhance effective bandgap
T=300 K
Ge
Si
GaAs
GaP
InPAlSb
GaSb
InAs
AlP
AlAs
0.8
0.4
1.2
1.6
2.0
2.4
2.8
0
5.4 5.6 5.8 6.0 6.2 6.4
Ene
rgy
Gap
(eV
)
Lattice Constant (Å)
InSb
adapted from Bennett
Ge
Si
GaAs
GaP
InPAlSb
GaSb
InAs
AlP
AlAs
0.8
0.4
1.2
1.6
2.0
2.4
2.8
0
0.8
0.4
1.2
1.6
2.0
2.4
2.8
0
5.4 5.6 5.8 6.0 6.2 6.45.4 5.6 5.8 6.0 6.2 6.4
Ene
rgy
Gap
(eV
)
Lattice Constant (Å)
InSb
adapted from Bennett
~0.5x Si
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Use mobility as proxy for velocity
~2x Si
~2x Si
GaAs, InP, GaSb: promising for nFETGe: borderline nFETGe, GaSb, InSb: borderline pFETGaAs: ruled out for pFET
300 K quantum-well or inversion layer mobility at any sheet carrier concentration:
del Alamo, Nature 2011
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The role of compressive biaxial strain
~2x Si InAs: hurts nFET (need tensile strain)Ge, GaSb, InSb: bigpFET improvement (µ>1,000 cm2.V.s)
~2x Si
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What about ternary III-Vs?
~2x Si
InGaAs: promising for nFETInGaSb: promising for pFETInGaAs: borderline for pFET
~2x Si
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Dit close to band edges
GaAs, GaSb: ruled out for nFETGaSb, InGaAs: ruled out for pFETLittle known about InAs or InSb
Buried-channel structures still possible for narrow-bandgap materials but need to provide appropriate band discontinuity
Dit(cm2/V.s)
Energy in bandgap
1013
1012
1011
GaAs
GaSb
GaAs
GaSb
InGaAs
InGaAs
InP
GeGe
Ev Ec
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InGaAs nFETInP nFETGe nFETInGaSb pFETGe pFET
Options for post-Si CMOS
~2x Si
~2x Si
Different lattice constants for n-channel and p-channel devices (except for Ge)
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1717
3. What have we learned from III-V HEMTs?
1717
The High Electron Mobility Transistor is now >30 years old!
Mimura, JJAPL 1980
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PHEMT ICs
18
Bipolar/E-D PHEMT process
Henderson, Mantech 2007
40 Gb/s modulator driver Tessmann, GaAs IC 1999
77 GHz transceiver
Carroll, MTT-S 2002
UMTS-LTE PA moduleChow, MTT-S 2008
Single-chip WLAN MMIC, Morkner, RFIC 2007 PHEMT MMIC market=$1.2B in 2011
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Near-THz III-V FETs
fT in III-V FETs vs time:
19
(and MHEMT)
Current fmax record:fmax=1.25 THzKim IEDM 2010(Teledyne/MIT)
Current record:fT=688 GHzfmax=800 GHzKim IEDM 2011 (Teledyne/MIT)
(and MHEMT)
• For >20 years, record fT obtained on InGaAs-channel HEMTs• InGaAs-channel HEMTs offer record of balanced fT and fmax
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S D
Etch stopper
Barrier
Channel
Buffer
tins
Oxide
tch
Gate
Cap
2020
III-V HEMTs: excellent model system to explore logic suitability of III-Vs
2020
- QW channel (tch=10 nm):• InAs core (tInAs = 5 nm)• InGaAs cladding
n,Hall=13,200 cm2/V-sec- InAlAs barrier (tins=4 nm)- Ti/Pt/Au Schottky gate- Lg=30 nm Kim, EDL 2010
State-of-the-art: InAs HEMTs
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2121
Lg=30 nm InAs HEMT
21
• Large current drive: ION>0.5 mA/µm at VDD=0.5 V• High transconductance: gmpk= 1.9 mS/μm at VDD=0.5 V • VT = -0.15 V, RS=190 ohm.μm
21
Kim, EDL 2010
0.0 0.2 0.4 0.6 0.80.0
0.2
0.4
0.6
0.8
0.2 V
0.4 V
0 V
I D [m
A/
m]
VDS [V]
VGS =
-0.6 -0.4 -0.2 0.0 0.20.0
0.5
1.0
1.5
2.0
g m [m
S/m
]VGS [V]
VDS = 0.5 V
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109 1010 1011 10120
10
20
30
40
Frequency [Hz]
Gai
ns [d
B]
-1
0
1
2
3
K
H21
K
MSG/MAG
Ug
Lg=30 nm InAs HEMT
222222
• First transistor of any kind with both fT and fmax > 640 GHz• Current record is fT, fmax > 688 GHz from Teledyne/MIT
collaboration (Kim, IEDM 2011)22
Kim, EDL 2010
fT = 644 GHzfmax = 681 GHz
VDS=0.5 V, VGS=0.2 V
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30 nm InAs HEMT – Logic characteristics
232323
• S = 74 mV/dec, DIBL = 80 mV/V
23Kim, EDL 2010
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.410-9
10-8
10-7
10-6
10-5
10-4
10-3
VDS = 0.05 V
VDS = 0.5 V
IG
ID
VDS = 0.5 V
I D, I
G [A
/m
]
VGS [V]
VDS = 0.05 V
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30 nm InAs HEMT – Logic characteristics
242424
• S = 74 mV/dec, DIBL = 80 mV/V• At IOFF=100 nA/μm and VDD=0.5 V, ION=0.52 mA/μm
24
Kim, EDL 2010
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.410-9
10-8
10-7
10-6
10-5
10-4
10-3
VDS = 0.05 V
VDS = 0.5 V
IG
ID
VDS = 0.5 V
I D, I
G [A
/m
]
VGS [V]
VDS = 0.05 V
ION=0.52 mA/μm
IOFF=100 nA/μm
0.5 V
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FOM that integrates short-channel effects and transport: ION @ IOFF=100 nA/µm, VDD=0.5 V
InAs HEMTs: higher ION for same IOFF than Si. Why?
InAs HEMTs: Benchmarking with Si
25
KimIEDM 2008
Kim EDL 2010
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1. Very high electron injection velocity at the virtual source
EC
vinj
• vinj(InGaAs) increases with InAs fraction in channel
• vinj(InGaAs) > 2vinj(Si) at less than half VDD
• ~100% ballistic transport at Lg~30 nm
Why high ION?
Kim, IEDM 2009Liu, Springer 2010Khakifirooz, TED 2008del Alamo, Nature 2011
26
EV
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2. Quantum capacitance less of a bottleneck than previously believed
InAs channel: tch = 10 nm
-0.4 -0.2 0 0.2 0.40
10
20
30
40
VG [V]
Cap
acita
nce
[fF/
m2 ]
Experiment (CG)
Cins ( tins = 4 nm)
Ccent1
CQ1 (m||* = 0.026me )
CG (m||* = 0.026me )
CG ( 0.07 ) CG ( 0.05 )
Biaxial strain + non-parabolicity + strong quantization: m||
* ↑ CG ↑ ns ↑ ION ↑
Why high ION?
Jin, IEDM 2009
27
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3. Sharp subthreshold swing due to quantum-well channel
• Dramatic improvement in short-channel effects with thin channel• Thin channel does not degrade vinj at Lg~40 nm (Kim, IPRM 2011)
Why high ION?
Kim, IPRM 2010
28
60
70
80
90
16040 20012080
InAs HEMTs: tch = 5 nm
InAs HEMTs: tch = 10 nm
In0.7Ga0.3As HEMTs: tch = 13 nmSu
btre
shol
d sw
ing
[mV/
dec]
Lg [nm]
tins = 4 nm, Lside = 80 nm
state-of-the-art Si
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-1.00 -0.75 -0.50 -0.25 0.00 0.25 0.5010-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
VDS
= 0.5 V
I D, I G
[A/
m]
VGS [V]
tins
= 10 nm tins = 7 nm t
ins = 4 nm ID
IG
29
Limit to III-V HEMT Scaling: Gate Leakage Current
tins ↓ IG↑ Further scaling requires high-K gate dielectric
29
InAs HEMTLg = 30 nmtch = 10 nm
tins=4 nm
tins=7 nm
tins=10 nmdel Alamo. IPRM 2011
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4. III-V CMOS:device design and challenges
Intel’s 45 nm CMOSIII-V HEMT
• What do we preserve?
• What do we change?
~1 m
Modern III-V HEMT vs. modern Si MOSFET:
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III-V CMOS: HEMT features worth preserving
31
• Quantum-well channel: key to scalability
• Undoped channel:
• InAs-rich channel: for high mobility and velocity
• Buried-channel design:
• Raised source and drain regions: essential for scalability
• Undoped QW channel in extrinsic regions: key to low access resistance
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III-V CMOS: HEMT features to change
32
• Schottky gate: need MOS gate with very thin high-K dielectric
• T-gate: need rectangular gate
• Barrier under contacts: need to eliminate
• Alloyed ohmic contacts: change to refractory ohmic contacts
• Source and drain contacts: need self-aligned with gate
• Footprint: need to reduce by 1000x!
n+n+
QW-MOSFETHEMT
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III-V CMOS: other critical issues
33
• p-channel MOSFET: with performance >1/3 that of n-MOSFET
• Co-integration of n-FET and p-FET on Si: compact, planar surface
• Sub-10 nm MOSFET architectures
n-MOSFET p-MOSFET
Silicon
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Focus on ION for fixed IOFF as FOM.Simple model:• Q-V characteristics from Poisson-Schrodinger simulations
(from subthreshold to strong inversion)• 2D ballistic velocity model (1 subband):
Lundstrom, TED 2002
• Add channel capacitance to match experimental S• Add ohmic drop on experimental RS
• No adjustable parameters beyond m*=0.05 mo
• Did not attempt to match VT
What can we expect from~10 nm III-V NMOS at 0.5 V?
34
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Model validation: I-V characteristics of 30 nm InAs HEMT
35
ID(exp) > ID(sim): impact ionization?
VDS=0.5 VVDS=0.5 VRS=190 ohm.umS=74 mV/dec
• Excellent agreement through nearly five orders of magnitude of ID
• Residual disagreement due to impact ionization?
VDS=0.5 V
IOFF =100 nA/um
ION
ION
VDS=0.5 VIOFF
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Projection to ~10 nm InAs NMOS at 0.5 V
36
Scale experimental 30 nm InAs HEMT by about 3x:
• Q-V characteristics from Poisson-Schrodinger simulator• Assume same short-channel effects: S=74 mV/dec• Examine impact of RS and Dit
tins=2.6 nm(=250)
tch=3 nmLg=10 nm
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Role of RS
37
• RS depresses ION without changing IOFF
• To obtain ION>1 mA/µm, need RS<100 Ω.µm
VDS=0.5 V
IOFF =100 nA/um
ION
VDS=0.5 VIOFF
IONVDS=0.5 VLg=10 nmS=74 mV/dec
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Role of Dit
38
• Dit in bandgap increase S ION↓• Dit inside conduction band further decrease ION
VDS=0.5 V
IOFF =100 nA/um
ION
VDS=0.5 VIOFF
Simple case: constant Dit throughout structureFor RS=100 ohm.um and S=74 mV/dec (for Dit=0):
ION
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Role of Dit
39
• To obtain ION>1 mA/µm, need Dit<3x1012 eV-1.cm-2
• Relative insensitivity of ION to Dit due to high Cins:Cins=85 fF/µm2 ↔ Dit=5.3x1013 eV-1.cm-2
VDS=0.5 VLg=10 nmRS=100 ohm.umS=74 mV/dec (Dit=0)
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Assumptions/concerns
• Aggressive vertical scaling possible: EOT=0.41 nm [EOT ≡ equivalent oxide thickness]
• Rigid 3X shrink preserves short-channel effects• Lside can be shrank without degrading SCE• RS<100 Ω.µm feasible at required footprint• Ballistic transport even with high-K dielectric + thin channel
40
tins=2.6 nm(=250)
tch=3 nmLg=10 nm
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Critical issue #1: the gate stack
Challenge: metal/high-K oxide gate stack– Fabricated through ex-situ process– Very thin barrier (EOT<1 nm)– Low gate leakage (IG<1 A/cm2 at VGS=0.5 V)– Low Dit (<3x1012 eV-1.cm-2 in top ~0.3 eV of bandgap and inside
CB)– Reliable
41
n+n+
high-K dielectric
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Problem: Fermi level pinning at oxide/III-V interfaces
III-V MOSFET: a >40 year pursuit!
42
Kohn, EL 1977
Mimura, EL 1978
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Problem: Fermi level pinning at oxide/III-V interfaces
43Spicer, JVST 1979
Fermi level pinning due to interfacial defects– Even 1% of a monolayer of O at GaAs surface pins EF
– EF pinning produced by any foreign element at GaAs surface– EF pinning position largely independent of surface adatom
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Recent breakthrough: oxide/III-V interfaces with unpinned Fermi level!
44
In-situ UHV Ga2O3-Gd2O3 on GaAs Ex-situ ALD Al2O3 on InGaAs
Ren, SSE 1997 Ye, EDL 2003
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“Self-cleaning” during ALD
45Huang, APL 2005
ALD largely eliminates surface oxides responsible for Fermi level pinning:
– Occurs during first exposure of III-V surface to ALD metal source– Surface robust to later exposure to ALD oxidant– First observed with Al2O3, then with other high-K dielectrics– First seen in GaAs, then in other III-Vs
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Interface state density in high-K/III-V by ALD
46Brammertz, APL 2008
Dit hard to characterize reports vary widelyGeneral consensus for Dit:
– GaAs: high at midgap, medium close to Ecand Ev, large peak around midgap
– InGaAs: high close to Ev, low close to Ec
– InP: high close to Ev, very low close to Ec
Heyns, IRPS 2012
InP
GaAsInGaAs
Ec
Ec
Ec
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Problem: low mobility in high-K/InGaAs structure
47Lin, IEDM 2008
In high-K/InGaAs surface-channel structure:– Low mobility (µe<2,000 cm2/V.s vs. µe~10,000 cm2/V.s in HEMT) – tox ↓ µe ↓– Mostly due to interface roughness scattering
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Solution: buried-channel structure
48
Introduce thin wide bandgap semiconductor between dielectric and channel:
– For InGaAs, InP best choice (lattice matched, low Dit close to Ec) – Key trade-off: scalability vs. transport:
tbarr ↓ µe ↓ s ↑
Urabe, ME 2011
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49
The high-water mark: Intel’s InGaAs Quantum-Well MOSFET
• Direct MBE on Si substrate (1.5 m buffer thickness)• InGaAs buried-channel MOSFET (under 2 nm InP barrier)• 4 nm TaSiOx gate dielectric by ALD, Lg=75 nm• First III-V QW-MOSFET with better performance than Si
Radosavljevic, IEDM 2009
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Critical issue #2: the ohmic contacts
50
Challenge: nanometer-scale ohmic contacts with low Rs– Low contact resistance (Rs<100 Ω.µm)– Raised above channel– Self-aligned to gate (Lside<10 nm)
Recessed gate Regrown source and drain
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Key problem: ohmic contact scaling
Current contacts to III-V FETs are >100X off in required contact resistance 51
Waldron, TED 2010
Reduce contact resistivity + resistance of contact stack
HEMT Today: Rc~200 Ω.μmNeed: Rc~50 Ω.μm
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Resistivity and contact resistance of n+-In0.53Ga0.47As
52
Mo
TiW
Cr
n+-Si
n=5x10-4 Ω.cm
n=1.4x10-4 Ω.cm
• n+-In0.53Ga0.47As vs. n+-Si:o μe: ~10X across doping range minimum ρn comparableo ρc comparable for various metals
• Fundamentally, contacts to InGaAs should be as good as to Si
Singisetti APL 2008Baraskar JVSTB 2009
Singisetti DRC 2007Crook APL 2007
Fujii EL 1986
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Recessed-gate self-aligned InGaAs QW-MOSFET
53
Key features: • Buried channel design
• Inverted-delta doping
• Refractory ohmic contacts
• Ohmic contacts self-aligned to gate
• Gate-last process
• Lift-off free front-end process
• Extensive RIE
Process leverages self-aligned InGaAs HEMT for mmw applications
(Waldron, TED 2010; Kim, IEDM 2010)
Lin, APEX 2012
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54
Output and transfer characteristics: evidence of RIE damage and solution
• Lg=2 µm, Lside= 100 nm• RIE leads to extensive device damage• Damage annealed at 340oC for 15 min• gm=205 μS/μm at VDS=0.5 V for Lg=2 μm• VT=0.05 V
0.0 0.2 0.4 0.6 0.80
50
100
150
200 w/ annealing w/o annealing
I d (A
/m
)
Vds (V)
Vgs-Vt=0 to 1V in 0.2 V stepLg= 2 m
-0.8 -0.4 0.0 0.4 0.80
50
100
150
0
50
100
150
200
250
I d (A
/m
)Vgs (V)
: w/ annealing: w/o annealing
Lg= 2m, Vds= 0.5 V
Gm (
S/
m)
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55
Subthreshold and mobility characteristics
• S=95 mV/dec• Ion/Ioff=106
• μpeak=2800 cm2/V.s
-0.8 -0.4 0.0 0.4 0.810-4
10-3
10-2
10-1
100
101
102
S=300mV/dec
w/ annealing w/o annealing
Vds=0.5 and 0.05 VLg= 2m
S=95mV/dec
I d (A
/m
)
Vgs (V)0 2 4 6 8
0
1000
2000
3000 w/ annealing w/o annealing
Mob
ility
(cm
2 / V.s
)Ns(1012 cm-2)
W/L=200/200 m
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56
Source and drain resistance
• Rs=260 Ω.μm (our best result in HEMT ~140 Ω.μm)• Major component is lateral Mo resistance (Rsh=25 Ω/) • Vertical tunneling resistance greatly reduced wrt HEMT (50 Ω.μm vs.
>100 Ω.μm)
0 5 10 15 20 250
5
10
15
20
25
520m
Vg=1 V
Rsd
(K
m)
Lg (m)
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Latest results: Dielectric scaling to EOT<1 nm
-0.2 0.0 0.2 0.4 0.610-11
10-10
10-9
10-8
10-7
10-6
S=69 mV/dec
Vds=0.5 and 0.05 VLg= 300m
I d (A
/m
)
Vgs (V)
57
• Long-channel In0.53Ga0.47As FET • InP scaled to 1 nm by Ar-based dry etching• S=69 mV/dec• Close to lowest S reported in any III-V MOSFET: 66 mV/dec (EOT=1.2 nm)
[Radosavljevic, IEDM 2011]
Lin, IEDM 2012
InP (1 nm) + Al2O3 (0.4 nm) + HfO2 (2 nm) EOT~0.9 nm
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Latest results: Lg=60 nm QW-MOSFET
Many improvements:• Lg=60 nm• Improved gate recess process• Tight S/D spacing (Lside < 20 nm)• Scaled barrier (InP) and dielectric (high-K) thickness
SiO2
InGaAs channel-Si
InAlAs buffer
InP substrate
Pad
Mo (S/D)
n+ InGaAsInP
DielectricMo (G)
50 nm
Mo(S/D) Mo (G)Cap
SiO2
Lside~20 nm
Lg= 90 nm
Lin, IEDM 2012
58
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Transfer and output characteristics
• S=145 mV/dec at 0.5 V• Ion = 120 mA/µm measured at Vdd= 0.5 V and Ioff= 100 nA/µm• Peak gm = 1250 µS/µm• Ig < 5x10-10 A/µm at maximum gate overdrive• Ron = 570 Ω.µm (at Vgs-Vt=0.7 V)
0.0 0.2 0.4 0.6 0.80
200
400
600
800
I d (A
/m
)
Vds (V)
Vgs-Vt=0 to 0.7 V in 0.1 V stepLg= 60 nm
Lin, IEDM 2012 59
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Regrown source and drain self-aligned InGaAs QW-MOSFET
60
Key features: • n+-InGaAs raised source and drain regions grown by MOCVD
• Self-aligned to gate
• Surface quantum-well channel
• Gate oxide: Al2O3 (0.5 nm) + HfO2 (6.5 nm); EOT=1.3 nm
Egard, IEDM 2011
n+ n+
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Characteristics of Lg=55 nm MOSFET
61
• gm=1900 µS/µm
• S=187 mV/dec
• RS=88 Ω.µm
Egard, IEDM 2011
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e,h(cm2/V.s)
a (nm)0.54
1,000
10,000
100
0.56 0.58 0.60 0.62 0.64 0.66
GaAs
Electrons
InGaAs
GaAs
InGaAs
InGaSbGaSb InSb
Holes
InSb
SiGeGe
Si
Si GeGaAs
InP AlSbGaSb
InAs InSb
increasingcompressivebiaxial stress
relaxed lattice constant
InAs
GaSbInP
Critical issue #3: the p-channel device
62
Challenge: high-performance p-type III-V MOSFETs– Antimonide channel– Incorporating strong compressive strain
del Alamo, Nature 2011
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III-V pFETs: the benefits of strain
63
MIT workThompson, IEDM 2006Weber, IEDM 2007
Xia, APL 2011Xia, TED 2011Xia, ISCS 2011Gomez, EDL 2010
Compressive biaxial strain + uniaxial strain μ↑↑
0
1sp
Uniaxial-strain piezoresistance coefficients in p-type Quantum Wells
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P-type InGaAs QW-FET with process-induced uniaxial strain + epitaxially-grown biaxial strain
64Anisotropic gm enhancement gm enhancement scales correctly
Xia, IEDM 2011
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Strain-induced Δgm anisotropy
65
Result of band deformation + piezoelectric effect
Pz affects quantization in valence band m* anisotropy
Xia, IEDM 2011
-0.1 -0.05 0 0.05 0.1-0.16
-0.14
-0.12
-0.1
-0.08
-0.06
Ev (e
V)
m*//↓m* ↑
Biaxial +[-110] uniaxial
Biaxial
hh1
lh1
hh2
k[110] k//[-110]
Polarizationfield
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InGaSb surface-channel MOSFET
66
InGaSb surface channel device problematic: high Dit close to valence band edge
• Al2O3 (10 nm) / In0.35Ga0.65Sb (7 nm) MOSFET• S=120 mV/dec in Lg=5 µm device
BiaxialGaSb
Nainani, IEDM 2010Nainani, TED 2011
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InGaSb buried-channel MOSFET
67
Need Al containing barrier (i.e. AlInSb) Also need cap: GaSb or InAs
Scalibility problems for buried-channel InGaSb MOSFETs
channel
barrier
structure lattice constant
Madisetti, DRC 2012
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InGaSb buried-channel MOSFET
68
Al2O3/GaSb/AlInSb/InGaSb buried-channel MOSFET:
No subthreshold swing data given
Yuan, VLSI Tech 2012
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Critical issue #4: non-planar MOSFET designs
Challenge: small subthreshold swing on a small-footprint– Planar designs might not provide enough “electrostatic integrity”– Need higher carrier confinement through restricted dimensionality
designs
69
n+n+
FinFET Gate-all-around nanowire FETQW-MOSFET
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Increased electrostatic control through multiple gates
As number of gates increases, electrostatic control of gate over channel improves S ↓
– Improved Lg scaling– Cross section ↓ S ↓
70
FinFETTrigate
Nanowire
Chen, ICSICT 2008
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InGaAs Trigate MOSFET
71Far improved S vs. planar quantum-well MOSFET
Radosavljevic, IEDM 2011
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InGaAs Gate-All-Around Nanowire MOSFET
72
Gu, IEDM 2011Gu, APL 2011
• Lch= 50-120 nm • WFin=30, 50 nm• HFin = 30 nm• LNW = 150-200 nm• tox = 10 nm Al2O3
• # wires = 1, 4, 9, 19
Surface-channel design
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InGaAs Gate-All-Around Nanowire MOSFET
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-2 -1 0 1 210-2
10-1
100
101
102
103 Vds=1V
Vds=0.5V
I s (A
/m
)
Vgs (V)
Vds=0.05V
LG = 50nmWFin = 30nmNo. of wires = 4
Vth = -0.68VDIBL = 210mV/VSS = 150mV/dec
Ig @ Vds=1V
10-6
10-5
10-4
10-3
10-2
10-1
100
I g (A/c
m2 )
• Ion =720 μA/μm (86 μA/wire)
• gm =510 μS/μm (61 μS/wire) at VGS-VT=2 V
• S=150 mV/dec (EOT≈4.5 nm), Ig <10-7 A/cm2
• Low field µ~900 cm2/V.s (200 cm2/V.s in Si GAA NW from Samsung)
Gu, EDL 2012
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The challenge: cost-effective co-integration of nFETs and pFETs on Si substrate
– Different channel materials – Different lattice constants– Planar surface– Thin buffer layer– Compact– Low defectivity
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Critical issue #5: co-integration of nFETs and pFETs
Fiorenza ECS 2010
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Direct Wafer Bonding
75
Yokoyama, VLSI Tech 2011
Device surfaces at two different levels
Dielectric bonding of InGaAs/InP wafer and Ge wafer
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III-V on Insulator (XOI)XOI platform: epitaxial layer transfer onto Si/SiO2 substrate
Produces freestanding materials on a receiver substrate
Ko, Nature 2010
• Single crystal material
• Strain preserved
• Void-free interfaces
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III-V CMOS on Si
77Nah, Nano Lett 2012
SiO2InAs cappedInGaSb photoresist
InAs
2-step transfer processnFET: InAs (8 nm)pFET: InAs/In0.3Ga0.7Sb/InAs: 2.5/7/2.5 nmBoth grown on GaSb wafer
Ni
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III-V CMOS on Si
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Nah, NanoLett 2012
-1.0 -0.5 0.0 0.5 1.00
20
40
60
80
100
120
I p(A
)
Vd(V)
0
20
40
60
80
100
120
140 |Vg|= 0.2V |Vg|= 0.4V |Vg|= 0.6V |Vg|= 0.8V |Vg|= 1.0V
I n(A
)
LG = 2.9 m LG = 2.6 m
1st III-V CMOS on Si based on InAs n-FETs and InGaSb p-FETs
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Aspect Ratio Trapping
Fiorenza ECS 2010
Growth in high aspect ratio trenches: dislocations “trapped” at sidewalls
InP
GeGaAs
Ge
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Aspect Ratio Trapping+ Epitaxial Lateral Overgrowth
Fiorenza ECS 2010
Planar surfaces obtained by epitaxial lateral overgrowth following ART
GaAs MOSFETs demonstrated
Wu, APL 2008
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5. CMOS R&D roadmap*
*grossly oversimplified and biased towards Intel
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III-Vs in CMOS: narrow window of opportunity
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V. Moroz, UCB Seminar 2011
Due to band-to-band tunneling
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Conclusions
• New materials coming into CMOS roadmap:– InGaAs most promising III-V for n-MOSFET– InGaSb most promising III-V for p-MOSFET, also Ge
• Lots of fundamental research needed to chart a path for CMOS beyond Si:
– Interface physics and chemistry with III-Vs– Structures for sub-10 nm gate lengths– MOS gate stack reliability– Integration of n-channel and p-channel devices based on different
materials onto Si substrate