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Sanghun Jeon Ph.D. Associate Professor Department of Applied Physics Korea University Nano-crystalline Oxide Semiconductor Materials for Semiconductor and Display Technology

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Sanghun Jeon Ph.D. Associate Professor

Department of Applied Physics

Korea University

Nano-crystalline Oxide Semiconductor Materials for Semiconductor and Display

Technology

Personnel Profile (Affiliation and Employment) Affiliation

Associate Professor in the Department of Applied Physics at Korea University

Employment

~ 10 Yr experience at Samsung Adv. Inst. Tech., and Samsung Electronics in Semiconductor Area

for Last a Decade with 6 research awards.

12~ Samsung Adv. Inst. Tech., SEC. Principal Research Staff Member

Project leader of Haptic materials and devices (Tactile sensor)

09~11 Samsung Adv. Inst. Tech., SEC. Principal Research Staff Member

Ox-based Device, Lead Device Physicist and Process Integrator

Photo/Image Sensor, Interactive Display, Integrated Circuits, High Power Device Transparent device, 3D

device, Electrical/Reliability/Modeling works.

05~09 Memory Business Division of SEC, Senior Research Staff Member

Charge Trap Flash (8, 16, 32Gb). Process Integrator and Device Engineer.

03~05 Samsung Adv. Inst. Tech., [SAIT] Senior Research Staff Member

Initiative Study on Charge Trap Flash Memory Device.

03 Ph.D. Electronic Materials (Semiconductor Device, MOS dev. & Tr. Tech

(w/ Best Paper Award & Young Researcher Award)

Young Researcher Award at Int. Conf. on SSDM Nagoya Japan 2002)

Education

Technology Transfer @ Samsung Two-time tech. transfer from SAIT to business divisions of SEC, memory

division (2005-2009) and display division (2011)

8Gb

Flash

Device

32Gb

Flash

Tech.

16Gb

Flash

Tech.

1T DRAM Memory

Division of

SEC (2005-

2009)

Basic Research

on CTF

Meeting

Specification of

NAND for 40nm gen.

SAIT (2003-2005) SAIT (2009-2012)

Display Division

of SEC (2011)

Understanding on

science of oxide

Demonstration

of Ox. Sensor

Array

Various

Sensors for

E-Body

Tech. Transfer

Contents

Bilayer oxide transistor exhibits remarkable performance such as, high mobility

(23~47cm2/Vs) and high breakdown voltage (BV) of 60~340V despite low process

temperatures (<300°C), which can be integrated on metal pad.

VLSI 2012VLSI 2012

0 100 200 300 400 50010

-13

10-11

10-9

10-7

200Å

Bi-layer

IZO: 600ÅIZO: 400ÅIZO: 200ÅIZO: 100Å

HIZO-IZO

-HIZO/IZO

Single

HIZO:400Å

I DS @

VG

S-V

TH=

-1V

[A

]

VDS

[V]-20 -15 -10 -5 0 5 10 15 20

10-13

10-11

10-9

10-7

10-5

10-3

VDS

:10V

Bi-layer

IZO: 600ÅIZO: 400ÅIZO: 200ÅIZO: 100Å

HIZO(200Å )-IZO

HIZO:400Å

Single Layer

I DS [

A]

VGS

[V]

0.00

0.05

0.10

0.15

0.20

sat [

cm

2/V

s]

400Å200Å

HIZO-IZO Bi-LayerHIZO

Po

wer,

BV

×I o

n [

W]

Sample

0

10

20

30

40

50

Single Bi-layer

600Å400Å200Å

100Å

IZO Thickness

40mv =>800uA

50nsec

0.000 0.001 0.002 0.003 0.004

L

H

VO

UT

(V

)

Time (sec)

Low Data Latch Output

0.0 2.0m 4.0m 6.0m

L

H

L

H

VO

UT

(V

)

Time (sec)

VIN

(V

)

Monitoring signal

Sample signal

TFT Response Speed

S R

QnQ

IN

OUT

High Data Latch Output

Image Sensor Memory

Power Display

For nc-ox. device, I present various applications.

The Evolution of Devices

• CMOS Logic Device (Si → III-V/ Graphene on Si)

VNAND, VLSI 2009

Planar Structure, IEDM 2006

• Memory (Planar →Vertical/Hybrid Integration)

III-V Integration

RRAM, Adv.

Fuct. Mat. 2008

Si based Integration

AOS TFT

Transition

Ox. Based

RRAM

High-k

metal gate

Graphene

Key Trend: Alternative Materials and 3D Stack

Benefit of nc-InGaZnO, nc-HfInZnO, and

nc-InZnO

• Optical transparency due to large band-gap of ~3.4eV

• Stackable process nature due to low temp. process capability

• Nano-crystalline structure in amorphous matrix (negligible DVth) but High (>10)

→ The integration of nc-oxide semiconductor onto Si circuits is possible.

1

Drift corrected spectrum profile Scanning

IZO

HIZO

CC

D S

pe

ctr

um

pro

file

CCD Spectrum profile

SiO2 HIZO

IZO

Spectrum profile Scanning

IZO

GIZO

GIZO

CCD Spectrum profile

CCD Spectrum profile

CCD Spectrum profile CCD Spectrum profile CCD Spectrum profile

CCD Spectrum profile

CCD Spectrum profile

CCD Spectrum profile

Mo

SiO2

GIZO

GIZO IZO IZO

GIZO

GIZO

Mo

CMOS Image Sensor

Applications

Current Status of CIS Devices

Conventional Architecture New architecture

0

1

2

3

4

5

6

0

20

40

60

80

100

Pix

el S

ize (

nm

)

Resolu

tion (

Mega P

ixel)

2000-2H 2004-2H 2007-2H 2010-2H 2012-2H 2015-2H

FSIS BSIS 3D StackBSIS+ α

(3D Stack)

FSIS: Front side image sensor BSIS: Back side image sensor

Front side image

sensor

Back side image

sensor

Photo diode

Metal 1

Metal 2

Color filter

Photo diode

Metal 2

Metal 1

Color filter

Light path

Light source

Blocked/deflected light

Time

• Like others, CIS devices are facing physical limitation

• Shrinking the pixel size is a major driver for imaging business

• Pixel performance is inversely proportional to the size of CIS

• At a pace which counteract both, new technique is needed

Conventional Architecture New architecture

0

1

2

3

4

5

6

0

20

40

60

80

100

Pix

el S

ize (

um

)

Resolu

tion (

Mega P

ixel)

2000-2H 2004-2H 2007-2H 2010-2H 2012-2H 2015-2H

FSIS: Front side image sensor BSIS: Back side image sensor

Time

Pixel Circuit of CMOS Image Sensor

• A pixel consists of 1 Photodiode (PD) and 4 Transistors.

• Pixel Tr.s (Reset, SF, RS) are shared with neighboring pixels

• Interestingly, all pixel transistors are NMOSFET

• Pixel Tr.s (Reset, SF, RS) with less stringent requirement can be replaced with

oxide TFT

VDD

Co

lum

n B

us

TX11 TX12

TX21 TX22

Reset

RS

SF

PD FD

TX: Transfer Gate Transistor

Reset: Reset Transistor

SF: Source Follower Transistor

RS: Row Select Transistor

PD: Photodiode

FD: Floating Diode

Our Approach

Transparent

conducting line Metal line

Micro-lens

• The integration of electronically active oxide device onto silicon circuit.

• Here we propose a novel hybrid CIS architecture utilizing nanometer scale

nano-crystalline oxide TFT with a photodiode.

nc-oxide TFT

S. Jeon et al., ACS Applied Mat. Int. 2011

S. Jeon et al., IEEE IEDM 2010

Structural Comparison (1st layer)

• This demonstrates how Si PD in active can be enlarged.

Transfer Gate Si

Transistor

Transfer Gate

Transistor Other Pixel

Transistors

Novel Hybrid Conventional

Si PD

Si PD

• The 2nd layer of a novel hybrid four-pixel CIS structure consists of inter-connect

metal lines and other pixel transistors.

• Some interconnect metal lines for delivering constant voltage, VDD, are replaced

by a TCO

Structural Comparison (2nd layer)

TFT

Metal

line

Transparent

Conducting

Line

Micro-lens

Micro-lens

Novel Hybrid Conventional

nc-IGZO TFT

Conventional

Pixel Wavelength (nm) Quantum Efficiency (%) Ratio (%)

Conventional

450

34.3 -

Hybrid + TCO

Interconnect Line 49.2 143

Conventional

540

61.9 -

Hybrid + TCO

Interconnect Line 71.5 116

Conventional

650

41.3 -

Hybrid + TCO

Interconnect Line 49.4 120

Novel Hybrid

• Electromagnetic power density contour plots were calculated by Sentaurus

electromagnetic solver.

• The simulation results reveals a quantum efficiency increase of 143% 116%, and

120% at blue, green, and red wavelengths, respectively.

Simulation Results

Structural Analysis & Electrical Analysis

• Self aligned top gate structure

• Dual gate stack (SiO2/Al2O3)

• Trapezoidal active channel

• nc-oxide semiconductor

-4 -2 0 2 410

-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

Vd=0.1V

Vd=1.0V

Vd=2.0V

Vd=3.0V

Vd=4.0V

Vd=5.0V

I DS(A

)

VGS

(V)

-2 0 2 40

5

10

15

20Vd=3.0V

Mo

bili

ty(c

m2eV

-1se

c-1)

Vg(V)

Mo

IGZO

180nm

SiO2

Al2O3

X-X ’

Y-Y ’

IGZO

Mo

280 320 360 400 440

as-deposited

20 sec

40 sec

60 sec

120 sec

Inte

ns

ity

(C

ou

nts

)

Energy ( keV)

In

Ga,Zn

O

a b

d c

X X’

Y

Y’

Energy (keV)

Inte

nsity (co

un

ts)

In rich region

a-IGZO

AfterBefore

5 nm5 nm

a-IGZO

Gate

IGZO n+G Ox.

n+

Ar + Ar +

X Y

Z

-4 -2 0 2 410

-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

Vd=0.1V

Vd=1.0V

Vd=2.0V

Vd=3.0V

Vd=4.0V

Vd=5.0V

I DS(A

)

VGS

(V)

S. Jeon et al., Applied Physics Letters 2011

Memory Applications

Essential Device Architecture for V-NAND

SiN

High k

SiO2

Si

High FM metal

Planar NAND

Vertical NAND for 1 terabit and beyond

Core CTF Stack for Vertical NAND

S. Jeon et al., US 7,391,075

Revolutionary Transition

Even with revolutionary transition, the core stack remains the same.

Three dimensional approach to high density memory

IEDM 2009, IEEE TED 2011, ACS

Appl. Mat. Int. 2011

ba

Vertical NAND Flash

Oxide TFT for 3D logic

Stackable RRAM

Bottom Si

Layer:CMOS

The schematics of 3D approach Depletion load inverter by hybrid channel

Integrated circuits: Ring oscillator & NOR decoder

Oxide-based integrated circuits

can be applied to integrated

sensors.

Memory Layer

3D Logic

Bottom Logic

Conventional

Architecture

3D Logic

Architecture

Power Applications

Conventional Power and This System

PMIC

Gate DRV Gate DRV

Power TR. Power TR.

Conventional Power system

PMICOxide

Power TR.

PMIC

Power system with gate driver

Gate DRV

using ox. Tr.

Conventional Power System Currently Proposed System

Different device specifications of PMIC & gate driver hinders on-chip integration even with

the merits, such as low cost, reduced form factor, and low noise.

S. Jeon et al., VLSI 2012

High Power Oxide Transistor Technology Bilayer oxide transistor exhibits remarkable performance such as, high mobility

(23~47cm2/Vs) and high breakdown voltage (BV) of 60~340V despite low process

temperatures (<300°C), which can be integrated on metal pad.

VLSI 2012VLSI 2012

0 100 200 300 400 50010

-13

10-11

10-9

10-7

200Å

Bi-layer

IZO: 600ÅIZO: 400ÅIZO: 200ÅIZO: 100Å

HIZO-IZO

-HIZO/IZO

Single

HIZO:400Å

I DS @

VG

S-V

TH=

-1V

[A

]

VDS

[V]-20 -15 -10 -5 0 5 10 15 20

10-13

10-11

10-9

10-7

10-5

10-3

VDS

:10V

Bi-layer

IZO: 600ÅIZO: 400ÅIZO: 200ÅIZO: 100Å

HIZO(200Å )-IZO

HIZO:400Å

Single Layer

I DS [

A]

VGS

[V]

0.00

0.05

0.10

0.15

0.20

sat [

cm

2/V

s]

400Å200Å

HIZO-IZO Bi-LayerHIZO

Po

wer,

BV

×I o

n [

W]

Sample

0

10

20

30

40

50

Single Bi-layer

600Å400Å200Å

100Å

IZO Thickness

40mv =>800uA

50nsec

0.000 0.001 0.002 0.003 0.004

L

H

VO

UT

(V

)

Time (sec)

Low Data Latch Output

0.0 2.0m 4.0m 6.0m

L

H

L

H

VO

UT

(V

)

Time (sec)

VIN

(V

)

Monitoring signal

Sample signal

TFT Response Speed

S R

QnQ

IN

OUT

High Data Latch Output

Display Applications

In-cell touch technologies Displays with touch functionality are in great demand.

“ In-cell touch display” is an industrial goal (integration of

sensor into LCD cell)

Even with various approaches, there is no clear solution to

realize large area interactive display.

Previous photo-sensor technologies based on a-Si are not

applicable for large area touch screen due to low speed.

Information

Display 2010

Motivation of oxide photo-sensor

Large size High resolution

(FHDUD)

Motion picture

(>120Hz)

Large Area Interactive Display

R G B

Display Region Sensor Region

High oxide TFT for

display

• Process compatibility:

oxide sensor

• Display size is limited

by driving speed. 5

cm2/eV/s for UD-level

Gated Three Terminal Sensor Architecture

GateIsolation Ox.

Shield MetalSource/Drain

GIZOIZO

GIZO

Passivation

Gate Ox.

Switch Sensor

High photo-current for oxide sensor leads to simple pixel structure

2 TFT architecture: One sensor TFT & one switch TFT (Shield Metal)

Transparent photo-sensor array due to simple structure

Light

Dark

a-Si Photo TFT array Oxide Photo TFT array

10-1

101

103

105

107

109

10-13

10-11

10-9

10-7

Ox. TFT

a-Si TFT

I DS [

A]

Pulse Cycle [#]

Sensor Switch

Fully Transparent Ox. Sensor Array

S. Jeon et al., Nature Materials 2012

S. Jeon et al., Adv. Mat. 2012

S. Jeon et al., IEEE IEDM 2010

S. Jeon et al., IEEE IEDM 2011

Demonstration of photo-sensor array and Interactive

Display

Array : 192 x 256 lines

(49,152 pixels)

S. Jeon IEDM 2010, Adv. Mat. 2012, SID 2012

Photo-sensor in 2010 Interactive Display in 2011

S. Jeon, Nature Materials

Summary

• NC-oxide semiconductor devices present various device applications.

• We proposes a novel hybrid CMOS image sensor utilizing oxide TFT and

demonstrating excellent device performance of 180nm Lg TFT for future

high density CIS devices.

• We present the three-dimensionally alternating integration of stackable

logic devices with memory cells

• We present high performance bilayer oxide semiconductor such as

HfInZnO/InZnO transistor for high power application

• We have integrated photo-TFTs in a transparent active-matrix

photosensor array that can be operated at high frame rates and that has

potential applications in contact-free interactive displays