Muon Tracker Front-end Electronics

PHENIX FEE Review

June 10-11, 1998

Brookhaven National Laboratory

Belinda Wong-SwansonLANL NIS-4

Tel: 505-665-8787Email: bwong-swanson@lanl.gov

Topics

• MuTr Signal Requirements and Channel Counts

• MuTrFEE Design Team• MuTrFEE Overview

– Technical Design Requirement & Constraints– Detector-FEE Circuit Requirements & Constraints– Cathodes FEM Layout & “FEM” Description– Cathode FEE Counts

Topics (continued)

• Current Status• Prototype Plan and Schedule• MuTrFEE Schedule

– Overall Schedule– Fabrication Schedule– Major Milestones

MuTr Signal Requirements

• Cathodes– 4 pulse-height samples per event (stale hits

rejection)– Channel Matching ~ 1% (after calibration)– Noise < 3000 e¯– 11-bit dynamic range (0.1 10 x 80 fC)– ~750ns integration time & < 12s decay time for

10 –150 pF strip capacitances

MuTr Signal Requirements

• Anodes– Latch (1-bit A/D)

• 10 – 50 pF input capacitance, ~70 ns chg collect’n time

– DO NOT IMPACT ACCEPTANCE• Must hide in shadows of detector octant frames

MuTr Channel Counts

Station phi - cm/ oct str ips/ oct Cathodes r - cm/ oct wi r es/ oct Anodes

1N 104 96 4608 100 96 2304

2N U:208 192 9216 U:187 192 4608

D:214 D:194

3N 354 320 15360 320 320 7680

Subtot N Cathodes 29184 Anodes 14592

1S 104 96 768 100 96 2304

2S U:178 160 7680 U:161 160 3840

D:186 D:168

3S 268 256 12288 241 240 5760

Subtot S Cathodes 24576 Anodes 11904

Totals Cathodes 53760 Anodes 26496

MuTrFEE Team

Function Personnel Institute EffortCPA compl'n & bench test Mark Musrock ORNL/I&C 0.5Det Interconnects & CFTM Gary Smith LANL/NIS-4 0.25Interconnects Details Lee Morrison LANL/NIS-4 0.25Backplane compl'n (& SCI) Manny Echave (Oct98) LANL/NIS-4 0.50CPA det tst & CAIC & CROC Maureen Cafferty LANL/NIS-4 1.00CROC-digital & DAQI Scott Robinson LANL/NIS-4 0.50HV (FPC, LVDC Dist'n, Gnding) Greg Hart (Oct98) LANL/P-25 0.75Prototypes Test Hardware Patricia Saveedra* NMSU EE GS Sum98Prototypes Test Software Andrew Hoover* NMSU Phys GS Sum98Mechanical & Thermal Engr J ake Archuleta LANL/NIS-4 1.00Mechanical Design & Layout Bernie Archuleta LANL/NIS-4 1.00Systems Engineering Belinda Wong-Swanson LANL/NIS-4 0.75Systems Integration & PM Tom Carey LANL/P-25 1.00

*Grad Students have grants Free to PHENIX

MuTrFEE Technical Design Requirements & Constraints

• General– Interface to PHENIX Online System– Provide Ancillary (Remote) Controls & Monitors– Robustness (No access for ~months at a time)

• Nothing between Stations 1 & 2– Station-1 electonics upstream of Station-1

detectors– Stations-2&3 electronics between Stations-2&3

detectors

MuTrFEE Technical Design Requirements & Constraints (cont’d.)

• Stations-2&3 electronics inside magnet– minimal-to-no access for very long periods

• engineer against multiple single-point failures

– low-noise electronics in a magnetic field• no (iron-core) transformers• no electric motors/fans

– low-noise electronics inside a dirty “oven” - 30°C ambient

• cooling in a hot/humid/stagnant environment– fluid-based cooling

– dried atmosphere with good thermal conduction

• enclosures for environmental isolation

MuTrFEE Technical Design Requirements & Constraints (cont’d.)

• Nothing in acceptance downstream of Sta-1– Extremely limited “radial” space at Station-2– Anodes readout must hide behind Sta-2 octant

framesand not enlarge “dead bands” at Sta-3 octant boundaries

• Clear lines of sight for alignment monitoring– Limited space in all dimensions for cathodes

readout at Stations 2&3– Anodes readout must have radial “holes” along

spokes

MuTrFEE Technical Design Requirements & Constraints (cont’d.)

• Limited space in both r and z at Station-1– Also must leave space for BB-counters’ cabling

• Minimal cathode analogue-cable lengths– avoid noise pickup

• Limited magnet “penentrations” availablefor MuTrEE services and signals

– Lower ones consumed by magnet power & cooling

• Must not distort or load detector structures

Top view of an octantbetween Station 2 andStation 3, South-Arm

MuTrFEE Technical Design Requirements & Constraints (cont’d.)

• Top 5 lampshade panels are removable– Cannot attach to/mount anything from them– Must try to avoid having anything delicate near

them• Big, heavy, oddly shaped, unstable orientations

– Can’t rely solely on jigs & rigging fixtures

• Must avoid noise sources safely– Humidity + dissimilar metals cathodic currents

• Need electrical isolation wrt det mounts & magnet

– BUT must not allow hazardous step potentials to develop

Detector-FEE Circuit Requirements and Constraints

• Detectors + FEE constitute a LARGE, DISTRIBUTED, REACTIVE NETWORK– Difficult to establish a “True” Ground– Cathode and Anode electrodes are physically far

apart

• Ground & Power Paths are Intimately Connected to Detector & FEE Operations– Signal Returns are tied to Preamp LV Power Rails

Detector-FEE Circuit Requirements and Constraints (continued)

• Grounding & Power Distribution must be designed to minimize noise and EMI pickup– Especially for Cathodes subsystem

• Grounding & Power Distribution must be designed to protect equipment & personnel

Detector-FEE Power and Grounding Strategies

• Independent returns for all signals to only one common at the detectors– Dedicated plane in detector PCBs

• Isolation of detector frames from magnet to avoid long term degradation of grounds due to corrosion with dissimilar metals

• Low voltage DC power “floated” with respect to (HV + detectors)

Detector-FEE Power and Grounding Strategies (continued)

• Passive ground isolation and filtering in both HV and LV circuits to prevent pickup on power cables from leaking into detector-FEE circuits

• Isolation of FEE frames from detector frames and magnets and mechanical structures.

• Bleeder resistors in HV distribution to allow the detector to discharge in case of HV faults.

Detector-FEE Power and Grounding Strategies (continued)

• Considering active monitoring for ground faults between magnets, detectors, and FEE structures that may lead to step-potentials build-up during abnormal operations or failures.

• Studying details regarding filtering, TVSS, etc. in AC-power system.

Cathodes FEM Layout

FPC

AncillaryControls

& MonitorsCAIC

A

CAIC

B

CROC

B

CROC

A

SCI

BACKPLANE

Cathodes FTM

DAQI

ARCNet

DCM

T&FC

LVDC

Cathode Detector Signals: 64 Strips/CROC, 4 Samples/Strip/Event;128 Strips/FEM==>512 Data words/40usec readout

Definition of MuTr “FEM”

• Chassis has 2 Front End Modules (FEMs)– Half-chassis has 1

FEM

• FEM has– Backplane

• Mates with FEM Transition Module

– Analogue/Digital interconnect for Cathodes/Anodes

Definition of MuTr “FEM” (continued)

– Readout Interfaces (2)• Slow Controls Interface

– ARCNet + Serial for configuration & initialization

• DAQ Interface– Glink-in + Fast Timing & Control + Data Formatter + GLink-

out

» sometimes called “Heap Manager” in other subsystems

Definition of MuTr “FEM” (continued)

– ReadOut Cards • Cathodes ROC (2)

– pre-amp + AMU-ADC + some buffering

– Analogue ins via Cathodes Analogue Input & Calibration Card

» So can replace FEM cards w/o disturbing detector cables

» Analogue inputs perpedicular to fast backplane signals

» Includes circuitry for precision cathodes calibration

To 14channels

Ccal

Ccal

Ccal

Ccal

CH1

CH2

CH3

CH4

Ccal

Ccal

Ccal

Ccal

CH5

CH6

CH7

CH8

To 14channels

To 14channels

To 14channels

PreampASIC1 of 8

CROC

FromDet.

FromDet.

FromDet.

FromDet.

FromDet.

FromDet.

FromDet.

FromDet.

SD_IN

DATACLOCK

BEAMCLOCK

RD_WR*

SUBSEL0

SUBSEL1

SUBSEL2

CRDSEL0

CRDSEL1

CRDSEL2HARDWIRED

CARD SELECTand CONTROL

LOGIC

MB0 (RESET)

MB1 (RESET)

MB6 (CAL)

MB7 (CAL)

MODE_ENBL

BA

CK

PL

AN

E

CO

NT

RO

L L

OG

IC

ENA0

A1

DAC1_8BIT

DAC2_8BIT

DAC3_8BIT

DAC4_8BIT

LATCH

DATACLOCK

RD_WR*LATCH

SWITCH_EN1

SWITCH_EN2

SWITCH_EN3

SWITCH_EN4

VREFANALOG

OUT

8-BITDAC1

NO

NC

SD_OUT1

ENA0A1

SWITCH CONTROL

V

Vr

EN

SWITCH EN1

DATACLOCK

RD_WR*LATCH

VREFANALOG

OUT

8-BITDAC2

NO

NC

SD_OUT2

ENA0A1

SWITCH CONTROL

V

Vr

EN

SWITCH EN2

DATACLOCK

RD_WR*LATCH

VREFANALOG

OUT

8-BITDAC3

NO

NC

SD_OUT3

ENA0A1

SWITCH CONTROL

V

Vr

EN

SWITCH EN3

DATACLOCK

RD_WR*LATCH

VREFANALOG

OUT

8-BITDAC4

NO

NC

SD_OUT3

ENA0A1

SWITCH CONTROL

V

Vr

EN

SWITCH EN4

DATACLOCK

RD_WR*LATCH

DAC1_8BIT

DAC2_8BIT

DAC3_8BIT

DAC4_8BIT

CO

NT

RO

L L

OG

IC

RST

(INJECT)

SD_OUT1

SD_OUT2

SD_OUT3

SD_OUT4

SD_OUT

CAIC

CR

DS

EL

CRD_SEL

RST

RST

RST

RST

(FR

OM

SL

OW

CO

NT

RO

LS

)(F

RO

M T

IMIN

G &

FA

ST

CO

NT

RO

LS

)(F

RO

M S

C)

CROC Block Diagram

Readout controlFull scale count

AMU-ADC

AMU-ADC

11-bits of data

11-bits of data

Write addressRead addressControl

ARCNetTiming &fast controls

8 channelpre-amp

8 channelpre-amp

8 channelpre-amp

8 channelpre-amp

8 channelpre-amp

8 channelpre-amp

8 channelpre-amp

8 channelpre-amp

From cathode analog input and calibration card

MuTrFEE has only 2 ASICs: CPA which is unique to MuTr, and AMUADC which is common to 4 PHENIX subsystems

Cathode FEE Counts

Current Status

• CPA prototype chips now under test– 2 test stands, allow both bench-top and on-detector

tests

– Bench-top test results all agree with expectations from simulations

– 2 minor design mods & no additional prototyping req’d in order for all design specs to be met

– Foresee no obstacles to completion by Jul98

– Additional tests will focus on analog interconnects and CAIC-circuit prototyping

– Ready for CPA Production ASAP after 10/1/98

Current Status (continued)

• Backplane design (including layout and simulation) almost complete (on hold for final decisions regarding proposed simplifications)

• Detailed CFTM and CAIC design underway• Detailing AMUADC timing and control

requirements (to accommodate 4 samples/event) underway

• Preparing for on-detector tests with CPA test stand

Current Status (continued)

• Beginning to develop test equipment for prototype testing of FEM boards

• Completed FEM Chassis design• Detailing cooling system design• Detailing cabling and services plants routing

requirements• Detailing mechanics designs• Beginning to develop installation scenarios.

Cathode Prototype Plan and Schedule

• Plan presented at May98 Muon Arms MiniTAC Review was to delay almost all prototyping until 10/1/98. LANL P-Division has agreed to provide some support for earlier prototyping.

• Plan explicitly incorporates 2 rounds of prototyping.

• Prototyping and integrated-FEM tests to be completed by June 99.

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edu

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ear)

Fabrication & Integration Milestones

• 10/01/98 CPA ASIC production• 06/17/99 Cathodes FEM design integration

and tests completed– Start fab’ing prod’n parts for S-Arm cathodes

• After 04/01/99 (JFY boundary)

• 05/99-09/99 Prepare cathodes FEM test stations

• 08/05/99 Begin FEE infrastructure installation– after detector installation complete

Fabrication & Integration Milestones (continued)

• 09/99-01/00 Assemble and test S-Arm cathodes FEM

• 11/10/99 Begin S-Arm cathodes FEM installation in assembly area

• 02/14/00 S-Arm cathodes FEMs installed– S-Arm ready for roll-in

Major Milestones After S-Arm Installation

• In current project plan– 03/01 N-Arm cathodes FEMs installed– 07/01 S-Arm anodes FEMs installed– 08/01 N-Arm anodes FEMs installed

• These dates are dependent on– access to collision hall– availability of AEE contingency funds for anodes

development and production