multippgle voltage domains (with software...

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Multiple Voltage Domainsp g(with Software Labs)

Material from Vazgen Melikyan, SynopsysCo-developed for MSE Conference 2009

and Synopsys University Program

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Prof. Dejan MarkovićElectrical Engineering Department

University of California, Los Angeles.

Low Power Design Flow

RTL Power Constructs

RTL Simulation

Definition of power domainIsolation behavior of a particular signalRetention behavior of particular registers

Power domain simulationIsolation logic simulation

Create Power Domains

Logic Synthesis

Physical Implementation

Clock GatingApply OpCond on blocksSpecial cell InsertionRetention Cell SynthesisCompileMV DFT

Voltage Area CreationMTCMOS InsertionPhysical synthesisLeakage optimizationMCMMScan reorderingMV aware CTS

Libr

arie

s

2

Verification

Signoff

MV aware Routing

RTL vs. Gates matching

Static Low Power Checks

Parasitic Extraction

SI, Timing, Power Signoff

Power Network Analysis

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UPF

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Unified Power Format (UPF)

UPF

UPF provides the ability for electronic systems to be designed with power as a key consideration early in the process

No existing HDL adequately supports the specification of power distribution and management

Vendor-specific formats are non-portable and create

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opportunities for bugs via inconsistent specifications

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UPF: Definition

UPF Definition

Define power distribution architecture

Power domains

Supply rails

Create power management (operational) scenarios

Switches

Power state tables

Set usage of special low power cells

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Switches

Isolation

Level shifters

Retention

UPF: Basic Design Flow

Design Specification (XML)

RTL UPF+

Power AwareRTL and Gate LevelFunctional VerificationLike Simulation Pattern to Verify

Logic Synthesis

Gate Level UPF

Physical Synthesis

+

Like Simulation Pattern to Verify• Power states from PST• Isolation value• Retention• …

Formal and StructuralVerification like CorrectImplementation of

I l ti

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Gate LevelPG Gate Level

UPF+

1 Power Format for Implementation and Verification

• Isolation• Level shifter• Switches• …

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Library Requirements for UPF (1)

• Level shifters– Identified in .lib by is_level_shifter : true;

• Isolation cells– Identified in .lib by

• Retention registers– Identified in .lib by

is_isolation_cell : true;

retention_cell : cell_type;

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• Power switch (MTCMOS) cells– Identified in .lib by switch_cell_type : coarse_grain;

Library Requirements for UPF (2)• Power / ground (PG) pin

definitions are required for all cells in a library

– Defined as attributes in lib

pg_pin(VDD) {std_cell_main_rail : true ;Defined as attributes in .lib

– Allows accurate definition of multiple power / ground pin information

• Benefits– Power domain driven

synthesis – Automatic power net

connections

voltage_name : VDD;pg_type : primary_power;

}pg_pin(VSS) {voltage_name : VSS;pg_type : primary_ground;

}

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– PST-based optimization– Verification of PG netlist vs.

power domains– Power switch verification– CCS Power library accuracy

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Chip Top Introduction

(Design used in Software Labs)

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ChipTop Logic Design Structure

• Synthesizable RTL code• M lti li GPR M X d Chi T• Multiplier, GPRs, MemX and

MemY are shutdown power domains (PD)

• GENPP is an always-on PD within Multiplier

• Single clock

ChipTop

MemX MemY

PwrCtrl1900um2

InstDecode1197um2

GPRs34150um2

Multiplier46089um2

GENPP

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MemX174304.8um2

MemY174304.8um2

GENPP26009um2Number of clocked elements: 719

Combinational area: 92.315um2

Noncombinational area: 1650996um2

Dynamic Power: 2.6193mWLeakege Poower : 1.39 mW

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Power Management: Operating Voltages

ChipTop(High Volt) GPRs

(Low Volt, High Volt.OFF)

MemX

MemYHier(Low Volt, OFF)

MemXHier(Low Volt, OFF)

GENPP(High Volt)

Multiplier(High Volt, OFF)

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PwrCtrlMemY

Power Nets Scheme

on/offInstDecode

0.8V

VDDI

on/offGPRs

0.8V

VDDGVDD

1.0V

OFF

VDDIS

VSS

1.0V

OFF

VDDGS

VSS

Multiplier

1.0V GENPPChipTop

inst_ongprs_onmult_on

on/off

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1.0V

OFF

VSS

GENPP

1.0V1.0V

VDDMS

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Retention Registers Scheme

on/offInstDecode

0.8V

1.0V

VDDI

VDDIS

on/offGPRs

0.8V

1.0V

VDDG

VDDGS

ISO LS ELSRR

OFF

VSS

ISO LS ELSRR

OFF

VSS

Multiplier

1 0V

VDD

NRESTORE

SAVE

on/off

VDD

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1.0V

OFF VDDMS

VSS

ISO

ISO

GENPP

1.0V

ChipTop

1.0V

Low-Power Design Examples

(Software Labs)

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Low power methodology manual Laboratory works

• Lab 1: Clock gating

• Lab 2: Power gating

• Lab 3: Multi-voltage design

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LPMM Lab1: Clock gating DC commands

• sets the clock gating style used for clock gate insertion and replacement.set_clock_gating_style

• performs clock gating on an appropriately prepared GTECH netlist. insert_clock_gating

• propagates timing constraints from lower levels of the design hierarchy to the current design.

propagate_constraints-gate_clock

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• reports information about clock gating performed by Power Compiler.

report_clock_gating <-hier> <-ungated>

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LPMM Lab1: Clock Gating DC Script#Reading designanalyze -library WORK -format verilog {./RTL/top_odyssey.v./RTL/srff.v ./RTL/power_controller.v}

read_file -format verilog {./RTL/top_odyssey.v}

#Reading UPFsource ./inputs/chiptop+.upf

#Reading constraintssource ./inputs/chiptop+_s0.sdc

#Compilingcompile -exact_map -gate_clock

#Generating clock gating reportreport_clock_gating

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p _ _g g

#Writing out resultschange_names -rule verilog –hier

write -f verilog -h -out ./results/compile.v

write -f ddc -h -out ./results/compile.ddc

save_upf ./results/compile.upf

LPMM Lab1: DC and ICC views

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LPMM Lab1: Results

Clock gating technique (Hw-5: update the numbers)• Total area: 47358.089912 um2

T t l D i P 522 6792 W• Total Dynamic Power : 522.6792 mW

Without Clock gating technique (Hw-5: update…)• Total area: 36996.139839 um2

• Total Dynamic Power : 672.5113 mW

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Area loss: 22%Power gain: 28.6%

LPMM Lab2: Power gating UPF commands

• Creates power domain. Here domain name and elements from it must be specified.create_power_domain

• Creates supply port for mentioned power domaincreate_supply_port

• Creates supply net for power domaincreate_supply_net

• Connects supply nets and portsconnect supply net

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pp y p_ pp y_

• Sets power domain’s power/ground netsset_domain_supply_net

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LPMM Lab2: Power gating UPF commands


C t it h t ifi d d icreate power switch • Creates a power switch at a specified power domaincreate_power_switch

• Defines the UPF isolation strategy for the power domains in the designset_isolation

• Provides additional options needed for creating isolation cells. This command is needed with most set_isolation commandsset_isolation_control

• Defines the UPF retention strategy for the power domains in the designset_retention

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• Defines the UPF retention control signals for the defined UPF retention strategyset_retention_control

• Defines how to map the unmapped sequential cells to retention cells for the specified retention strategy of the power domain.map_retention_cell

create_power_domain TOP

create_power_domain GPRS -elements GPRs

create_supply_port VDD

create_supply_net VDD -domain TOP

LPMM Lab2: Power Gating UPF example (1)

Creating power domains

create_supply_net VDD -domain GPRS –reuse

connect_supply_net VDD -ports VDD

create_supply_port VSS

create_supply_net VSS -domain TOP

create_supply_net VSS -domain GPRS -reuse

connect_supply_net VSS -ports VSS

create_supply_net VDDGS -domain GPRS

t d i l t TOP \

Creating supply nets

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set_domain_supply_net TOP \

-primary_power_net VDD \

-primary_ground_net VSS

set_domain_supply_net GPRS \

-primary_power_net VDDGS \


Setting primary power/ground nets

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create_power_switch gprs_sw \

-domain GPRS \

-input_supply_port {in VDD} \

l { } \

LPMM Lab2: Power Gating UPF example (2)

Creating power switch

-output_supply_port {out VDDGS} \

-control_port {gprs_sd PwrCtrl/gprs_sd} \

-on_state {state2002 in {gprs_sd}}

set_isolation gprs_iso_out \-domain GPRS \

-isolation_power_net VDD \-isolation_ground_net VSS \-clamp_value 1 \-applies_to outputs

Setting Isolation

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set_isolation_control gprs_iso_out \-domain GPRS \-isolation_signal PwrCtrl/gprs_iso \-isolation_sense low \-location parent

Setting Isolation control options

set_retention gprs_ret -domain GPRS \-retention_power_net VDDGS \-retention_ground_net VSS

set_retention_control gprs_retd i \

LPMM Lab2: Power Gating UPF example (4)Setting Retention

Setting -domain GPRS \-save_signal {PwrCtrl/gprs_restore low} \-restore_signal {PwrCtrl/gprs_restore high}

map_retention_cell gprs_ret -domain GPRS -lib_cells RDFFNX1

add_port_state VDD -state {HV 1.2}

add_port_state gprs_sw/out-state {HV 1.2}\-state {OFF off}

create pst chiptop pst -supplies {VDD VDDGS}

Retention control options

Mapping Retention cells to library’s cell

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create_pst chiptop_pst -supplies {VDD VDDGS}

add_pst_state overdrive -pst chiptop_pst -state {HV HV}

add_pst_state function1 -pst chiptop_pst -state {HV HV}

add_pst_state function2 -pst chiptop_pst -state {HV OFF}

add_pst_state hibernate -pst chiptop_pst -state {HV OFF}

add_pst_state sleep -pst chiptop_pst -state {HV OFF}

Port state definition

Creating Port State Table

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LPMM Lab2: Power Gating DC Script#Reading designanalyze -library WORK -format verilog{./RTL/top_odyssey.v ./RTL/srff.v./RTL/power_controller.v}



#Compilingcompile

name_format \-isolation_prefix "ISO_“\-level_shift_prefix "LS_“


#Setting voltages and optionsset_voltage 1.2 -obj {VDD VDDGS}

set_voltage 0.000 -obj {VSS}


write -f verilog-h -out ./results/compile.v

write -f ddc-h -out ./results/compile.ddc


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set auto_insert_level_shifters_on_clocks all

set_dont_touch [get_nets Ovfl]

set_dont_use saed90nm_typ_ht/AODFF*

set_dont_use saed90nm_max/AODFF*

set_dont_use saed90nm_min/AODFF*

LPMM Lab2: Design environment & Tool Chain of Physical Synthesis

RTL Code (Verilog / VHDL)

Designed device

Standard cells

Macro cells cells

I/Ocells

Design Constraints

Gate-level Netlist (Verilog / VHDL)

Logic Synthesis(DC)

Design Library

Physical Design(ICC)

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Design Constraints GDS IIUPF

UPF

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LPMM Lab2: DC and ICC views

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LPMM Lab2: Results

Power gating technique (not fully debugged…)Total Area: 130134.690886 um2

T t l D i P 329 0739 WTotal Dynamic Power: 329.0739 mW

Without Power gating technique (debugging…)• Total area: 88689.9541117 um2

• Total Dynamic Power: 192.3634 mW

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Area loss: 31.8%Power gain: 41.6%

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LPMM Lab3: Multi-Voltage UPF commands


• Creates supply port for mentioned power domaincreate_supply_port

• Creates supply net for power domaincreate_supply_net

• Connects supply nets and portsconnect_supply_net “net

name” -ports “port name”

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• Sets power domain’s power/ground netsset_domain_supply_net

• Applies_to outputs -rule low_to_high -location parent - Create the constraints for Level Shifter cell.set_level_shifter

create_power_domain TOP

create_power_domain GPRS -elements GPRs

create_supply_port VDD

create_supply_net VDD -domain TOP

LPMM Lab3: Multi-Voltage UPF example (1)

Creating power domains

create_supply_net VDD -domain GPRS –reuse

connect_supply_net VDD -ports VDD

create_supply_port VSS

create_supply_net VSS -domain TOP

create_supply_net VSS -domain GPRS -reuse

connect_supply_net VSS -ports VSS

create_supply_net VDDGS -domain GPRS

t d i l t TOP \

Creating supply nets

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set_domain_supply_net TOP \

-primary_power_net VDD \


set_domain_supply_net GPRS \

-primary_power_net VDDGS \


Setting primary power/ground nets

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set_isolation gprs_iso_out \-domain GPRS \

-isolation_power_net VDD \-isolation_ground_net VSS \-clamp value 1 \

LPMM Lab3: Multi-Voltage UPF example (2)

Setting Isolation

p_ \-applies_to outputs

set_isolation_control gprs_iso_out \-domain GPRS \-isolation_signal PwrCtrl/gprs_iso \-isolation_sense low \-location parent

add_port_state VDD -state {HV 1.2}

add_port_state VDDGS -state {LV 0.7}

Setting Isolation control options

Port state definition

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LPMM Lab3: Multi-Voltage DC Script#Reading designanalyze -library WORK -format verilog{./RTL/top_odyssey.v ./RTL/srff.v./RTL/power_controller.v}



#Compilingcompile

name_format \-isolation_prefix "ISO_“\-level_shift_prefix "LS_“


#Setting voltages and optionsset_voltage 0.7 -obj {VDDGS}

set_voltage 1.2 -obj {VDD }

set voltage 0.000 -obj {VSS}


write -f verilog-h -out ./results/compile.v

write -f ddc-h -out ./results/compile.ddc


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set_voltage 0.000 obj {VSS}

set uto_insert_level_shifters_on_clocks all

set compile_preserve_subdesign_interfaces truesetverilogout_show_unconnected_pins true

set_dont_touch [get_nets Ovfl]

set_dont_use saed90nm_typ_ht/AODFF*

set_dont_use saed90nm_max/AODFF*

set_dont_use saed90nm_min/AODFF*

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LPMM Lab3: DC view

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LPMM Lab3: Results

With Multi Voltage technique (Hw-5, update…)Total area: 1781481.983087 um2

T t l D i P 7 2485 WTotal Dynamic Power: 7.2485 W

Without Multi Voltage technique (Hw-5, update…)• Total area: 1215683.305258 um2

• Total Dynamic Power: 10.0721 W

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Area loss: 32%Power gain: 28%

multippgle voltage domains (with software...

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