multiplexers/demultiplexers - welcome to matcecampus.matc.edu/lokkenr/elctec-131/pp...
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Multiplexers/DemultiplexersELCTEC-131
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Basic Multiplexers (MUX) (MUX): A digital circuit that directs one
of several inputs to a single output based on the state of several select inputs.
A MUX is called a m-to-1 MUX.
A MUX with n select inputs will require m = 2n data inputs (e.g., a 4-to-1 MUX requires 2 select inputs S1 and S0).
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Basic Multiplexers (MUX)
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Basic Multiplexers (MUX)
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4-to-1 Multiplexers Truth Table
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S1 S0 Y0 0 D0
0 1 D1
1 0 D2
1 1 D3
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Multiplexer Logic
Boolean expression for a 4-to-1 MUX is
This expression can be expanded to any size MUX so the VHDL architecture could use a very long concurrent Boolean statement.
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013012011010 SS D S S D SS D S S DY +++=
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Double Subscript Notation Naming convention in which variables are
bundled in numerically related groups, the elements of which are themselves numbered.
The first subscript identifies the group that a variable belongs to (D01, D00).
The second subscript indicates which element of the group a variable represents.
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Truth Table for a 4-to-1 4-bit Bus MUX
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S1 S0 Y3 Y2 Y1 Y0
0 0 D03 D02 D01 D00
0 1 D13 D12 D11 D10
1 0 D23 D22 D21 D20
1 1 D33 D32 D31 D30
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Block Diagram 4-to-1 4-bit Bus MUX
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VHDL Constructs For MUXs
The following three VHDL constructs can be used to describe the Multiplexer:
◦ Concurrent Signal Assignment Statement
◦ Select Signal Assignment Statement
◦ CASE Statement
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PROCESS and Sensitivity List
PROCESS: A VHDL construct that contains statements that are executed if a signal in its sensitivity list changes.
Sensitivity list: A list of signals in a PROCESS statement that are monitored to determine whether the Process should be executed.
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Case Statement
A case statement is a VHDL construct in which there is a choice of statements to be executed, depending on the value of a signal or variable.
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Case VHDL Template
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CASE __expression ISWHEN __constant_value =>
__statement;__statement;
WHEN __constant_value =>__statement;__statement;
WHEN OTHERS =>__statement;__statement;
END CASE;
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MUX 4-to-1 VHDL – 1
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Basic Entity declaration for a 4-to-1 MUX: ENTITY mux4case ISPORT(
d0, d1, d2, d3 : IN BIT;
s : IN BIT_VECTOR (1 downto 0);
y : OUT BIT);END mux4case;
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MUX 4-to-1 VHDL – 2
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ARCHITECTURE mux4to1 OF mux4case ISBEGIN
-- Monitor select inputs and execute if they changePROCESS(s)BEGIN
CASE s IS
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MUX 4-to-1 VHDL – 3
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WHEN "00" => y <= d0;WHEN "01" => y <= d1;WHEN "10" => y <= d2;WHEN "11" => y <= d3;WHEN others => y <= '0';
END CASE;END PROCESS;
END mux4to1;
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Multiplexer Applications
Used in directing multiple data sources to a single processing element such as multiple CD Player Streams to a DSP.
Used in Time Division Multiplexing (TDM) by the Phone Service to multiplex multiple voice channels on a single coax line (or fiber).
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Demultiplexer Basics – 1
Demultiplexer: A digital circuit that uses a decoder to direct a single input (from a MUX) to one of several outputs.
A DEMUX performs the reverse operation of a MUX.
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Demultiplexer Basics – 2
The selected output is chosen by the Select Inputs (as in a MUX).
Designated as a 1-to-n DEMUX that requires m select inputs such that noutputs = 2m select inputs.
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Demultiplexer Basics – 3 1-to-4 DEMUX Equations:
They are similar to a MUX and can be designed using CASE Statements.
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. S S D YS SDY
SS D YS S D Y
)()(
)()(
01030102
01010100
;
;;
==
==
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Demultiplexer Basics – 3
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Demultiplexer Basics – 4
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Demultiplexer Basics – 5
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Demultiplexer VHDL Entity
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ENTITY dmux8 ISPORT(
s : IN STD_LOGIC_VECTOR (2 downto 0);
d : IN STD_LOGIC;y : OUT STD_LOGIC_VECTOR (0 to 7));
END dmux8;
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DemultiplexerVHDL Architecture
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ARCHITECTURE a OF dmux8 ISSIGNAL inputs : STD_LOGIC_VECTOR (3 downto 0);
BEGINinputs <= d & s;WITH inputs select
Y <= “01111111” WHEN “0000”,“10111111” WHEN “0001”,
• • •• • •
“11111111” WHEN others;END a;
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Demultiplexer VHDL Architecture
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Lab 13 Multiplexer Application
Create a Block Diagram File for a 4-to-1 multiplexer as shown in Figure 13.1 in Experiment 13.
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Simulation Criteria Each data input channel of the multiplexer will
be selected in an ascending sequence by applying a binary count to the combined select inputs.
Each data input should be easily recognizable by having a “signature” waveform applied to it.
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Simulation Criteria
Each channel should be selected for a period no less than about two or three cycles of the signature waveform.
The output waveform should display a series of unique signature waveforms, indicating the selection of the data channels in the correct sequence.
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Testing the 4-to-1 MUX
Follow the procedure in the Experiment
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Testing the 4-to-1 MUX
Create symbols for the MUX and clock divider.
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Assign pin numbers. When you have assigned the pin numbers, save and compile the file again.
Download the test circuit to the CPLD test board. Test all select combinations.
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Explain your observations in your test report. Compare the y output to the MUX inputs displayed on the d LEDS.
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