multiple xing 4

7/31/2019 Multiple Xing 4

1/33

PHY 201 (Blum)1

Multiplexing and Demultiplexing

In some sense, Multiplexing and Demultiplexing is just aspecial case of the truth tables we have been studying. You

can look under multiplexor and decoder in the index of Tokheim for more information.


2/33

PHY 201 (Blum)2

Getting Around

A fair amount of what goes on inside computers or oncomputer networks just involves moving data (asopposed to processing that data).Most designs have shared information channels (abus).

Part of the path used to get from Point A to Point B mayalso be along the way from Point C to Point D.

Multiplexing and demultiplexing concerns selectingthe data to be transmitted and directing the data to itsdestination.


3/33

PHY 201 (Blum)3

Multiplexing

Multiplexing is sending more than one signalon a carrier.There are two standard types of multiplexing.

Frequency-Division Multiplexing (FDM): themedium carries a number of signals, which havedifferent frequencies; the signals are carried

simultaneously.Time-Division Multiplexing (TDM): differentsignals are transmitted over the same medium butthey do so at different times they take turns.


4/33

PHY 201 (Blum)4

Mutiplexing

Multiplexing allows one to select one of the many possiblesources.


5/33

PHY 201 (Blum)5

Statistical TDM

In standard TDM, the inputs take turns, one afterthe other gets to put its information onto the wire.

In Statistical TDM, the input with the most data orhighest priority gets a higher share of the time.In this course, our wires hold a single bit of information at a time, so we will focus on a simple

type of TDM. It will be somewhat more likestatistical TDM in that we will be choosing whichinput places its information on the wire.


6/33

PHY 201 (Blum)6

Multiplexing

There are several data inputs and one of them isrouted to the output (possibly the sharedcommunication channel).

Like selecting a television channel (although thatexample is FDM).

In addition to data inputs, there must be selectinputs .

The select inputs determine which data input getsthrough.How many select pins are needed?

Depends on number of data inputs.


7/33PHY 201 (Blum)7

Addresses

All of the (data) inputs at hand are assignedaddresses. The address of the data input is

used to select which data input is placed on theshared channel.So in addition to the collection of data inputs,

there are selection (or address) inputs that pick which of the data inputs gets through.


8/33PHY 201 (Blum)8

How many?

One bit can have two states and thus distinguishbetween two things.

Two bits can be in four states and Three bits can be in eight states, N bits can be in 2 N states

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1


9/33PHY 201 (Blum)9

Nomenclature

A Multiplexer is also known as a MUX .A MUX has several data inputs and one dataoutput .If the MUX has N (possible) data inputs , it isreferred to as an N-to-1 MUX.

Since computers work in binary, the N is usually a powerof 2.

An N-to-1 MUX should have log 2(N) address inputs(pins).


10/33PHY 201 (Blum)10

Log 2(N)

N Log 2(N)2 1

4 28 316 432 5

64 6128 7256 8

N Log 2(N)512 9

1024 102048 114096 128192 13

16384 1432768 1565536 16


11/33PHY 201 (Blum)11

Combinatorial Logic

A MUX uses combinatorial logic (as opposedto a sequential logic which involves memory).

The output of a MUX depends solely on thedata input and the select input.Thus it is just the realization of a truth

table.


12/33PHY 201 (Blum)12

Truth table for 2-to-1 MUX

Select Data

OutA D0 D1

0 0 0 0

0 0 1 00 1 0 1

0 1 1 1

1 0 0 0

1 0 1 11 1 0 0

1 1 1 1

When A=0,

Out issame asD0,when

A=1,Out issame asD1


13/33PHY 201 (Blum)13

Algebra for 2-to-1 MUXTake expressions for 1s found in truth table A D0D1 + A D0D1 + AD 0 D1 + AD 0D1

This can be factored as follows

A D0(D 1 +D 1) + A(D 0 +D 0)D 1(D 1 +D 1) = 1Not D 1 or D 1, doesnt care about D 1Note that this factoring/reducing requires the two terms to differ byonly one input.

A D0 + AD 1(A more general technique for simplifying Boolean expressions usesthe Karnaugh map.)


14/33PHY 201 (Blum)14

Karnaugh Version

A B\S 0 1

0 0 0 00 1 0 11 1 1 1

1 0 1 0


15/33PHY 201 (Blum)15

Gates for 2-to-1 MUX

V15 V

J1

Key = 0

J2

Key = 1

J5

Key = A

U1NOT

X1

2.5 V

U2

AND2

U3

AND2

U4

OR2


16/33PHY 201 (Blum)16

4-to-1 MUX: truth table

Select DataOut

A B D0 D1 D2 D3

0 0 D0 D1 D2 D3 D00 1 D0 D1 D2 D3 D11 0 D0 D1 D2 D3 D21 1 D0 D1 D2 D3 D3

D0 could be a 1 or a 0, but if A=0 and B=0 then Outis whatever D0 is.


17/33

PHY 201 (Blum)17

4-to-1 MUX: gate version

Many inputsOne output

V15 V

J1

Key = 0

J2

Key = 1

J3

Key = 2J4

Key = 3

J5

Key = A

J6

Key = B

U1NOT

U2NOT

U3

AND3

U4

AND3

U5

AND3U6

AND3

U7

OR4

X1

2.5 V


18/33


19/33

PHY 201 (Blum)19

Demultiplexing

If any of several signals was put onto a single carrier,then at the other end the signals must be separatedand each sent to the appropriate destination.

One input (the shared channel) is routed to one of several outputs.Like mail, it is possible for me to send a message to anyindividual one of you. So there must be a set of paths fromme to each of you, and there must be a mechanism forselecting one of those paths in a particular instance.

In addition to data input, there must be select inputs.To select from 2 N data outputs requires N select inputs.


20/33

PHY 201 (Blum)20

Demultiplexing

Demultiplexing allows one to select one of the many possibledestinations.


21/33

PHY 201 (Blum)21

NomenclatureDemultiplexer a.k.a. DeMUX .A DeMUX has one data input and several outputs .

If the DeMUX has N (possible) data outputs , it may

referred to as an 1-to-N DeMUX.Since computers work in binary, the N is usually a powerof 2.An 1-to-N DeMUX should have log 2(N) address inputs(pins).DeMUX are also sometimes referred to by the number of address pins log2(N)-to-N DeMUX (e.g. 3-to-8 or 2-to-4DeMUX)


22/33

PHY 201 (Blum)22

Combinatorial Logic

A DeMUX has many outputs.Each of those outputs depends only on theinput data and the select data (i.e. no memoryis involved) .Thus a DeMUX is just a realization of a truth

table (as is all combinatorial logic).


23/33

PHY 201 (Blum)23

1-to-4 DeMux: Truth table

Select Data Output

S1 S0 A O0 O1 O2 O30 0 0 0 0 0 0

0 0 1 1 0 0 00 1 0 0 0 0 0

0 1 1 0 1 0 0

1 0 0 0 0 0 0

1 0 1 0 0 1 01 1 0 0 0 0 0

1 1 1 0 0 0 1


24/33

PHY 201 (Blum)24

1-to-4 DeMUX: gate version (may also becalled 2-to-4)

One input

M a n y o u

t p u t s

V15 V

J1

Key = 0

J5

Key = A

J6

Key = B

U1NOT

U2NOT

U3

AND3

U4

AND3

U5

AND3

U6

AND3

X1

2.5 V

X2

2.5 V

X3

2.5 VX4

2.5 V


25/33

PHY 201 (Blum)25

Decoder

A variation on the previous circuit is to haveno input data.

The selected output will be high, the otherslow.

Or vice versa.

This can be used to activate a control pin onthe selected part of circuit.


26/33

PHY 201 (Blum)26

2-to-4 Decode: Truth table

Select Output

S1 S0 O 0 O1 O2 O30 0 1 0 0 00 1 0 1 0 01 0 0 0 1 01 1 0 0 0 1


27/33

PHY 201 (Blum)27

2-to-4 Decode: gatesV15 V

J5

Key = A

J6

Key = B

U1NOT

U2NOT

X1

2.5 V

X2

2.5 V

X3

2.5 VX4

2.5 V

U3

AND2

U4

AND2

U5

AND2

U6

AND2


28/33

PHY 201 (Blum)28

Decoder plus registers = RAM

A register is a unit of memory that holds one word of data.

A typical word may be 32 or 64 bits.

E.g. the Memory Address Register (MAR) holds anaddress associated with memory

Memory (RAM), on the other hand, is a largecollection of registers to hold the values of many

different words.In addition to the registers is a decoder. The decodedetermines which word one is writing to or readingfrom.


29/33

PHY 201 (Blum)29

Decoder plus registers = RAM

Decoder MDR MAR

Load pins (allow data into a register)

Addressable set of registers

MAR: MemoryAddress registerholds address one iswriting to or readingfrom

MDR Memorydata registerholds databeing written toor being readfrom memory.

Only one location selected.


30/33

PHY 201 (Blum)30

ROM is Combinatorial

In ROM (Read Only Memory), one inputs an addressand gets a predetermined output for that address.

The same input always yields the same output.ROM is the realization of a truth table.ROM is a way to realize a generic truth table.

In a way the opposite of what we do with a Karnaugh map.With a K-map we take a specific output and simplify it asmuch as possible. With ROM, we leave it as generic aspossible.


31/33

PHY 201 (Blum)31

The logic of ROM

Decoder

Addresslines

fuse

Burned

fuse


32/33

PHY 201 (Blum)32

Logic of ROM (Cont.)

Fuses connect output of decoder to output of ROM.

Normal voltage and current does not burn(blow) the fuse. So when the selected decoder output is high,

all ROM output lines to which it is connectedare also high.


33/33

33

Logic of ROM (Cont.)

Higher voltage and current will break theconnections (a.k.a. burning).

They are applied selectively to break certainconnections.The ROM output is not affected by thedecoder output if the connection is broken.(Implementation may be different, but this isthe basic logic).

multiple xing 4

Documents