MULTICHIP MODULE TECHNOLOGY HANDBOOK

Philip E. Garrou Dow Chemical Company

IwonaTurlik Motorola

McGRAW-HILL New York San Francisco Washington, D.C. Auckland Bogota

Caracas Lisbon London Madrid Mexico City Milan Montreal New Delhi San Juan Singapore

Sydney Tokyo Toronto

CONTENTS

1.1 1.2 1.3 1.4 1.5 1.6

Introduction System Packaging Challenges Packaging Efficiency Miniaturization Reliability Future Challenges

References

Preface xv Acknowledgments xvli Contributors xix

Chapter 1. Technical Drivers 1.1

1.1

1.2

1.3

1.5

1.6

1.7

1.10

Chapter 2. MCM-C Materials, Processes, and Applications 2.1

2.1 Introduction 2.2 2.2 Thick Film Hybrids 2.2

2.2.1 Thick Film Technology 2.3 2.2.2 Photoimageable Thick Film Processing 2.4 2.2.3 Diffusion Patteming 2.4

2.3 High-temperature Cofired Alumina (HTCC) 2.5 2.3.1 Introduction 2.5 2.3.2 Materials for HTCC Alumina Packages 2.6 2.3.3 Processing HTCC Ceramics 2.7 2.3.4 HTCC Alumina MCM Conclusions 2.11

2.4 Low-temperature Cofired Ceramic (LTCC) Substrates 2.11 2.4.1 Introduction 2.11 2.4.2 Glass-Ceramic Compositions 2.11 2.4.3 Glass Ceramic Substrate Fabrication 2.14 2.4.4 Future of Glass-Ceramic Substrate Technology 2.17

2.5 Aluminum Nitride 2.17 2.5.1 Introduction 2.17

VÜi MULTICHIP MODULE TECHNOLOGY HANDBOOK

2.5.2 Materials for Multilayered AIN Packages 2.20 2.5.3 AIN Materials and Greensheet Technology 2.20

2.6 Typical MCM Merchant Design Rules 2.23 2.6.1 Kyocera 2.25 2.6.2 NTK 2.23 2.6.3 IBM 2.23

2.7 MCM-C Application Examples 2.25 2.7.1 IBM 2.23 2.7.2 Kyocera 2.25 2.7.3 Unysis 2.26 2.7.4 Fujitsu 2.27 2.7.5 NEC 2.28 2.7.6 Honeywell 2.29 2.7.7 Hughes 2.30 2.7.8 Lockheed 2.30 2.7.9 Dassault 2.31

2.8 Ceramic MCM Future Directions 2.32 References 2.32

Chapter 3. MCM-D Thin Film Materials, Processes, and Applications 3.1

3.1 Introduction 3.2 3.2 Construction Materials 3.2

3.2.1 Thin Film Dielectrics 3.2 3.2.2 Carrier Substrates 3.19 3.2.3 Conductor Metallizations 3.21

3.3 Thin Film Processing 3.23 3.3.1 Dielectric Application and Curing 3.23 3.3.2 Via Formation 3.25 3.3.3 Metal Deposition and Definition Techniques 3.32

3.4 Thin Film MCM Processes 3.36 3.4.1 AT&T 3.36 3.4.2 IBM 3.38 3.3.3 Hughes-HDMI 3.39 3.4.4 MMS 3.41 3.4.5 n-Chip SiCB™ 3.42 3.4.6 General Electric-HDI 3.42 3.4.7 NTK 3.43 3.4.8 Kyocera 3.43 3.4.9 OKI 3.44 3.4.10 IMC 3.45 3.4.11 Thomson 3.45 3.4.12 Fujitsu 3.46 3.4.13 Toshiba 3.46

3.5 Reliability 3.46 3.5.1 Copper/Polymer Interfaces 3.46 3.5.2 Environmental Reliability Testing 3.49

3.6 Application Areas 3.50 3.6.1 Mainframe Computers 3.50 3.6.2 Workstations, Servers, Desktops, and Portables 3.54 3.6.3 Military and Space 3.59 3.6.4 Telecommunication 3.66 3.6.5 Consumer 3.68

References 3.70

CONTENTS ix

Chapter 4. MCM-L Materials, Processes, and Applications 4.1

4.1 Introduction 4.1 4.1.1 Definition of MCM-Ls 4.2 4.1.2 Advantages and Disadvantages of MCM-Ls 4.2

4.2 Basic MCM-L Constructions 4.5 4.2.1 MCM-Ls Using Conventional PWB Constructions 4.8 4.2.2 Few-Chip Package Constructions 4.12 4.2.3 MCM-D/L: Thin Film Additive 4.14 4.2.4 MCM-L Structures Using Flexible Materials 4.21 4.2.5 Historically Important Laminate-Based Technologies 4.26 4.2.6 Emergence of Laser-Based Technology Options 4.29

4.3 Other MCM-L Technologies 4.35 4.3.1 Hitachi Transfer Laminate Circuit Technology 4.35 4.3.2 Toshiba Buried Bump Interconnect Technology 4.35

4.4 MCM-L Substrate Materials 4.37 4.4.1 Organic Base Laminates 4.37 4.4.2 Cast Films 4.39 4.4.3 Metals and Surface Finishes 4.40 4.4.4 Chip Attachment Area and Escape Method 4.41

4.5 Underfill 4.41 4.5.1 Chip-Size Packages 4.42

4.6 Conclusions and Status 4.43 References 4.43

Chapter 5. High-Density, Large-Area Processing (LAP) 4.1

5.1 Introduction and Definitions 5.1 5.1.1 Convergence of MCM Process Technologies 5.1 5.1.2 State of the Art Circuit Density vs. Processing Area 5.2

5.2 Economic Motivations for LAP Thin Film Processing 5.4 5.3 Leveraging the Fiat Panel Display Infrastructure 5.6 5.4 LAP Construction Materials: Options and Limitations 5.7

5.4.1 Substrates 5.7 5.4.2 Dielectrics 5.11 5.4.3 Metallization 5.12

5.5 LAP Unit Operations 5.13 5.5.1 Photoresist and Dielectric—Deposition and Curing 5.15 5.5.2 Metal Deposition and Definition 5.18 5.5.3 Photolithography 5.19 5.5.4 Via Generation by Laser Ablation 5.21 5.5.5 Inspection and Electrical Test 5.22

5.6 High-Density LAP Processes 5.22 5.6.1 Sequential (on Laminate) 5.22 5.6.2 Sequential (Nonlaminate) 5.22

5.7 Conclusions and Future Trends 5.25 References 5.26

Chapter 6. 3-D Packaging 6.1

6.1 Introduction 6.1 6.1.1 Surface Mounting Techniques for Packaged Dice 6.2 6.1.2 Multichip Module Techniques for Unpackaged Dice 6.2

X MULTICHIP MODULE TECHNOLOGY HANDBOOK

6.2 Classification 6.4 6.2.1 Bare Die Assembly vs. Packaged Die Assembly 6.4 6.2.2 Multichip Module Assembly 6.7 6.2.3 Stacked Wafer Assembly 6.7 6.2.4 Stacked Heterogeneous Parts—Microsystems 6.7

6.3 Manufacturing Techniques 6.9 6.3.1 Bare Die Assembly 6.10 6.3.2 Packaged Die Assembly 6.16 6.3.3 Multichip Module Assembly 6.21 6.3.4 Stacked Wafer Assembly 6.28 6.3.5 Stacked Heterogeneous Parts—Microsystems 6.30

6.4 Cost 6.31 6.5 Conclusion 6.32 References 6.35

Chapter 7. MCM Package Design 7.1

7.1 Introduction 7.2 7.2 Mechanical Design Considerations for MCM Packages 7.2

7.2.1 Package Size 7.3 7.2.2 Package I/O 7.11 7.2.3 Expansion Matching 7.14 7.2.4 Compliant Leads 7.14 7.2.5 Vibration and Shock Considerations 7.16

7.3 Electrical Design Considerations for MCM Packages 7.19 7.3.1 Package Lead Characteristics 7.19 7.3.2 Package Body Electrical Characteristics 7.20

7.4 Thermal Design Considerations for MCM Packages 7.21 7.4.1 Temperature Extreme Considerations 7.21 7.4.2 Temperature Rise inside MCM Packages 7.22

7.5 Environmental Design Considerations for MCM Packages 7.23 7.5.1 Thermal Cycling 7.23 7.5.2 Hermeticity Considerations 7.25 7.5.3 Pressure Cycling 7.33 7.5.4 Hermetic-Equivalent Packaging, Moisture and Corrosion Resistance,

Reliability without Hermeticity 7.34 7.6 Examples of MCM Package Design Approaches 7.35

7.6.1 Premolded Plastic MCM Packages 7.35 7.6.2 Postmolded Plastic MCM Packages 7.35 7.6.3 Encapsulated Chip-on-Board MCM Packages 7.36 7.6.4 Metal Hermetic MCM Packages 7.36 7.6.5 Ceramic Hermetic MCM Packages 7.36

7.7 Cost Considerations for MCM Packaging 7.37 References 7.42

Chapter 8. Assembly 8.1

8.1 Introduction 8.2 8.2 Facilities and Handling 8.4 8.3 Electrostatic Discharge 8.7 8.4 Die Attachment 8.10

8.4.1 Epoxy 8.10

3.5

8.6

8.4.2 Polyimides 8.4.3 Thermoplastics 8.4.4 Solder 8.4.5 Other Die Attach Materials Wire Bonding 8.5.1 Thermosonic Wire Bonding 8.5.2 Ultrasonic Wire Bonding 8.5.3 Wire Bond Quality 8.5.4 Wire Bonding Equipment 8.5.5 Bonding Wire 8.5.6 Substrate Metallization and Reliability Considerations 8.5.7 Plasma Cleaning 8.5.8 Rework 8.5.9 Wire Bond Summary Tape Automated Bonding 8.6.1 Bump Formation 8.6.2 Inner Lead Bonding 8.6.3 Testing 8.6.4 Outer Lead Bonding 8.6.5 Rework 8.6.6 Tape Automated Bonding Summary Flip Chip 8.7.1 Bump Formation 8.7.2 Assembly 8.7.3 Reliability 8.7.4 Rework 8.7.5 Flip Chip Summary Assembly Summary inces

CONTENTS xi

8.15 8.15 8.15 8.16

8.16 8.17 8.20 8.21 8.23 8.24 8.24 8.27 8.27 8.27

8.29 8.30 8.32 8.35 8.35 8.36 8.38

8.38 8.39 8.46 8.50 8.50 8.52

8.53

8.56 8.8

Chapter 9. Module-to-Board Connections 9.1

9.1 Introduction 9.1 9.1.1 Off-the-Shelf Connector Approach 9.2 9.1.2 Customized Connector Approach 9.2

9.2 Requirements 9.2 9.2.1 Electrical Requirements 9.2 9.2.2 Thermal Capabilities 9.3 9.2.3 Mechanical Compatibility 9.3 9.2.4 I/O Requirements 9.3 9.2.5 MCM Connection System Reliability 9.4

9.3 Attachment Approaches 9.5 9.3.1 Peripheral I/O Connections 9.5 9.3.2 Array Connections 9.5

9.4 Survey of MCM Attachment Options 9.6 9.4.1 Pins 9.6 9.4.2 Solder Joints at the MCM-PCB Interface 9.7 9.4.3 Compliant Springs at the MCM-PCB Interface 9.9 9.4.4 Conductive Adhesives 9.17 9.4.5 FlexCircuits 9.18

9.5 Trends and Future Requirements 9.20 References 9.21

XÜ MULTICHIP MODULE TECHNOLOGY HANDBOOK

Chapter 10. MCM Design 10.1

10.1 Introduction 10.1 10.2 Chapter Purpose 10.1 10.3 Reasons for a Design Infrastructure 10.2 10.4 MCM CAD Process 10.3

10.4.1 Design Conception 10.5 10.4.2 Startingthe Design Phase 10.5 10.4.3 Library Generation 10.7 10.4.4 Design Capture 10.8 10.4.5 Netlist Generation 10.9 10.4.6 Prelayout Design Evaluation 10.9 10.4.7 Physical Design 10.13 10.4.8 Backannotation 10.17 10.4.9 Manufacturing Data 10.17 10.4.1 OPostlayout Analysis 10.17 10.4.11 MCM Test Strategy 10.18

10.5 Summary 10.20 Acknowledgment 10.21 Suggested Readings 10.21

Chapter 11. MCM Eiectrical Performance Analysis 11.1

11.1 Introduction 11.1 11.2 Basic Building Blocks of Eiectrical Interconnections 11.2

11.2.1 Transmission Lines 11.2 11.2.2 I/O Buffers 11.5

11.3 Role of Physical Scale and Structure in Transmission Lines 11.6 11.3.1 Transmission Line Properties 11.7 11.3.2 When Is Controlled Impedance Important? 11.8

11.4 Materials Properties and Transmission Lines 11.10 11.4.1 Metal Resistivity and Permeability 11.10 11.4.2 Resistance and Skin Effects 11.11 11.4.3 Dielectric Constant 11.11

11.5 Estimating Delays 11.13 11.5.1 Time-Constant Estimates for Point-to-Point Interconnections 11.13 11.5.2 Time-Constant Estimates for Bus Interconnections 11.16

11.6 Delay Simulations and Examples 11.18 11.7 A System Design Perspective on Delays 11.22

11.7.1 Delay vs. Interconnection Length 11.22 11.7.2 System Size and Delay Budget 11.22

11.8 Conclusions 11.23 References 11.24

Chapter 12. Electronic Packaging for High-Performance Digital ICs 12.1

12.1 Introduction 12.2 12.2 MCMs Operating in Support of High Clock Rate Digital ICs 12.2 12.3 MCMs and High-Speed IC Design 12.9 12.4 Review of the Different MCM Types 12.10

12.4.1 MCM-Ls 12.10

CONTENTS XIII

12.4.2 MCM-Cs 12.11 12.4.3 MCM-Ds 12.12 12.4.4 Chips-First MCMs 12.14 12.4.5 Chip-On-Board 12.14

12.5 MCM Features Required for High Clock Rate Digital Systems 12.14 12.6 Transmission Line Effect on MCM Design and Fabrication 12.17 12.7 Achieving Low-Loss Interconnects on MCMs 12.26 12.8 Multiple Power and Ground Planes in High Clock Rate MCMs 12.32 12.9 Electrical Interconnect of Chips to the MCM 12.42 12.10 Thermal Environment of High Clock Rate Digital MCMs 12.47 12.11 Testing of High-Performance MCMs 12.49

12.11.1Test Fixtures for MCMs 12.49 12.11.2Passive Testing of MCMs 12.56 12.11.3External Testing of Active-Circuit MCMs 12.58 12.11.4Built-ln Self-Testof High-Performance MCMs 12.60

12.12 Rework and Repair of High Clock Rate MCMs 12.61 12.13 Packaging of MCMs 12.62 12.14 Additional Requirements for First-Pass Functionality:

Electromagnetic Modeling Tools 12.64 12.14.1 Electromagnetic Parameter Extraction 12.64 12.14.3Modeling Noise Disturbances in Power and Ground Planes 12.72 12.14.2Simulation of Propagating Signal Wavefronts 12.71 12.14.4Has Your EM Modeling Tool Been Validated? 12.75

12.15 The Future: Mixed-Signal Multichip Modules 12.76 Acknowledgments 12.78 References 12.80 Appendix: A Brief Discussion of S-parameters 12.83

Chapter 13. Thermal Management 13.1

13.1

13.2

13.3 13.3

13.16

13.26

13.29

References 13.31

Chapter 14. Known-Good Die 14.1

14.1 Introduction 14.2 14.1.1 ConceptofKGD 14.2 14.1.2 Impact of KGD on Yield 14.3

14.2 Background 14.4 14.2.1 Traditional Integrated Circuit Manufacturing Flow 14.5 14.2.2 Bare Die Supplier Concerns 14.7 14.2.3 Defect Activation 14.8 14.2.4 Reliability Prestress 14.8 14.2.5 Electrical Pretest 14.11

13.1 13.2 13.3

13.4 13.5

Introduction Thermal Performance Figures of Merit MCM Cooling Designs 13.3.1 Air-Cooled Modules 13.3.2 Liquid-Cooled Modules Technology Comparison Future Challenges

XIV MULTICHIP MODULE TECHNOLOGY HANDBOOK

14.3 Recent Progress on KGD 14.16 14.3.1 Industry and Government KGD Initiatives, Evolution, and Accomplishments 14.18 14.3.2 Standards for Unpackaged Chips 14.18 14.3.3 Die Information Exchange Format 14.21 14.3.4 Known-Good Die Technologies 14.23 14.3.5 Levels of Test and Reliability 14.32

14.4 Remaining Issues 14.43 14.4.1 KGD Availability 14.46 14.4.2 Quantification and Measurement of KGD Level 14.48 14.4.3 Cost, Cost, Cost 14.51

14.5 Future Improvements 14.56 14.5.1 Wafer-Level KGD Assurance Technologies 14.56 14.5.2 Singulated Bare Die Testing 14.58 14.5.3 Information Technology: Surfing the Internet for KGD 14.61 14.5.4 KGD from PPM IC Processing 14.62 14.5.5 Füll KGD Availability 14.62

14.6 Conclusions 14.63 Acknowledgments 14.63 References 14.63

Chapter15. MCM Test and Design for Test 15.1

15.1 MCM Test Issues 15.1 15.2 Faults and Defects in MCMs 15.2

15.2.1 Physical Faults/Defects 15.3 15.2.2 Fault Models 15.4

15.3 Test Metrics and Economics 15.5 15.3.1 Fault Coverage 15.5 15.3.2 Yield 15.7 15.3.3 Defect Level and Test Leakage 15.7 15.3.4 Test-Related Cost Issues 15.8

15.4 Test Design and Test Vector Generation 15.10 15.4.1 Test Vectors and Automatic Test Pattern Generation 15.11 15.4.2 Design Modeling and Simulation 15.13 15.4.3 Fault Simulation 15.15

15.5 Substrate Testing and Inspection 15.15 15.5.1 Electrical Test Methods 15.15 15.5.2 Mechanical Contact Probe Testers 15.19 15.5.3 Noncontact Methods 15.22 15.5.4 Automatic Optical Inspection 15.25

15.6 MCM Assembly Testing 15.28 15.6.1 MCM Interconnect Testing 15.29 15.6.2 In-Circuit Test Approaches 15.30 15.6.3 ASIC Approaches to MCM Assembly Testing 15.33

15.7 Design for Testability 15.36 15.7.1 Ad-Hoc Methods 15.36 15.7.2 MCM-Level Boundary Scan 15.37 15.7.3 Internal Scan Design 15.41 15.7.4 Built-In Self-Test 15.47

References 15.54

Index 1.1