multi-target production code generation for optimal use of
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1© 2015 The MathWorks, Inc.
Multi-target
Production Code Generation for
optimal use of Hardware Resources
Sebastien Dupertuis, EngD, B.Sc.
Senior Applications Engineer
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Three Key Takeaways
Target heterogeneous systems from one model in MATLAB and Simulink
Automation through automatic code generation and connect to hardware
Verification at each step of the development process
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ChallengeDevelop and deliver such a complex and reliable product
without spending too much time and money
SolutionUse Model-Based Design to model, implement, test, and
deploy the MIMO system onto an embedded hardware
Results Improved time to market and used fewer prototypes
156k+ lines of source code generated in 15 minutes
No bugs in the generated code since the project began
Validation time for ventilation performance reduced by
80%, 2 weeks down to 2 days
IMT Developed a highly complex ventilator called
Bellavista, partially unknown, MIMO system
requiring total robustness and reliability
“Model-Based Design not only helps to deal
with highly complex MIMO systems, but also
enables us to identify problems early in the
development process. That reduces costs and
improves time to market.”
Matthias van der Staay
IMT
Exhibitor: IMT
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Agenda
Multi-target Production Code Generation
– Who
– Capabilities
– Workflows
– Standards
– Summary
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Philips Healthcare MRI scannerAirSonea device, which connects
to a patient’s smartphone
Sonova’s hearing aid and
cochlear implant solutions
Toyota engine
Alstom Grid’s HVDC demonstrator system
with power converter modules
http://ch.mathworks.com/company/user_stories/
The HB-SIA aircraft on a test
flight over San Francisco Bay Photo © Solar Impulse | Revillard | Rezo.ch
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Model-Based Co-Design for C and HDL
Systems
Software Hardware
http://www.mathworks.com/tagteam/75977_Concepts_to_Chips_SELEX_ES.pdf
Motor Control
Doppler Radar
FIL
HIL
PIL
PIL: Processor-in-loop
FIL: FPGA-in-loop
HIL: Hardware-in-loop
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Agenda
Multi-target Production Code Generation
– Who
– Capabilities
– Workflows
– Standards
– Summary
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Modeling: Three methods
Simulink
Simulink
Stateflow MATLAB
Block Oriented For Systems Design
Textual for Concise Numerics
State Machines for Event-based Logic
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Code Generation: Five languages
Model
Code
• C/intrinsics
• C++
• VHDL
• Verilog
• Structured Text
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Hardware Support: Any device
Portable code: any device for
algorithm code generation
supported
Support packages offer select
target-specific system
executable generation and
workflows
– ARM … C2000 … Zynq
Hardware vendors offer their own
support packages
– Freescale, Infineon, Microchip,
Renesas, TI, STMicroelectronics, ...
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System-on-
Chip
Challenge: Selecting the Right Hardware?
PLC/PAC
MCU/DSP FPGA/ASIC
HW Characteristics:
• Price
• Sampling frequency
• Workflow complexity
• Form-factor
• Availability
• ….
Let’s make an informed decision on HW selection within the development process...
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Code generation for PLC / PAC
Target-Independent Models:
– Enabling design portability across PLC HW
Workflows:
– IEC 61131-3
– Rockwell
– Siemens
– Beckhoff
– B&R
– …
Structured
TextGenerate
Verify
PAC
PLC
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Code Generation for DSP / MCU / SoC
Target-Independent Models:
– Enabling design portability across DSP/MCU
and SoC
Workflows:
– ANSI C/C++
– TI, ARM, etc
– Verification In-the-Loop
– Rapid prototyping and HIL test
– Certification and standards
Optimized code for production:
– Target-aware code (ARM, TI, etc)
Structured
TextGenerate
Verify
PAC
PLC
C/C++Generate
Verify
DSP
MCU
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Code Generation for FPGA / ASIC / SoC
C/C++Generate
Verify
MCU
DSP
VHDL /
VerilogGenerate
Verify
ASIC
FPGA
Structured
textGenerate
Verify
PAC
PLC Target-Independent Models:
– Enabling design portability across
FPGA/ASIC and SoC
Workflows:
– Verilog/VHDL
– Xilinx, Altera, SoC
– HDL co-simulation (Mentor/Cadence)
– Verification In-the-Loop
– Rapid prototyping
– Certification and standards
Optimized code for production:
– Resource sharing, timing optimization
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MathWorks Coders
C/C++Generate
Verify
MCU
DSP
VHDL /
VerilogGenerate
Verify
ASIC
FPGA
Structured
textGenerate
Verify
PAC
PLC
One model to
many targets
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Agenda
Multi-target Production Code Generation
– Who
– Capabilities
– Workflows
– Standards
– Summary
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Design Elaboration
Algorithm Environment
E.g. Floating-point or Fixed-point?
Sample Times
Discrete or time continuous
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Algorithm Environment
Non-Real-Time functional
verification of the algorithm
component
Component Testing and ProfilingAlgorithm verification via SIL, PIL, FIL
Is the generated
code functionally
equivalent to the
model ?
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Algorithm Environment
Prototyping
Does algorithm
perform well on
actual device
with true
latencies?
Harness
Code
Exhibitor: Speedgoat
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Algorithm Environment
Production Code Generation
Does the code
work on
production
hardware?
Code
Exhibitor: MathWorks
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Results for ARM Cortex-A (FIR Filter)
410.7
185.5
16.8 14.1
ANSI, No Opt ANSI, Opt NE10, No Opt NE10, Opt
1x
Run Format: [ANSI or Ne10], [gcc no opt or gcc -02], ARM 1Ghz Cortex A8
Embedded Coder ANSI-C
Embedded Coder ANSI-C
(& GCC optimized)
Embedded Coder,
NEON Optimized
Embedded Coder,
NEON Optimized
(& GCC Optimized)Execution T
ime
2.2x
24.5x 29.1x
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Results for Xilinx Zynq-7000 All-Programmable SoC
3014%
178%
104%
Baseline Constant Multipliers Resource Sharing
Strategy
DS
P r
esourc
es
Example: Field-Oriented Controller
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Agenda
Multi-target Production Code Generation
– Who
– Capabilities
– Workflows
– Standards
– Summary
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Coding Standards
MISRA-C STARC HDL
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Model-Based Design – Certification Examples
TRW Germany
Electronic parking brake control system
Honeywell Aerospace USA
Flight Control Systems
Weinmann Medical Germany
Transport ventilator
Alstom France
Train Control Systems
Alstom Grid UK
HDVC Power Systems
DO-178B (Level A)
EN 50128IEC 62304 IEC 61508
ISO 26262
Airbus Helicopters
Certified flight software
ARP4754 & DO-178
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Agenda
Multi-target Production Code Generation
– Who
– Capabilities
– Workflows
– Standards
– Summary
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Get Started with Automatic Code Generationuse 5 proven principles
1. Experiment with a small piece of the project
2. Re-use system-level models for implementation
3. Use automatic code generation to iterate
towards maximum performance
4. Pick hardware platform that make sense for you
5. Take advantage of MathWorks resources
Link to MathWorks white paper
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32© 2015 The MathWorks, Inc.