M t A l i dMeasurement, Analysis and Improvement of Supply Noise in 3D ICs

Pulkit Jain Dong JiaoPulkit Jain, Dong Jiao, Xiaofei Wang, and Chris H. Kim

University of Minnesota, Minneapolis, MN

pulkit@umn.eduwww umn edu/~chriskim/

Symposia on VLSI Technology and Circuits

www.umn.edu/~chriskim/

Outline• Introduction• Through Si Via (TSV) Characterization oug S a ( S ) C a acte at o• Supply Noise Measurement Macro

Tier to tier Supply Noise– Tier-to-tier Supply Noise– 3D vs. 2D DC Noise– 3D vs. 2D AC Noise

• Multi-story Power Delivery (MSPD) Scheme– Demonstration on 3D SRAM

• SummarySummary

Slide 1

3D IC: Motivation and Challenges

Source: Global foundries

• Motivation– Reduced footprint

• Challenges– Yield

Global foundries

p– Heterogeneous integration– High memory bandwidth

– Thermal congestion– EDA tools support

Slide 2

– I/O power reduction – Power delivery

3D Cross Section Examples

• Heat sink at bottom while I/O pads at top• 3 tier stack requires a combination of F-F & F-B

3D processes differ for bulk and SOI cases

Slide 3

• 3D processes differ for bulk and SOI cases

Proposed TSV Char. & Supply Noise Measurement Test ChipNoise Measurement Test Chip

3D

4mm

TSV probeMIT Lincoln Lab 150nm 3D FD-SOI

3D noise

3D SRAMTSVTSV

block

2D noise

3D noise

• Goal: Evaluation of TSV impact on supply noiseM d l d i & t ti ifi 2D d I/O bl k

Slide 4

• Modular design & t-tier specific 2D and I/O blocks

TSV Characterization Methods

• Conventional approaches of direct probing are invasive and not scalable

• ROSC based evaluation yields frequency info directly, and hence more relevant for logic circuits

Slide 5

and hence more relevant for logic circuits

Statistical TSV Char. Block

• 3 possible topologies of TSV loaded ROSCs3 possible topologies of TSV loaded ROSCs • Flexible number of TSVs in 105 chain structure

used

Slide 6

used

Tier-to-tier Variation150nm 3D FD-SOI 1 5V 25°C150nm 3D FD-SOI, 1.5V, 25 C

30 17% variation ti

No TSV case

OSC

s

20

across tiers

t

% o

f R

10b

m

0.9 1 1.1 1.2 1.30

• Isolate inter-tier systemic variation before ti ti TSV i t

ROSC period (normalized)

Slide 7

estimating TSV impact

Measured 3D-ROSC Characteristics

• Inter-tier variation calibrated out as 2D and 3D were locally correlated (r > 0.98)3D ROSC period 13 52% slower than 2D ROSC

Slide 8

• 3D-ROSC period 13-52% slower than 2D-ROSC

TSV Capacitance

• Simple linear model: CTSV=NINV/TSVCINV∆T3D/T2D• 30% coupling effect, 35% topology effect, no

Slide 9

effect of environment variables

TSV Resistance

• R of inter-TSV and bonding wires calibrated out• R of stacked TSV > sum of individual TSVs

Slide 10

R of stacked TSV sum of individual TSVs

Proposed TSV Model

• Average values of TSV R and C estimated from th d t ti ti l d tthe measured statistical data

Slide 11

Supply Noise Measurement Setup

• DC noise tapped by Kelvin probing• DC noise tapped by Kelvin probing• AC noise is sensed by on-chip supply noise sensor• Noise generation circuit produces programmable

Slide 12

g p p gmagnitude and frequency of current noise

DC Noise Comparison30

160300t tierm tier 2D

3DTotal dropI/O drop

150nm 3D FD-SOI, 1.5V, 25°C

20 -69%

80

120200

b tier TSV drop

0

10 3.8X

0

40

0

100 2D has 3X pads

Thi IR d i I/O >> TSV d

0 400 800Current (mA)

0 200 400 600Current (mA)

0 400 800Current (mA)

800

• This process: IR drop in I/O >> TSV drop• IR noise severely exacerbated in 3D due to

reduced # of I/O pins

Slide 13

reduced # of I/O pins

I/O and TSV Count Dependency

• Extrapolations based on smaller current noise

Slide 14

• For example, 4A load and 140 pads would need 150 TSVs

AC Noise Measurement: 2D vs. 3D

• The difference between the three tiers expected to be negligible due to small decap and damping effect of TSV

Slide 15

• Peak noise unchanged but frequency spectrum altered

Multi-story Power Delivery (MSPD) Single story Two storySingle story Two story

Raja. et al., VLSI’04Gu et al., ISLPED’05

• Current consumption halved at same drawn power• The middle node is ‘quiet’ due to current balance

3D IC ff dil bl l t k

Slide 16

• 3D ICs offer readily separable power supply networks

Proposed MSPD Scheme

DC DC DC DC

b

• MSPD across different tiersWorst case MSPD one story is not switching

Slide 17

• Worst case MSPD one story is not switching

MSPD DC Noise Measurements

• Same number of pads assumedW f MSPD i 1 4X I

Slide 18

• Worst case for MSPD promises 1.4X IMAX

MSPD Demonstration on 3D-SRAM

• All tiers identical except for I/O and control path on top tier. Stacked TSVs on peripheryC t i l i t t

Slide 19

• Concentric supply ring structure

MSPD Demonstration on 3D-SRAM

• Simulations show 19% FMAX and 15% latency improvements (with 10% more DC noise in conv )

Slide 20

10% more DC noise in conv.)

Summary• A 3D test chip for power supply measurement

fabricated in a 150nm fully depleted SOI process • TSV impact on circuit delay measured using

ROSCs3D ROSC 14 52% l th 2D– 3D ROSCs 14-52% slower than 2D

– TSV loading equivalent to 40-55% FO1 delay• DC noise becomes a bigger issue in 3D• DC noise becomes a bigger issue in 3D

– Limited I/O pins reduces max. current by 69% from 2D– Novel MSPD scheme increases max current by 40%Novel MSPD scheme increases max. current by 40%

• A 393kb 3D SRAM demonstrates efficient MSPD implementationimplementation

Slide 21