MSP430FR58xx, MSP430FR59xx,MSP430FR68xx, and MSP430FR69xx Family

User's Guide

Literature Number: SLAU367FOctober 2012Revised January 2015

Contents

Preface....................................................................................................................................... 351 System Resets, Interrupts, and Operating Modes, System Control Module (SYS)....................... 37

1.1 System Control Module (SYS) Introduction ............................................................................ 381.2 System Reset and Initialization........................................................................................... 38

1.2.1 Device Initial Conditions After System Reset.................................................................. 401.3 Interrupts .................................................................................................................... 40

1.3.1 (Non)Maskable Interrupts (NMIs) ............................................................................... 411.3.2 SNMI Timing ....................................................................................................... 411.3.3 Maskable Interrupts ............................................................................................... 411.3.4 Interrupt Processing............................................................................................... 421.3.5 Interrupt Nesting................................................................................................... 431.3.6 Interrupt Vectors................................................................................................... 431.3.7 SYS Interrupt Vector Generators................................................................................ 44

1.4 Operating Modes ........................................................................................................... 461.4.1 Low-Power Modes and Clock Requests ....................................................................... 481.4.2 Entering and Exiting Low-Power Modes LPM0 Through LPM4............................................. 491.4.3 Low Power Modes LPM3.5 and LPM4.5 (LPMx.5) ........................................................... 49

1.5 Principles for Low-Power Applications .................................................................................. 511.6 Connection of Unused Pins ............................................................................................... 521.7 Reset Pin (RST/NMI) Configuration ..................................................................................... 521.8 Configuring JTAG Pins .................................................................................................... 521.9 Vacant Memory Space .................................................................................................... 531.10 Boot Code ................................................................................................................... 53

1.10.1 IP Encapsulation (IPE) Instantiation by Boot Code .......................................................... 531.10.2 IP Encapsulation Signatures ................................................................................... 531.10.3 IP Encapsulation Init Structure ................................................................................. 541.10.4 IP Encapsulation Removal ..................................................................................... 54

1.11 Bootstrap Loader (BSL) ................................................................................................... 551.12 JTAG Mailbox (JMB) System ............................................................................................ 55

1.12.1 JMB Configuration ............................................................................................... 551.12.2 JMBOUT0 and JMBOUT1 Outgoing Mailbox................................................................. 561.12.3 JMBIN0 and JMBIN1 Incoming Mailbox....................................................................... 561.12.4 JMB NMI Usage .................................................................................................. 56

1.13 JTAG and SBW Lock Mechanism Using the Electronic Fuse........................................................ 561.13.1 JTAG and SBW Lock Without Password ..................................................................... 571.13.2 JTAG and SBW Lock With Password ......................................................................... 57

1.14 Device Descriptor Table ................................................................................................... 571.14.1 Identifying Device Type.......................................................................................... 581.14.2 TLV Descriptors .................................................................................................. 591.14.3 Calibration Values................................................................................................ 60

1.15 SFR Registers .............................................................................................................. 631.15.1 SFRIE1 Register ................................................................................................. 641.15.2 SFRIFG1 Register ............................................................................................... 651.15.3 SFRRPCR Register .............................................................................................. 67

1.16 SYS Registers .............................................................................................................. 68

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1.16.1 SYSCTL Register ................................................................................................ 691.16.2 SYSJMBC Register .............................................................................................. 701.16.3 SYSJMBI0 Register.............................................................................................. 711.16.4 SYSJMBI1 Register.............................................................................................. 711.16.5 SYSJMBO0 Register ............................................................................................ 721.16.6 SYSJMBO1 Register ............................................................................................ 721.16.7 SYSUNIV Register ............................................................................................... 731.16.8 SYSSNIV Register ............................................................................................... 731.16.9 SYSRSTIV Register ............................................................................................. 74

2 Power Management Module (PMM) and Supply Voltage Supervisor (SVS)................................. 752.1 Power Management Module (PMM) Introduction ...................................................................... 762.2 PMM Operation ............................................................................................................. 77

2.2.1 VCORE and the Regulator .......................................................................................... 772.2.2 Supply Voltage Supervisor ....................................................................................... 772.2.3 Supply Voltage Supervisor - Power-Up ........................................................................ 782.2.4 LPM3.5 and LPM4.5 .............................................................................................. 782.2.5 Brownout Reset (BOR) ........................................................................................... 782.2.6 RST/NMI............................................................................................................ 792.2.7 PMM Interrupts .................................................................................................... 792.2.8 Port I/O Control .................................................................................................... 79

2.3 PMM Registers ............................................................................................................. 802.3.1 PMMCTL0 Register (offset = 00h) [reset = 9640h] ........................................................... 812.3.2 PMMCTL1 Register (offset = 02h) [reset = 9600h] ........................................................... 822.3.3 PMMIFG Register (offset = 0Ah) [reset = 0000h] ............................................................. 832.3.4 PM5CTL0 Register (offset = 10h) [reset = 0001h] ............................................................ 84

3 Clock System (CS) Module .................................................................................................. 853.1 Clock System Introduction ................................................................................................ 863.2 Clock System Operation................................................................................................... 88

3.2.1 CS Module Features for Low-Power Applications ............................................................ 883.2.2 LFXT Oscillator .................................................................................................... 883.2.3 HFXT Oscillator.................................................................................................... 893.2.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO).................................................. 903.2.5 Module Oscillator (MODOSC) ................................................................................... 903.2.6 Digitally Controlled Oscillator (DCO)............................................................................ 903.2.7 Operation From Low-Power Modes, Requested by Peripheral Modules .................................. 913.2.8 CS Module Fail-Safe Operation ................................................................................. 923.2.9 Synchronization of Clock Signals ............................................................................... 94

3.3 Module Oscillator (MODOSC) ............................................................................................ 943.3.1 MODOSC Operation .............................................................................................. 94

3.4 CS Registers ................................................................................................................ 953.4.1 CSCTL0 Register.................................................................................................. 963.4.2 CSCTL1 Register.................................................................................................. 963.4.3 CSCTL2 Register.................................................................................................. 973.4.4 CSCTL3 Register.................................................................................................. 983.4.5 CSCTL4 Register.................................................................................................. 993.4.6 CSCTL5 Register ................................................................................................ 1013.4.7 CSCTL6 Register ................................................................................................ 102

4 CPUX .............................................................................................................................. 1034.1 MSP430X CPU (CPUX) Introduction................................................................................... 1044.2 Interrupts ................................................................................................................... 1064.3 CPU Registers ............................................................................................................ 107

4.3.1 Program Counter (PC) .......................................................................................... 1074.3.2 Stack Pointer (SP) ............................................................................................... 107

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4.3.3 Status Register (SR) ............................................................................................ 1094.3.4 Constant Generator Registers (CG1 and CG2) ............................................................. 1104.3.5 General-Purpose Registers (R4 to R15)...................................................................... 111

4.4 Addressing Modes ........................................................................................................ 1134.4.1 Register Mode.................................................................................................... 1144.4.2 Indexed Mode .................................................................................................... 1154.4.3 Symbolic Mode................................................................................................... 1194.4.4 Absolute Mode ................................................................................................... 1244.4.5 Indirect Register Mode .......................................................................................... 1264.4.6 Indirect Autoincrement Mode................................................................................... 1274.4.7 Immediate Mode ................................................................................................. 128

4.5 MSP430 and MSP430X Instructions ................................................................................... 1304.5.1 MSP430 Instructions ............................................................................................ 1304.5.2 MSP430X Extended Instructions .............................................................................. 135

4.6 Instruction Set Description............................................................................................... 1474.6.1 Extended Instruction Binary Descriptions..................................................................... 1484.6.2 MSP430 Instructions ............................................................................................ 1504.6.3 Extended Instructions ........................................................................................... 2024.6.4 Address Instructions............................................................................................. 245

5 32-Bit Hardware Multiplier (MPY32) ..................................................................................... 2605.1 32-Bit Hardware Multiplier (MPY32) Introduction..................................................................... 2615.2 MPY32 Operation......................................................................................................... 263

5.2.1 Operand Registers............................................................................................... 2645.2.2 Result Registers ................................................................................................. 2655.2.3 Software Examples .............................................................................................. 2665.2.4 Fractional Numbers.............................................................................................. 2675.2.5 Putting It All Together ........................................................................................... 2705.2.6 Indirect Addressing of Result Registers ...................................................................... 2735.2.7 Using Interrupts .................................................................................................. 2735.2.8 Using DMA........................................................................................................ 274

5.3 MPY32 Registers ......................................................................................................... 2755.3.1 MPY32CTL0 Register ........................................................................................... 277

6 FRAM Controller (FRCTL) .................................................................................................. 2786.1 FRAM Introduction........................................................................................................ 2796.2 FRAM Organization....................................................................................................... 2796.3 FRCTL Module Operation ............................................................................................... 2796.4 Programming FRAM Memory Devices................................................................................. 280

6.4.1 Programming FRAM Memory Via JTAG or Spy-Bi-Wire ................................................... 2806.4.2 Programming FRAM Memory Via Bootstrap Loader (BSL) ................................................ 2806.4.3 Programming FRAM Memory Via Custom Solution......................................................... 280

6.5 Wait State Control ........................................................................................................ 2806.5.1 Wait State and Cache Hit....................................................................................... 281

6.6 FRAM ECC ................................................................................................................ 2816.7 FRAM Write Back ........................................................................................................ 2816.8 FRAM Power Control..................................................................................................... 2816.9 FRAM Cache .............................................................................................................. 2826.10 FRCTL Registers ......................................................................................................... 283

6.10.1 FRCTL0 Register ............................................................................................... 2846.10.2 GCCTL0 Register............................................................................................... 2856.10.3 GCCTL1 Register............................................................................................... 286

7 Memory Protection Unit (MPU) ........................................................................................... 2877.1 Memory Protection Unit (MPU) Introduction .......................................................................... 288

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7.2 MPU Segments ........................................................................................................... 2897.2.1 Main Memory Segments ........................................................................................ 2897.2.2 IP Encapsulation Segment ..................................................................................... 2907.2.3 Segment Border Setting ........................................................................................ 2917.2.4 IP Encapsulation Border Settings.............................................................................. 2927.2.5 Information Memory ............................................................................................. 293

7.3 MPU Access Management Settings.................................................................................... 2937.4 MPU Violations............................................................................................................ 294

7.4.1 Interrupt Vector Table and Reset Vector ..................................................................... 2947.4.2 Violation Handling ............................................................................................... 294

7.5 MPU Lock.................................................................................................................. 2947.6 MPU Registers ............................................................................................................ 295

7.6.1 MPUCTL0 Register .............................................................................................. 2967.6.2 MPUCTL1 Register .............................................................................................. 2977.6.3 MPUSEGB2 Register ........................................................................................... 2987.6.4 MPUSEGB1 Register ........................................................................................... 2997.6.5 MPUSAM Register............................................................................................... 3007.6.6 MPUIPC0 Register .............................................................................................. 3027.6.7 MPUIPSEGB2 Register ......................................................................................... 3037.6.8 MPUIPSEGB1 Register ......................................................................................... 304

8 RAM Controller (RAMCTL) ................................................................................................. 3058.1 RAM Controller (RAMCTL) Introduction ............................................................................... 3068.2 RAMCTL Operation....................................................................................................... 306

8.2.1 Considerations for Complete Power Down................................................................... 3068.3 RAMCTL Registers ....................................................................................................... 307

8.3.1 RCCTL0 Register (offset = 00h) [reset = 6900h] ............................................................ 3089 DMA Controller................................................................................................................. 309

9.1 Direct Memory Access (DMA) Introduction............................................................................ 3109.2 DMA Operation............................................................................................................ 312

9.2.1 DMA Addressing Modes ........................................................................................ 3129.2.2 DMA Transfer Modes............................................................................................ 3139.2.3 Initiating DMA Transfers ........................................................................................ 3199.2.4 Halting Executing Instructions for DMA Transfers........................................................... 3209.2.5 Stopping DMA Transfers........................................................................................ 3209.2.6 DMA Channel Priorities ......................................................................................... 3209.2.7 DMA Transfer Cycle Time ...................................................................................... 3219.2.8 Using DMA With System Interrupts ........................................................................... 3219.2.9 DMA Controller Interrupts....................................................................................... 3219.2.10 Using the eUSCI_B I2C Module With the DMA Controller................................................. 3229.2.11 Using ADC12 With the DMA Controller...................................................................... 323

9.3 DMA Registers ............................................................................................................ 3249.3.1 DMACTL0 Register .............................................................................................. 3269.3.2 DMACTL1 Register .............................................................................................. 3279.3.3 DMACTL2 Register .............................................................................................. 3289.3.4 DMACTL3 Register .............................................................................................. 3299.3.5 DMACTL4 Register .............................................................................................. 3309.3.6 DMAxCTL Register .............................................................................................. 3319.3.7 DMAxSA Register ............................................................................................... 3339.3.8 DMAxDA Register ............................................................................................... 3349.3.9 DMAxSZ Register................................................................................................ 3359.3.10 DMAIV Register................................................................................................. 336

10 Digital I/O......................................................................................................................... 33710.1 Digital I/O Introduction ................................................................................................... 338

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10.2 Digital I/O Operation...................................................................................................... 33910.2.1 Input Registers (PxIN).......................................................................................... 33910.2.2 Output Registers (PxOUT) .................................................................................... 33910.2.3 Direction Registers (PxDIR) ................................................................................... 33910.2.4 Pullup or Pulldown Resistor Enable Registers (PxREN) .................................................. 33910.2.5 Function Select Registers (PxSEL0, PxSEL1).............................................................. 34010.2.6 Port Interrupts ................................................................................................... 340

10.3 I/O Configuration .......................................................................................................... 34210.3.1 Configuration After Reset...................................................................................... 34210.3.2 Configuration of Unused Port Pins ........................................................................... 34310.3.3 Configuration for LPMx.5 Low-Power Modes ............................................................... 343

10.4 Digital I/O Registers ...................................................................................................... 34510.4.1 P1IV Register ................................................................................................... 35810.4.2 P2IV Register ................................................................................................... 35810.4.3 P3IV Register ................................................................................................... 35910.4.4 P4IV Register ................................................................................................... 35910.4.5 PxIN Register ................................................................................................... 36010.4.6 PxOUT Register ................................................................................................ 36010.4.7 PxDIR Register.................................................................................................. 36010.4.8 PxREN Register ................................................................................................ 36110.4.9 PxSEL0 Register................................................................................................ 36110.4.10 PxSEL1 Register .............................................................................................. 36110.4.11 PxSELC Register.............................................................................................. 36210.4.12 PxIES Register ................................................................................................ 36210.4.13 PxIE Register .................................................................................................. 36210.4.14 PxIFG Register ................................................................................................ 363

11 Capacitive Touch IO .......................................................................................................... 36411.1 Capacitive Touch IO Introduction ....................................................................................... 36511.2 Capacitive Touch IO Operation ......................................................................................... 36611.3 CapTouch Registers...................................................................................................... 367

11.3.1 CAPTIOxCTL Register (offset = 0Eh) [reset = 0000h]..................................................... 36812 AES256 Accelerator .......................................................................................................... 369

12.1 AES Accelerator Introduction............................................................................................ 37012.2 AES Accelerator Operation.............................................................................................. 371

12.2.1 Load the Key (128-Bit, 192-Bit, or 256-Bit Keylength)..................................................... 37212.2.2 Load the Data (128-Bit State) ................................................................................. 37212.2.3 Read the Data (128-Bit State) ................................................................................ 37312.2.4 Trigger an Encryption or Decryption ......................................................................... 37312.2.5 Encryption ....................................................................................................... 37412.2.6 Decryption ....................................................................................................... 37512.2.7 Decryption Key Generation.................................................................................... 37612.2.8 AES Key Buffer ................................................................................................. 37712.2.9 Using the AES Accelerator With Low-Power Modes....................................................... 37712.2.10 AES Accelerator Interrupts................................................................................... 37712.2.11 DMA Operation and Implementing Block Cipher Modes................................................. 377

12.3 AES Accelerator Registers .............................................................................................. 39012.3.1 AESACTL0 Register............................................................................................ 39112.3.2 AESACTL1 Register............................................................................................ 39312.3.3 AESASTAT Register ........................................................................................... 39412.3.4 AESAKEY Register............................................................................................. 39512.3.5 AESADIN Register ............................................................................................. 39612.3.6 AESADOUT Register .......................................................................................... 39712.3.7 AESAXDIN Register............................................................................................ 398

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12.3.8 AESAXIN Register.............................................................................................. 39913 CRC Module ..................................................................................................................... 400

13.1 Cyclic Redundancy Check (CRC) Module Introduction.............................................................. 40113.2 CRC Standard and Bit Order............................................................................................ 40113.3 CRC Checksum Generation............................................................................................. 402

13.3.1 CRC Implementation ........................................................................................... 40213.3.2 Assembler Examples........................................................................................... 403

13.4 CRC Registers ............................................................................................................ 40513.4.1 CRCDI Register................................................................................................. 40613.4.2 CRCDIRB Register ............................................................................................. 40613.4.3 CRCINIRES Register........................................................................................... 40713.4.4 CRCRESR Register ............................................................................................ 407

14 CRC32 Module.................................................................................................................. 40814.1 Cyclic Redundancy Check (CRC32) Module Introduction........................................................... 40914.2 CRC Checksum Generation............................................................................................. 409

14.2.1 CRC Standard and Bit Order.................................................................................. 41014.2.2 CRC Implementation ........................................................................................... 41014.2.3 Assembler Examples........................................................................................... 410

14.3 CRC32 Register Descriptions ........................................................................................... 41214.3.1 CRC32 Registers ............................................................................................... 412

15 Watchdog Timer (WDT_A).................................................................................................. 41915.1 WDT_A Introduction ...................................................................................................... 42015.2 WDT_A Operation ........................................................................................................ 422

15.2.1 Watchdog Timer Counter (WDTCNT)........................................................................ 42215.2.2 Watchdog Mode ................................................................................................ 42215.2.3 Interval Timer Mode ............................................................................................ 42215.2.4 Watchdog Timer Interrupts .................................................................................... 42215.2.5 Fail-Safe Features .............................................................................................. 42315.2.6 Operation in Low-Power Modes .............................................................................. 423

15.3 WDT_A Registers......................................................................................................... 42415.3.1 WDTCTL Register .............................................................................................. 425

16 Timer_A........................................................................................................................... 42616.1 Timer_A Introduction ..................................................................................................... 42716.2 Timer_A Operation ....................................................................................................... 429

16.2.1 16-Bit Timer Counter ........................................................................................... 42916.2.2 Starting the Timer............................................................................................... 42916.2.3 Timer Mode Control ............................................................................................ 43016.2.4 Capture/Compare Blocks ...................................................................................... 43316.2.5 Output Unit ...................................................................................................... 43516.2.6 Timer_A Interrupts.............................................................................................. 439

16.3 Timer_A Registers ........................................................................................................ 44116.3.1 TAxCTL Register ............................................................................................... 44216.3.2 TAxR Register................................................................................................... 44316.3.3 TAxCCTLn Register ............................................................................................ 44416.3.4 TAxCCRn Register ............................................................................................ 44616.3.5 TAxIV Register .................................................................................................. 44616.3.6 TAxEX0 Register ............................................................................................... 447

17 Timer_B........................................................................................................................... 44817.1 Timer_B Introduction ..................................................................................................... 449

17.1.1 Similarities and Differences From Timer_A ................................................................. 44917.2 Timer_B Operation ....................................................................................................... 451

17.2.1 16-Bit Timer Counter ........................................................................................... 451

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17.2.2 Starting the Timer............................................................................................... 45117.2.3 Timer Mode Control ............................................................................................ 45217.2.4 Capture/Compare Blocks ...................................................................................... 45517.2.5 Output Unit ...................................................................................................... 45817.2.6 Timer_B Interrupts.............................................................................................. 462

17.3 Timer_B Registers ........................................................................................................ 46417.3.1 TBxCTL Register ............................................................................................... 46517.3.2 TBxR Register................................................................................................... 46717.3.3 TBxCCTLn Register ............................................................................................ 46817.3.4 TBxCCRn Register ............................................................................................. 47017.3.5 TBxIV Register .................................................................................................. 47117.3.6 TBxEX0 Register ............................................................................................... 472

18 Real-Time Clock (RTC) Overview ........................................................................................ 47318.1 RTC Overview............................................................................................................. 473

19 Real-Time Clock B (RTC_B) ............................................................................................... 47419.0.1 Real-Time Clock Operation in LPM3.5 Low-Power Mode................................................. 481

19.1 RTC_B Registers ......................................................................................................... 48219.1.1 RTCCTL0 Register ............................................................................................. 48419.1.2 RTCCTL1 Register ............................................................................................. 48519.1.3 RTCCTL2 Register ............................................................................................. 48619.1.4 RTCCTL3 Register ............................................................................................. 48619.1.5 RTCSEC Register Hexadecimal Format .................................................................. 48719.1.6 RTCSEC Register BCD Format ............................................................................ 48719.1.7 RTCMIN Register Hexadecimal Format................................................................... 48819.1.8 RTCMIN Register BCD Format............................................................................. 48819.1.9 RTCHOUR Register Hexadecimal Format................................................................ 48919.1.10 RTCHOUR Register BCD Format ........................................................................ 48919.1.11 RTCDOW Register............................................................................................ 49019.1.12 RTCDAY Register Hexadecimal Format................................................................. 49019.1.13 RTCDAY Register BCD Format........................................................................... 49019.1.14 RTCMON Register Hexadecimal Format ................................................................ 49119.1.15 RTCMON Register BCD Format .......................................................................... 49119.1.16 RTCYEAR Register Hexadecimal Format ............................................................... 49219.1.17 RTCYEAR Register BCD Format......................................................................... 49219.1.18 RTCAMIN Register Hexadecimal Format ............................................................... 49319.1.19 RTCAMIN Register BCD Format ......................................................................... 49319.1.20 RTCAHOUR Register Hexadecimal Format ............................................................ 49419.1.21 RTCAHOUR Register BCD Format ...................................................................... 49419.1.22 RTCADOW Register .......................................................................................... 49519.1.23 RTCADAY Register Hexadecimal Format ............................................................... 49619.1.24 RTCADAY Register BCD Format......................................................................... 49619.1.25 RTCPS0CTL Register ........................................................................................ 49719.1.26 RTCPS1CTL Register ........................................................................................ 49819.1.27 RTCPS0 Register ............................................................................................. 49919.1.28 RTCPS1 Register ............................................................................................. 49919.1.29 RTCIV Register................................................................................................ 50019.1.30 BIN2BCD Register ............................................................................................ 50119.1.31 BCD2BIN Register ............................................................................................ 501

20 Real-Time Clock C (RTC_C) ............................................................................................... 50220.1 Real-Time Clock (RTC_C) Introduction................................................................................ 50320.2 RTC_C Operation......................................................................................................... 505

20.2.1 Calendar Mode.................................................................................................. 50520.2.2 Real-Time Clock and Prescale Dividers .................................................................... 505

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20.2.3 Real-Time Clock Alarm Function ............................................................................ 50520.2.4 Real-Time Clock Protection ................................................................................... 50620.2.5 Reading or Writing Real-Time Clock Registers ............................................................ 50720.2.6 Real-Time Clock Interrupts .................................................................................... 50720.2.7 Real-Time Clock Calibration for Crystal Offset Error....................................................... 50920.2.8 Real-Time Clock Compensation for Crystal Temperature Drift ........................................... 51020.2.9 Real-Time Clock Operation in LPM3.5 Low-Power Mode................................................. 512

20.3 RTC_C Operation - Device-Dependent Features .................................................................... 51320.3.1 Counter Mode ................................................................................................... 51320.3.2 Real-Time Clock Event/Tamper Detection With Time Stamp............................................. 516

20.4 RTC_C Registers ......................................................................................................... 51820.4.1 RTCCTL0_L Register .......................................................................................... 52120.4.2 RTCCTL0_H Register.......................................................................................... 52220.4.3 RTCCTL1 Register ............................................................................................. 52320.4.4 RTCCTL3 Register ............................................................................................. 52420.4.5 RTCOCAL Register ............................................................................................ 52420.4.6 RTCTCMP Register ............................................................................................ 52520.4.7 RTCNT1 Register............................................................................................... 52620.4.8 RTCNT2 Register............................................................................................... 52620.4.9 RTCNT3 Register............................................................................................... 52620.4.10 RTCNT4 Register ............................................................................................. 52620.4.11 RTCSEC Register Calendar Mode With Hexadecimal Format ....................................... 52720.4.12 RTCSEC Register Calendar Mode With BCD Format ................................................. 52720.4.13 RTCMIN Register Calendar Mode With Hexadecimal Format........................................ 52820.4.14 RTCMIN Register Calendar Mode With BCD Format.................................................. 52820.4.15 RTCHOUR Register Calendar Mode With Hexadecimal Format..................................... 52920.4.16 RTCHOUR Register Calendar Mode With BCD Format............................................... 52920.4.17 RTCDOW Register Calendar Mode ...................................................................... 53020.4.18 RTCDAY Register Calendar Mode With Hexadecimal Format ....................................... 53020.4.19 RTCDAY Register Calendar Mode With BCD Format ................................................. 53020.4.20 RTCMON Register Calendar Mode With Hexadecimal Format ...................................... 53120.4.21 RTCMON Register Calendar Mode With BCD Format ................................................ 53120.4.22 RTCYEAR Register Calendar Mode With Hexadecimal Format ..................................... 53220.4.23 RTCYEAR Register Calendar Mode With BCD Format ............................................... 53220.4.24 RTCAMIN Register Calendar Mode With Hexadecimal Format ...................................... 53320.4.25 RTCAMIN Register Calendar Mode With BCD Format ................................................ 53320.4.26 RTCAHOUR Register......................................................................................... 53420.4.27 RTCAHOUR Register Calendar Mode With BCD Format ............................................. 53420.4.28 RTCADOW Register Calendar Mode .................................................................... 53520.4.29 RTCADAY Register Calendar Mode With Hexadecimal Format ..................................... 53620.4.30 RTCADAY Register Calendar Mode With BCD Format ............................................... 53620.4.31 RTCPS0CTL Register ........................................................................................ 53720.4.32 RTCPS1CTL Register ........................................................................................ 53820.4.33 RTCPS0 Register ............................................................................................. 54020.4.34 RTCPS1 Register ............................................................................................. 54020.4.35 RTCIV Register................................................................................................ 54120.4.36 BIN2BCD Register ............................................................................................ 54220.4.37 BCD2BIN Register ............................................................................................ 54220.4.38 RTCSECBAKx Register Hexadecimal Format .......................................................... 54320.4.39 RTCSECBAKx Register BCD Format .................................................................... 54320.4.40 RTCMINBAKx Register Hexadecimal Format........................................................... 54420.4.41 RTCMINBAKx Register BCD Format .................................................................... 54420.4.42 RTCHOURBAKx Register Hexadecimal Format........................................................ 545

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20.4.43 RTCHOURBAKx Register BCD Format ................................................................. 54520.4.44 RTCDAYBAKx Register Hexadecimal Format .......................................................... 54620.4.45 RTCDAYBAKx Register BCD Format .................................................................... 54620.4.46 RTCMONBAKx Register Hexadecimal Format ......................................................... 54720.4.47 RTCMONBAKx Register BCD Format ................................................................... 54720.4.48 RTCYEARBAKx Register Hexadecimal Format ........................................................ 54820.4.49 RTCYEARBAKx Register BCD Format .................................................................. 54820.4.50 RTCTCCTL0 Register ........................................................................................ 54920.4.51 RTCTCCTL1 Register ........................................................................................ 54920.4.52 RTCCAPxCTL Register ...................................................................................... 550

21 Enhanced Universal Serial Communication Interface (eUSCI) UART Mode............................ 55121.1 Enhanced Universal Serial Communication Interface A (eUSCI_A) Overview .................................. 55221.2 eUSCI_A Introduction UART Mode .................................................................................. 55221.3 eUSCI_A Operation UART Mode .................................................................................... 554

21.3.1 eUSCI_A Initialization and Reset ............................................................................. 55421.3.2 Character Format ............................................................................................... 55421.3.3 Asynchronous Communication Format ...................................................................... 55421.3.4 Automatic Baud-Rate Detection .............................................................................. 55721.3.5 IrDA Encoding and Decoding ................................................................................. 55821.3.6 Automatic Error Detection ..................................................................................... 55921.3.7 eUSCI_A Receive Enable ..................................................................................... 56021.3.8 eUSCI_A Transmit Enable .................................................................................... 56021.3.9 UART Baud-Rate Generation ................................................................................. 56121.3.10 Setting a Baud Rate .......................................................................................... 56321.3.11 Transmit Bit Timing - Error calculation ..................................................................... 56421.3.12 Receive Bit Timing Error Calculation ..................................................................... 56421.3.13 Typical Baud Rates and Errors.............................................................................. 56521.3.14 Using the eUSCI_A Module in UART Mode With Low-Power Modes ................................. 56721.3.15 eUSCI_A Interrupts in UART Mode......................................................................... 56721.3.16 DMA Operation ................................................................................................ 569

21.4 eUSCI_A UART Registers............................................................................................... 57021.4.1 UCAxCTLW0 Register ......................................................................................... 57121.4.2 UCAxCTLW1 Register ......................................................................................... 57221.4.3 UCAxBRW Register ............................................................................................ 57321.4.4 UCAxMCTLW Register ........................................................................................ 57321.4.5 UCAxSTATW Register ......................................................................................... 57421.4.6 UCAxRXBUF Register ......................................................................................... 57521.4.7 UCAxTXBUF Register ......................................................................................... 57521.4.8 UCAxABCTL Register.......................................................................................... 57621.4.9 UCAxIRCTL Register........................................................................................... 57721.4.10 UCAxIE Register .............................................................................................. 57821.4.11 UCAxIFG Register ............................................................................................ 57921.4.12 UCAxIV Register .............................................................................................. 580

22 Enhanced Universal Serial Communication Interface (eUSCI) SPI Mode ............................... 58122.1 Enhanced Universal Serial Communication Interfaces (eUSCI_A, eUSCI_B) Overview ....................... 58222.2 eUSCI Introduction SPI Mode ........................................................................................ 58222.3 eUSCI Operation SPI Mode........................................................................................... 584

22.3.1 eUSCI Initialization and Reset ................................................................................ 58422.3.2 Character Format ............................................................................................... 58522.3.3 Master Mode .................................................................................................... 58522.3.4 Slave Mode ...................................................................................................... 58622.3.5 SPI Enable....................................................................................................... 58722.3.6 Serial Clock Control ............................................................................................ 587

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22.3.7 Using the SPI Mode With Low-Power Modes............................................................... 58822.3.8 eUSCI Interrupts in SPI Mode ................................................................................ 588

22.4 eUSCI_A SPI Registers.................................................................................................. 59022.4.1 UCAxCTLW0 Register ......................................................................................... 59122.4.2 UCAxBRW Register ............................................................................................ 59222.4.3 UCAxSTATW Register ......................................................................................... 59322.4.4 UCAxRXBUF Register ......................................................................................... 59422.4.5 UCAxTXBUF Register ......................................................................................... 59522.4.6 UCAxIE Register................................................................................................ 59622.4.7 UCAxIFG Register.............................................................................................. 59722.4.8 UCAxIV Register................................................................................................ 598

22.5 eUSCI_B SPI Registers.................................................................................................. 59922.5.1 UCBxCTLW0 Register ......................................................................................... 60022.5.2 UCBxBRW Register ............................................................................................ 60122.5.3 UCBxSTATW Register ......................................................................................... 60122.5.4 UCBxRXBUF Register ......................................................................................... 60222.5.5 UCBxTXBUF Register ......................................................................................... 60222.5.6 UCBxIE Register ............................................................................................... 60322.5.7 UCBxIFG Register.............................................................................................. 60322.5.8 UCBxIV Register................................................................................................ 604

23 Enhanced Universal Serial Communication Interface (eUSCI) I2C Mode ................................ 60523.1 Enhanced Universal Serial Communication Interface B (eUSCI_B) Overview ................................... 60623.2 eUSCI_B Introduction I2C Mode ...................................................................................... 60623.3 eUSCI_B Operation I2C Mode ........................................................................................ 607

23.3.1 eUSCI_B Initialization and Reset ............................................................................. 60823.3.2 I2C Serial Data .................................................................................................. 60823.3.3 I2C Addressing Modes ......................................................................................... 60923.3.4 I2C Quick Setup ................................................................................................. 61023.3.5 I2C Module Operating Modes ................................................................................. 61123.3.6 Glitch Filtering ................................................................................................... 62123.3.7 I2C Clock Generation and Synchronization.................................................................. 62123.3.8 Byte Counter .................................................................................................... 62223.3.9 Multiple Slave Addresses...................................................................................... 62323.3.10 Using the eUSCI_B Module in I2C Mode With Low-Power Modes ..................................... 62323.3.11 eUSCI_B Interrupts in I2C Mode ............................................................................ 624

23.4 eUSCI_B I2C Registers .................................................................................................. 62723.4.1 UCBxCTLW0 Register ......................................................................................... 62823.4.2 UCBxCTLW1 Register ......................................................................................... 63023.4.3 UCBxBRW Register ............................................................................................ 63223.4.4 UCBxSTATW.................................................................................................... 63223.4.5 UCBxTBCNT Register ......................................................................................... 63323.4.6 UCBxRXBUF Register ......................................................................................... 63423.4.7 UCBxTXBUF .................................................................................................... 63423.4.8 UCBxI2COA0 Register......................................................................................... 63523.4.9 UCBxI2COA1 Register......................................................................................... 63623.4.10 UCBxI2COA2 Register ....................................................................................... 63623.4.11 UCBxI2COA3 Register ....................................................................................... 63723.4.12 UCBxADDRX Register ....................................................................................... 63723.4.13 UCBxADDMASK Register ................................................................................... 63823.4.14 UCBxI2CSA Register ......................................................................................... 63823.4.15 UCBxIE Register .............................................................................................. 63923.4.16 UCBxIFG Register ............................................................................................ 64123.4.17 UCBxIV Register .............................................................................................. 643

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24 REF_A ............................................................................................................................. 64424.1 REF_A Introduction....................................................................................................... 64524.2 Principle of Operation .................................................................................................... 646

24.2.1 Low-Power Operation .......................................................................................... 64624.2.2 Reference System Requests.................................................................................. 646

24.3 REF_A Registers ......................................................................................................... 64824.3.1 REFCTL0 Register (offset = 00h) [reset = 0000h] ......................................................... 649

25 ADC12_B ......................................................................................................................... 65125.1 ADC12_B Introduction ................................................................................................... 65225.2 ADC12_B Operation...................................................................................................... 654

25.2.1 12-Bit ADC Core ................................................................................................ 65425.2.2 ADC12_B Inputs and Multiplexer ............................................................................. 65425.2.3 Voltage References ............................................................................................ 65525.2.4 Auto Power Down .............................................................................................. 65525.2.5 Sample Frequency Mode Selection .......................................................................... 65625.2.6 Sample and Conversion Timing .............................................................................. 65625.2.7 Conversion Memory ............................................................................................ 65925.2.8 ADC12_B Conversion Modes ................................................................................. 66025.2.9 Window Comparator............................................................................................ 66525.2.10 Using the Integrated Temperature Sensor................................................................. 66625.2.11 ADC12_B Grounding and Noise Considerations ......................................................... 66725.2.12 ADC12_B Calibration ......................................................................................... 66825.2.13 ADC12_B Interrupts .......................................................................................... 668

25.3 ADC12_B Registers ...................................................................................................... 67025.3.1 ADC12CTL0 Register (offset = 00h) [reset = 0000h] ...................................................... 67625.3.2 ADC12CTL1 Register (offset = 02h) [reset = 0000h] ...................................................... 67825.3.3 ADC12CTL2 Register (offset = 04h) [reset = 0020h] ...................................................... 68025.3.4 ADC12CTL3 Register (offset = 06h) [reset = 0000h] ...................................................... 68125.3.5 ADC12MEMx Register (x = 0 to 31) ......................................................................... 68225.3.6 ADC12MCTLx Register (x = 0 to 31) ........................................................................ 68325.3.7 ADC12HI Register (offset = 0Ah) [reset = 0FFFh] ......................................................... 68525.3.8 ADC12LO Register (offset = 08h) [reset = 0000h] ......................................................... 68525.3.9 ADC12IER0 Register (offset = 12h) [reset = 0000h]....................................................... 68625.3.10 ADC12IER1 Register (offset = 14h) [reset = 0000h] ..................................................... 68825.3.11 ADC12IER2 Register (offset = 16h) [reset = 0000h] ..................................................... 69025.3.12 ADC12IFGR0 Register (offset = 0Ch) [reset = 0000h] ................................................... 69125.3.13 ADC12IFGR1 Register (offset = 0Eh) [reset = 0000h] ................................................... 69325.3.14 ADC12IFGR2 Register (offset = 10h) [reset = 0000h] ................................................... 69525.3.15 ADC12IV Register (offset = 18h) [reset = 0000h]......................................................... 696

26 Comparator E (COMP_E) Module ........................................................................................ 69826.1 COMP_E Introduction .................................................................................................... 69926.2 COMP_E Operation ...................................................................................................... 700

26.2.1 Comparator ...................................................................................................... 70026.2.2 Analog Input Switches ......................................................................................... 70026.2.3 Port Logic ........................................................................................................ 70026.2.4 Input Short Switch .............................................................................................. 70026.2.5 Output Filter ..................................................................................................... 70126.2.6 Reference Voltage Generator ................................................................................. 70226.2.7 Port Disable Register (CEPD) ................................................................................ 70326.2.8 Comparator_E Interrupts ...................................................................................... 70326.2.9 Comparator_E Used to Measure Resistive Elements ..................................................... 703

26.3 COMP_E Registers....................................................................................................... 70626.3.1 CECTL0 Register (offset = 00h) [reset = 0000h] ........................................................... 707

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26.3.2 CECTL1 Register (offset = 02h) [reset = 0000h] ........................................................... 70826.3.3 CECTL2 Register (offset = 04h) [reset = 0000h] ........................................................... 71026.3.4 CECTL3 Register (offset = 06h) [reset = 0000h] ........................................................... 71126.3.5 CEINT Register (offset = 0Ch) [reset = 0000h] ............................................................. 71326.3.6 CEIV Register (offset = 0Eh) [reset = 0000h] ............................................................... 714

27 LCD_C Controller.............................................................................................................. 71527.1 LCD_C Introduction....................................................................................................... 71627.2 LCD_C Operation......................................................................................................... 718

27.2.1 LCD Memory .................................................................................................... 71827.2.2 LCD Timing Generation........................................................................................ 71927.2.3 Blanking the LCD ............................................................................................... 72027.2.4 LCD Blinking..................................................................................................... 72027.2.5 LCD Voltage And Bias Generation ........................................................................... 72127.2.6 LCD Outputs..................................................................................................... 72427.2.7 LCD Interrupts................................................................................................... 72527.2.8 Static Mode ...................................................................................................... 72727.2.9 2-Mux Mode ..................................................................................................... 72827.2.10 3-Mux Mode.................................................................................................... 72927.2.11 4-Mux Mode.................................................................................................... 73027.2.12 6-Mux Mode.................................................................................................... 73127.2.13 8-Mux Mode.................................................................................................... 732

27.3 LCD_C Registers ......................................................................................................... 73427.3.1 LCDCCTL0 Register ........................................................................................... 73927.3.2 LCDCCTL1 Register ........................................................................................... 74127.3.3 LCDCBLKCTL Register ........................................................................................ 74227.3.4 LCDCMEMCTL Register....................................................................................... 74327.3.5 LCDCVCTL Register ........................................................................................... 74427.3.6 LCDCPCTL0 Register.......................................................................................... 74627.3.7 LCDCPCTL1 Register.......................................................................................... 74627.3.8 LCDCPCTL2 Register.......................................................................................... 74727.3.9 LCDCPCTL3 Register.......................................................................................... 74727.3.10 LCDCCPCTL Register........................................................................................ 74827.3.11 LCDCIV Register .............................................................................................. 748

28 Extended Scan Interface (ESI) ............................................................................................ 74928.1 Extended Scan Interface Introduction.................................................................................. 75028.2 Extended Scan Interface Operation .................................................................................... 751

28.2.1 ESI Analog Front End .......................................................................................... 75128.2.2 Extended Scan Interface Timing State Machine............................................................ 75828.2.3 Extended Scan Interface Pre-Processing and State Storage............................................. 76328.2.4 TimerA Output Stage........................................................................................... 76428.2.5 Extended Scan Interface Processing State Machine ...................................................... 76528.2.6 Extended Scan Interface Debug Register ................................................................... 76928.2.7 Extended Scan Interface Interrupts .......................................................................... 76928.2.8 Overview of Extended Scan Interface Applications ........................................................ 770

28.3 ESI Registers.............................................................................................................. 77728.3.1 ESIDEBUG1 Register .......................................................................................... 77828.3.2 ESIDEBUG2 Register .......................................................................................... 77828.3.3 ESIDEBUG3 Register .......................................................................................... 77828.3.4 ESIDEBUG4 Register .......................................................................................... 77928.3.5 ESIDEBUG5 Register .......................................................................................... 77928.3.6 ESICNT0 Register .............................................................................................. 78028.3.7 ESICNT1 Register .............................................................................................. 78028.3.8 ESICNT2 Register .............................................................................................. 781

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28.3.9 ESICNT3 Register .............................................................................................. 78128.3.10 ESIIV Register ................................................................................................. 78228.3.11 ESIINT1 Register.............................................................................................. 78328.3.12 ESIINT2 Register.............................................................................................. 78528.3.13 ESIAFE Register .............................................................................................. 78728.3.14 ESIPPU Register .............................................................................................. 78928.3.15 ESITSM Register.............................................................................................. 79028.3.16 ESIPSM Register.............................................................................................. 79228.3.17 ESIOSC Register.............................................................................................. 79328.3.18 ESICTL Register .............................................................................................. 79428.3.19 ESITHR1 Register ............................................................................................ 79628.3.20 ESITHR2 Register ............................................................................................ 79628.3.21 ESIDAC1Rx Register (x = 0 to 7) ........................................................................... 79728.3.22 ESIDAC2Rx Register (x = 0 to 7) ........................................................................... 79728.3.23 ESITSMx Register (x = 0 to 31) ............................................................................. 79828.3.24 Extended Scan Interface Processing State Machine Table Entry (ESI Memory)..................... 800

29 Embedded Emulation Module (EEM) ................................................................................... 80129.1 Embedded Emulation Module (EEM) Introduction ................................................................... 80229.2 EEM Building Blocks ..................................................................................................... 804

29.2.1 Triggers .......................................................................................................... 80429.2.2 Trigger Sequencer.............................................................................................. 80429.2.3 State Storage (Internal Trace Buffer) ........................................................................ 80429.2.4 Cycle Counter ................................................................................................... 80429.2.5 EnergyTrace++ Technology ................................................................................ 80529.2.6 Clock Control .................................................................................................... 80529.2.7 Debug Modes ................................................................................................... 805

29.3 EEM Configurations ...................................................................................................... 806Revision History ........................................................................................................................ 807

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List of Figures1-1. BOR, POR, and PUC Reset Circuit...................................................................................... 391-2. Interrupt Priority............................................................................................................. 401-3. Interrupt Processing........................................................................................................ 421-4. Return From Interrupt...................................................................................................... 431-5. Operation Modes ........................................................................................................... 471-6. Devices Descriptor Table.................................................................................................. 581-7. SFRIE1 Register ........................................................................................................... 641-8. SFRIFG1 Register.......................................................................................................... 651-9. SFRRPCR Register ........................................................................................................ 671-10. SYSCTL Register .......................................................................................................... 691-11. SYSJMBC Register ........................................................................................................ 701-12. SYSJMBI0 Register ........................................................................................................ 711-13. SYSJMBI1 Register ........................................................................................................ 711-14. SYSJMBO0 Register....................................................................................................... 721-15. SYSJMBO1 Register....................................................................................................... 721-16. SYSUNIV Register ......................................................................................................... 731-17. SYSSNIV Register ......................................................................................................... 731-18. SYSRSTIV Register........................................................................................................ 742-1. PMM Block Diagram ....................................................................................................... 762-2. Voltage Failure and Resulting PMM Actions ........................................................................... 772-3. PMM Action at Device Power-Up ........................................................................................ 782-4. PMMCTL0 Register ........................................................................................................ 812-5. PMMCTL1 Register ........................................................................................................ 822-6. PMMIFG Register .......................................................................................................... 832-7. PM5CTL0 Register......................................................................................................... 843-1. Clock System Block Diagram ............................................................................................. 873-2. Module Request Clock System........................................................................................... 913-3. Oscillator Fault Logic ...................................................................................................... 933-4. Switch MCLK from DCOCLK to LFXTCLK.............................................................................. 943-5. CSCTL0 Register........................................................................................................... 963-6. CSCTL1 Register........................................................................................................... 963-7. CSCTL2 Register........................................................................................................... 973-8. CSCTL3 Register........................................................................................................... 983-9. CSCTL4 Register........................................................................................................... 993-10. CSCTL5 Register ......................................................................................................... 1013-11. CSCTL6 Register ......................................................................................................... 1024-1. MSP430X CPU Block Diagram ......................................................................................... 1054-2. PC Storage on the Stack for Interrupts ................................................................................ 1064-3. Program Counter.......................................................................................................... 1074-4. PC Storage on the Stack for CALLA ................................................................................... 1074-5. Stack Pointer .............................................................................................................. 1084-6. Stack Usage ............................................................................................................... 1084-7. PUSHX.A Format on the Stack ......................................................................................... 1084-8. PUSH SP, POP SP Sequence.......................................................................................... 1084-9. SR Bits ..................................................................................................................... 1094-10. Register-Byte and Byte-Register Operation ........................................................................... 1114-11. Register-Word Operation ................................................................................................ 111

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4-12. Word-Register Operation ................................................................................................ 1124-13. Register Address-Word Operation ................................................................................... 1124-14. Address-Word Register Operation ................................................................................... 1134-15. Indexed Mode in Lower 64KB........................................................................................... 1154-16. Indexed Mode in Upper Memory ....................................................................................... 1164-17. Overflow and Underflow for Indexed Mode ........................................................................... 1174-18. Example for Indexed Mode .............................................................................................. 1184-19. Symbolic Mode Running in Lower 64KB .............................................................................. 1204-20. Symbolic Mode Running in Upper Memory ........................................................................... 1214-21. Overflow and Underflow for Symbolic Mode .......................................................................... 1224-22. MSP430 Double-Operand Instruction Format......................................................................... 1304-23. M