MPSoCResearch Group‐ University of Ferrara ‐

Davide BertozziPrincipal Investigator

The GroupEstablished in 2004 completely from scratch, with the mission to kick‐off a research and teaching program in architecture of digital integrated systems at University of Ferrara

Simone Medardoni,now in Arrow Electronics

Daniele Ludovici, now in Intel Mobile Communications

Alberto Ghiribaldi, now in ArzAdv

Marketing & Web Software

Alessandro Strano, now in Intel Mobile Communications Francisco Gilabert, now in 

Intel Mobile Communications

Gabriele Miorandi3° year PhD student

Marco BalboniPostDoc

Mahdi Tala1° year PhD student

Hervé Fankem Tatenguem,now in Sacher Lasertechnik GmbH

Luca Ramini, now in STMicroelectronics

Marta Ortin Obon, nowPostDoc at University of Zaragoza

11 PhD students – 128 scientific contributions – 5 BPAs – 100% employ. rate

Interdisciplinary Collaborations inside UNIFE

Michele Favalli:Reliability, testing

Maddalena Nonato:Synthesis flowsfor emergingtechnologies

Piero Olivo:Solid state disks

Gaetano Bellanca:Silicon photonics

Tortonesi Mauro: Programming models

Davide Bertozzi: Head of MPSoC Research Group

Funding• Fund raising: 1.061M euros. On average 88k euros/year

56%

17%

1%

26% EU projects

Italian

NoE

Local Uni

80% of the PhD students paid through fund raising

Key expertiseKey expertise on communication architectures (past, present and future).

The interconnect‐centric nature of modern embedded systemsenabled a quick expansion of the expertise to:

Many‐core Architectures 

“Dynamic”HW Architectures

EDA beyond its electronic roots

Solid State Drives

Networks‐on‐chipPhysical SynthesisPhysical Synthesis

RTL (Timing) Constraints

Place-and-RouteOptimization

Place-and-RouteOptimization

MacromodulesFixed netlists

Fault‐tolerance, Testing

Asynchronous NoC Nanophotonic NoC

Microserver Architecture

Virtual and FPGA prototyping

Emerging Interconnects: the Common EDA Challenge

NEED FOR A TRUE SOFT MACRO WITHMAINSTREAM EDA TOOLS, 

BEYOND CURRENT HARD‐MACRO APPROACHES

Technology‐independent design and timing constraints spec.

RTL simulation and logic synthesis

Max_performance synthesis, but also relaxation

Support for hierarchical design

Support for different aspect ratios

Qualify relative timing constraints

Support for link pipelining

RTL specification and parameterizability

Integration with front‐end prototype tools

Pseudo‐synchronous specification of timing constraints

Asynchronous NoC Design

SW

SW

SW

SW

CORE

NI

CORE

NIVO

LTAGE AN

D FREQ

UEN

CYISLAN

D

VOLTAG

E AN

D FRE

QUEN

CYISLA

ND

CORE

NI

CORE

NIMESOCH

RONOUS NoC

MESOCHRONOUSSYNCHRONIZERS

DC‐FIFOs

VOLTAG

E AN

D FRE

QUEN

CYISLA

ND

VOLTAG

E AND FREQ

UEN

CYISLAN

D

ChallengesCORE

NI

SW

SW

CORE

NI

CORE

NI

SW

SW

CORE

NI

VOLTAG

E AND FREQ

UEN

CYISLAN

D

VOLTAG

E AN

D FRE

QUEN

CYISLA

ND

VOLTAG

E AN

D FRE

QUEN

CYISLA

ND

VOLTAG

E AND FREQ

UEN

CYISLAN

D

ASYN

CHRO

NOUS NoC

ATS/STA

CLOCKLESSHANDSHAKING

The synchronization dilemma in GALS ESs: striving to preserve a clock, or going clockless?

A collaboration with Columbia University

Emerging Interconnects: the Common EDA Challenge

NEED FOR A TRUE SOFT MACRO WITHMAINSTREAM EDA TOOLS, 

BEYOND CURRENT HARD‐MACRO APPROACHES

Technology‐independent design and timing constraints spec.

RTL simulation and logic synthesis

Max_performance synthesis, but also relaxation

Support for hierarchical design

Support for different aspect ratios

Qualify relative timing constraints

Support for link pipelining

RTL specification and parameterizability

Integration with front‐end prototype tools

Pseudo‐synchronous specification of timing constraints

Asynchronous NoC Design

Can we infer application‐specific asynchronousnetworks‐on‐chip, where most of the NoC vendorstoday have their big markets?

Challenges

A collaboration with Columbia University

BEHAVIOURAL MODELING

COMMUNICATIONPROTOCOL 

PLATFORM INTEGRATION

TOPOLOGY SYNTHESIS

PLACE&ROUTE

PHYSICAL DESIGN

TAPE OUT

Emerging Interconnects: the Common EDA Challenge

Optical NoC DesignChallenges

Emerging technologies often carry different logic primitives, for which 

contemporary logic synthesis techniques are not suitable. New synthesis methods as technology

enablers. I have a great device; it works!

Cool, but I can’t do design with it!

AUTOMATIC SYNTHESIS TOOLFLOWS, VERTICALLY INTEGRATED WITH CURRENT PDKS, WILL BE KEY TO 

STREAMLINE SILICON PHOTONIC COMPONENT INTEGRATION INTO FUTURE IC DESIGNS

A collaboration with University of Zaragoza and TU Munich

BEHAVIOURAL MODELING

COMMUNICATIONPROTOCOL 

PLATFORM INTEGRATION

TOPOLOGY SYNTHESIS

PLACE&ROUTE

PHYSICAL DESIGN

TAPE OUT

I1 T1

T2

T3

T4I2

To ArbitratedOptical NoC (s)

To Electronic NoC (s)

Emerging Interconnects: the Common EDA Challenge

Optical NoC Design AUTOMATIC SYNTHESIS TOOLFLOWS, VERTICALLY INTEGRATED WITH CURRENT PDKS, WILL BE KEY TO 

STREAMLINE SILICON PHOTONIC COMPONENT INTEGRATION INTO FUTURE IC DESIGNS

Challenges

Emerging technologies often carry different logic primitives, for which 

contemporary logic synthesis techniques are not suitable. New synthesis methods as technology

enablers.

Conflict‐free ONoC

Architectural challenges: technology composition,Technology hybridization, customization.

A collaboration with University of Zaragoza and TU Munich

Host (multi‐core heterog.)

processor

General Purpose Programmable Accelerator

Hardware accelerators High‐Speed I/O

DMA engine

Top‐level NoC

Cache‐coherent interconnect

DRAM memory controller

2nd‐level NoC

Graphics FPGA‐likefabric

Intermediate Fabric

2nd‐level NoC

Heterogeneous Parallel Computer Architecture

Our mission: Hardware support for mixed‐criticality multi‐programmed workloads!

Our Vision

HYPERVISOR

RESOURCE MANAGER

Virtualization as a means of simplifying programming

Master the reconfiguration hooks exposed by a “dynamic” hardware platform” for energy‐efficient platform‐management

Dynamic repartitioning

A

B

B C

ADZzZ

Workload‐adaptive powermanagement while meeting application

requirements

Programmers should be allowed to specify hardware platform‐agnosticexecution requirements (perf. targets, quality‐of‐service, reliability, or security)    Programmers do not need to adapt their applications to the host system 

hardware, but just to the abstracted environment provided inside each VM. App. requirements

Platform state

Hardware support for fine‐grained adaptive resource sharing

A collaboration with University of Bologna and Universitat Politecnica de Valencia

EXPLOITING MANY-CORE PARALLELISM

0

0,5

1

1,5

2

Thread

‐Level Parallelism

on 

Dual‐Core Processor for 

Smartpho

nes

Android Apple

Issue: software parallelism does not keep up with Hardware parallelism!

Challenge: how can the large parallelism of many-core accelerators be really exploited?

Host Processor General-Purpose Programmable Accelerator

Serial Processing of acceleration requests (TOO SLOW!). Time interleaving (or TDM) of the whole accelerator

(CONTEXT SWITCHING EXPENSIVE!).

SPACE PARTITIONING or (Space-DivisionMultiplexing, SDM) of accelerator resources for concurrent processing.

Design methods for SDM-enabled many-core architectures Hardware support for partitioning and isolation, driven by predictability and/or security requirementsù Enable fine-grained adaptive partitioning

Our mission:

Dynamic Architecture

Partition scheduling.

Partition reshaping.

Avoid faulty links or switches.

Power-off unused or overheated regions.

Set up or tear down of reserved paths(hard QoS)

Effective Resource Sharing implies

The usage requirements will soon make many-core systems highly dynamic environments!

The dynamism of this scenario introduces new issues and challenges for the designers, bringing the runtime resource management concern to the forefront!

Efficient orchestration of lots of small jobs in parallel on the microserver nodes is key

Building Another Level of Hierarchy• Microservers are a new class of systems targeting lightweight, scale out workloads  by 

means of simpler and slower processors compared to high‐end enterprise solutions.• Recently, interest in a broader adoption in more computationally‐demanding contexts like 

big‐data, HPC computing, and other data‐center‐oriented computations. 

Christmann Informationstechnik+medien RECS 3.0 prototype (up to 72 ARM‐based microserver nodes in 

1U form factor)

High‐radixSwitch

An optical interconnect fabric is an appealing approach with cross‐layer disruptive implications for future microservers.

Where to place the phase transition between shared memory and MPI depends on the spatialextension of «local domains».

A collaboration with Scuola Superiore Sant’Anna and Università di Siena

Engineering Education for k‐12 studentsToday, there is an insufficient and declining students’ motivation to take scientific

careers. As a result, there are less engineers in EE than needed.

Working with technology is not enough! Working with technology is not enough!

Research is an active knowledgeconstruction process where the subject is engaged wit all of hisknowledge, skills and attitude

WE HAVE TO OPEN THE BLACK BOX! HOW?By bringing «scientific research» within reach of k‐12 students,

as an authentic educative experienceLead students to design (overly small) parts of the complex electronic devicesthat are personally meaningful and 

pervasive in their lives.

A collaboration with the Dept. of Philosophy, Education and Psychology at University of Verona

Research at school – step I• The university goes to the 

high‐school to help studentsopen the «black‐box»

Goals: Instil a sense of wonder at the complexity of modern electronic systems and nanoscale

technologies, so to break the consumerist approach of students to their use. Anticipate the university learning method to high‐school students. Allow students to make a more conscious choice of academic course of studies.

A collaboration with the Dept. of Philosophy, Education and Psychology at University of Verona

WELCOME TO THENOC CITY

Research at school – step II• High‐school students can already rely on formal learningcapabilities…what about k‐12 students?

Is it possible to teach advanced scientificconcepts to young students?

Challenge: contextualization and exemplification of formal and abstractengineering concepts to the children’s

stage of cognitive development.

Use the narrative approach!Children use narratives to explain the complexity of their experience of the 

world (Engel, 1999).The narrative approach to science 

education is already well established in other disciplines (Fuchs2007, Corni2010))

All you need is: An analogy! Figurative structure Story plot Narrative 

development

A collaboration with the Dept. of Philosophy, Education and Psychology at University of Verona

International collaborationsColumbia University(AsynchronousNoCs)

University of Thrace(Partitioning and Isolation)

TU Munich(Place&route for optical NoCs)

PolitechnicUniversity of Valencia (partitioning and reconfiguration)

University of Zaragoza (Optical NoCarchitectures)

ETH Zurich(programmingmodels)

Main Industrial contacts

Thank you