mosis report report - university of...

MOSIS REPORT

Report:

1. Report 1

2. Report 2

3. Report 3

Report 1 The most important step in designing a four-bit counter is determining what type of flip-

flop to use. Almost any type of flip-flop can be configured for counter functionality. The only

difference in using various flip-flops will be additional features that can be implemented with

certain configurations and the connections necessary for satisfactory operation. A D flip-flop

was chosen for this counter design since it is essentially the simplest type of flip-flop that can

be implemented. A D flip-flop has a minimal amount of transistors and the connections

required to form a counter are very simple once one flip-flop is created. The output of a D flip-

flop follows the input of the logic function when the clock transitions regardless of the output’s

present state. In this case, the flip-flop will be falling edge-triggered. The truth table for such a

flip-flop can be seen below.

Figure 1: D Flip-flop Truth Table

D Qn CLK Qn+1

0 d Falling 01 d Falling 1

The schematic that was used to implement the D flip-flop utilizes four NAND gates and

three inverters. The aspect ratios of each of the PMOS transistors in the configuration were

chosen to be twice the size of the NMOS transistors. This allows for a more similar mode of

operation for both types of devices. In addition, the aspect ratios in the inverter at the output

were chosen to be larger so more current can be driven serving as a form of buffer. The final

schematic implemented and tested for the D flip-flop can be seen in the figure below.

Figure 2: D Flip-flop Schematic

The layout for this given configuration was then implemented in layout. Once it

was DRC clean, it was extracted with parasitic capacitances and LVS tests were conducted.

After the schematic and extracted circuits matched, the flip-flop was tested and its functionality

was confirmed. A symbol was then created to be used in the counter design. During this

process, screenshots were taken and can be observed in Figures 3-5.

Figure 3: D Flip-flop Layout

Figure 4: D Flip-flop Extracted View

Figure 5: D Flip-flop Symbol

Now that the D flip-flop has been created, the remaining counter design is easily

designed. To create a counter from D flip-flops, a clock signal is routed to clock the flip-flop for

the LSB (least significant bit). The inverted output is then wired to the input of this flip-flop.

This essentially creates a toggle function which is what is needed for the LSB flip-flop. The

output of the LSB flip-flop is then routed to the clock input of the next stage. The inverted

output of this flip-flop is also connected back to its own input. This will create the next bit of

the counter, and the process is replicated for each of the other bits. Using the output of the

previous stage as a clock and attaching the inverted output to the input of the flip-flop is all that

is needed to create the up-counter logic. Figure 6 shows the final schematic of flip-flops and

the necessary connections to form the flip flop.

Figure 6: Counter Schematic using D Flip-flops

Since the layout of the D flip-flop was previously created, it can be used in the layout in

the same way the symbol was used in the schematic. In the following figure, the additional

connections needed are shown with the D flip-flop shown as a symbol. The subsequent figure

shows the final layout used with all parts visible.

Figure 7: Symbolic Counter Layout View

Figure 8: Final Counter Layout View

Just as in the layout of the D flip-flop, once the counter layout design was DRC clean, it

was extracted and an LVS check was performed. As the following figures show, the layout and

schematic were perfectly matched.

Figure 9: Extracted Counter View

Figure 10: LVS Output File

Now that everything matches in the extracted and schematic, the requirements of the

project needed to be verified. The functionality of the counter can be confirmed by looking at

the simulation results from the schematic and extracted files shown below. Figures showing

the delay and rise and fall times are also included below. The clock that was used had a rise/fall

time of 1 ps, a 50% duty cycle, a period of 100 ns, a low of 0 V, and a high of 5 V. The delay was

calculated by finding 50% of the input signal and determining the time difference between that

point and a point at 50% of the LSB output. The 50% point for each of the plots should have

been about 2.5 V since the input clock voltage was 0-5 V. To measure the rise time of the

counter, the time difference between low (zero) and 70% of the output was taken. The value of

70% should have been around 3.5 V. Similarly, the fall time was taken as the time difference

between high (5 V) and 30%. The value for 30% should have been around 1.5 V. A table

containing all the delays, rise times, and fall times will be included near the end of the report

after all the measurements have been presented.

Figure 11: Counter Simulation from Extracted View

Figure 12: Counter Delay Simulation from Extracted View

Figure 13: Counter Rise Time Simulation from Extracted View

Figure 14: Counter Fall Time Simulation from Extracted View

Figure 15: Counter Simulation from Schematic View

Figure 16: Counter Delay Simulation from Schematic View

Figure 17: Counter Rise Time Simulation from Schematic View

Figure 18: Counter Fall Time Simulation from Schematic View

The above results came out as expected. The functionality of the circuit implemented is

indeed up-counter logic. The project also required that various values of additional load

capacitance to be added to the output to see how this would affect the delay, rise time, and fall

time. Screen shots for each of these simulations can be seen in the Appendix. These values

were recorded and plotted versus the load capacitance. As can easily be seen below, as the

load capacitance is increased, all three of these parameters should also increase. As expected,

the relationship of these variations came out to be extremely linear.

Figure 19: Time Parameters versus Increasing Load Capacitance Plot

Overall, this project was very educational and all required portions of the project were

fulfilled. A counter was successfully implemented using a four D flip-flop configuration. The

counter behaved as expected when adding additional load capacitance. There was more

inherent delay, and the rise and fall times were longer. Upon completion of the project, a

symbol was produced for the entire counter design so that it may be used for any future

projects in which a counter may be needed. This symbol can be seen in Figure 20 below. The

design was also put on a pad frame so that it can be shipped off to be fabricated. Once it

comes back the counter can then be tested and used. The counter on the pad frame can be

seen in the final figure below.

0.00E+00

1.00E-09

2.00E-09

3.00E-09

4.00E-09

5.00E-09

6.00E-09

7.00E-09

8.00E-09

9.00E-09

0 1E-12 2E-12 3E-12 4E-12 5E-12 6E-12

Tim

e (s

)

Load Capacitance (F)

Delay/Rise Time/Fall Time vs Load Capacitance

Rise Time

Fall Time

Delay

Figure 20: Symbol Created for Final Counter Design

Figure 21: Counter Circuit on Pad Frame

APPENDIX

Counter Operation with 1-5pf Load Capacitance (Respectively)

Counter Delay with 1-5pf Load Capacitance (Respectively)

Counter Rise Time with 1-5pf Load Capacitance (Respectively)

Counter Fall Time with 1-5pf Load Capacitance (Respectively)

Report 2 Project Overview

This project is aimed at designing a 4-bit counter, for the AMI-0.6micron process, using the Cadence design tool. D flip-flops have been used to design a 4-bit binary ripple down-counter, and circuit simulations were performed using the Cadence Virtuoso Spectre simulator. The counter’s outputs were loaded with various capacitances (0 pF to 5 pF) to observe the effect of load on the rise and fall times, and overall delay times of the counter.

Introduction

A binary counter is a digital circuit that follows sequential logic. There are two types of counters: ripple (asynchronous) counters and synchronous counters. This project report is limited to the discussion of a 4-bit ripple down-counter. In ripple counters, only the first flip-flop is triggered using a clock pulse (CLK). Each consecutive flip-flop is triggered by the output transition that occurs in the previous flip-flop. In this project, four positive-edge triggered D flip-flops are connected as shown in Figure 1 to form a 4-bit binary ripple counter.

Schematic

Figures 2 and 3 show the transistor level and gate level schematics, respectively, of a positive-edge triggered D flip-flop. The W/L ratios for the transistors were chosen based on the ‘DFFPOSX1’ standard library cell of the OSU_AMI06 process, and the W/L of the pmos and nmos devices are 6/0.6 and 3/0.6 respectively. A symbol for the D flip-flop was created (Figure 4) for ease of use while designing the 4-bit counter (Figure 1). The number of transistors used to create a D flip-flop is lesser compared to other flip-flops. Hence, this flip-flop was chosen for this project as the routing in the final counter design would be simpler and the entire counter would occupy lesser area on chip.

Figure 1: Schematic of 4-bit asynchronous down-counter using positive-edge triggered D flip-flops

Figure 2: Transistor level schematic of a positive-edge triggered D flip-flop

Figure 3: Gate level schematic of a positive-edge triggered D flip-flop

Figure 4: Symbol for positive-edge triggered D flip-flop in Figure 3 The transient analysis for the down-counter was simulated for 4 µs using the Cadence Virtuoso Spectre simulator using a CLK frequency of 10 MHz and supply voltage of 5 V. The Spectre simulation results are shown in Figure 5. Q0 is the LSB and Q3 is the MSB. Since a positive-edge triggered flip-flop has been used, it can be seen that all the flip-flops are triggered at the rising edge of the corresponding input, and the counter counts from decimal 2n-1 (here, n = 4) to decimal 0.

Layout

The layout of the positive-edge triggered D flip-flop is shown in Figure 6. The ‘DFFPOSX1’ standard cell from the OSU_AMI06 library was used as a reference while designing the layout of the flip-flop shown in Figure 6. The layout of the counter is shown in Figure 7. The four D flip-flops are arranged in such a way that the last two flip-flops share a common ‘gnd’ supply with the first two flip flops (a pair of flip-flops are stacked over the other). This minimizes routing, and thereby, a delay caused by such routing, and also makes the circuit more compact. The power supply (‘vdd’) and input signal (CLK) are on the extreme left side of the design, and the output can be routed out from the extreme right of the circuit. Metal 1 and metal 2 have been used for interconnects between the flip-flops for

the counter. After verifying that the design conforms to DRC, the layout was extracted with parasitic caps. The extracted view is shown in Figure 8. Before performing post-layout simulations, LVS was performed on the extracted view to verify that the layout matched the schematic. The output of the LVS check is shown in Figure 9.

Figure 5: Pre-Spectre transient analysis simulation results for the 4-bit counter

Figure 6: Layout of positive-edge triggered D flip-flop

Figure 7: Layout of 4-bit ripple down-counter

Figure 8: Extracted view of the counter

Figure 9: LVS output

Transient analysis was performed on the extracted layout for 5 µs, with vdd = 5 V and a clock frequency of 10 MHz. The results of the simulation are show in Figure 10 (which closely matches the simulations for the schematic, shown in Figure 5).

Loading Effects

To study the effects of loading on the counter, capacitive loads ranging from 0 pF to 5 pF were added to each of the four output nodes of the counter (Figure 11). The rise, fall and delay times have been plotted for the MSB in order to observe the effect of all the loads in entirety on the final output. The rise time is calculated as the time taken to reach from 30% to 70% of the supply, the fall time is calculated as the time taken to reach from 70% to 30% of the supply, and the delay time is the time taken to reach from 0% to 50% of the input signal.

The plot of rise, fall and delay times for varying loads is shown in Figure 12. The individual plots showing the rise, fall and delay times for each load are given in Appendix A. It can be seen that the delay is almost proportional to the load at the output.

Figure 10: Post-Spectre transient analysis simulation results for the 4-bit counter

Figure 11: Schematic of counter with capacitive loads

Figure 12: Effect of capacitive loads on delay, rise and fall times

Conclusion

The 4-bit asynchronous down-counter was designed using positive-edge triggered D flip-flops, and pre- and post-spectre simulations were performed. The effect of loading capacitors at the output of the counter was also analyzed using the Cadence Virtuoso Spectre simulator. The final circuit is laid on a padframe, shown in Figure 12. It can be seen that the circuit actually occupies a very small area on the

chip! The input signals (CLK and vdd) have been routed on the extreme left of the chip, while the outputs and gnd signals have been routed via the extreme right.

Although it takes a considerable amount of time to learn how to use the Cadence tool, this project provides a good learning platform for circuit design and simulation, and gives a better understanding of the theory that was taught in class. Also, creating just a simple MSI circuit layout makes one appreciate the amount of effort and patience that goes in to the design and analysis of LSI circuits!

Reference

“Digital Logic and Computer Design”, Morris Mano, Prentice Hall Inc., 1979

Figure 13: 4-bit asynchronous down-counter circuit on padframe

APPENDIX A

Transient Analysis Simulation Results of Load vs Delay

Appendix A 1: Transient analysis at no load

Appendix A 2: Transient analysis at 1p F load



APPENDIX B

Netlist

// Generated for: spectre

// Generated on: Apr 22 08:51:47 2009

// Design library name: ECE533

// Design cell name: counter_4bit

// Design view name: extracted

simulator lang=spectre

global 0 vdd! gnd!

include "/usr/local/ncsu/ncsu-cdk-1.5.1/models/spectre/standalone/ami06P.m"

include "/usr/local/ncsu/ncsu-cdk-1.5.1/models/spectre/standalone/ami06N.m"

// Library name: ECE533

// Cell name: counter_4bit

// View name: extracted

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\+79 (_22 Q0 _52 vdd!) ami06P w=6e-06 l=6e-07 as=3.6e-12 ad=5.4e-12 \




\+77 (_52 _18 vdd! vdd!) ami06P w=6e-06 l=6e-07 as=9.9e-12 ad=3.6e-12 \




\+73 (_18 Q1 vdd! vdd!) ami06P w=6e-06 l=6e-07 as=9e-12 ad=9e-12 ps=9e-06 \

pd=9e-06 m=1 region=sat



























\+53 (_10 CLK _44 vdd!) ami06P w=6e-06 l=6e-07 as=3.6e-12 ad=5.4e-12 \








\+93 (vdd! Q1 _58 vdd!) ami06P w=3e-06 l=6e-07 as=1.35e-12 ad=9.45e-12 \












\+65 (_50 CLK _14 vdd!) ami06P w=3e-06 l=6e-07 as=6.75e-12 ad=1.35e-12 \




\+95 (Q1 _26 vdd! vdd!) ami06P w=1.2e-05 l=6e-07 as=9.45e-12 ad=1.8e-11 \




\+75 (vdd! Q0 _20 vdd!) ami06P w=1.2e-05 l=6e-07 as=1.8e-11 ad=9.9e-12 \








\+49 (vdd! CLK _8 vdd!) ami06P w=1.2e-05 l=6e-07 as=1.8e-11 ad=9.9e-12 \




\+45 (0 Q1 _42 0) ami06N w=3e-06 l=6e-07 as=1.35e-12 ad=4.95e-12 ps=9e-07 \

pd=3.3e-06 m=1 region=sat



\+43 (_42 _20 _26 0) ami06N w=3e-06 l=6e-07 as=3.6e-12 ad=1.35e-12 \


\+42 (_43 _21 _27 0) ami06N w=3e-06 l=6e-07 as=3.6e-12 ad=1.35e-12 \


\+41 (_26 Q0 _40 0) ami06N w=3e-06 l=6e-07 as=1.35e-12 ad=3.6e-12 ps=9e-07 \




\+39 (_40 _24 0 0) ami06N w=3e-06 l=6e-07 as=4.5e-12 ad=1.35e-12 ps=6e-06 \




\+37 (_24 _22 0 0) ami06N w=3e-06 l=6e-07 as=3.15e-12 ad=4.5e-12 \


\+36 (_25 _23 0 0) ami06N w=3e-06 l=6e-07 as=3.15e-12 ad=4.5e-12 \


\+35 (0 _24 _38 0) ami06N w=3e-06 l=6e-07 as=1.35e-12 ad=3.15e-12 ps=9e-07 \




\+33 (_38 Q0 _22 0) ami06N w=3e-06 l=6e-07 as=3.15e-12 ad=1.35e-12 \




\+31 (_23 _21 _37 0) ami06N w=3e-06 l=6e-07 as=1.35e-12 ad=3.15e-12 \


\+30 (_22 _20 _36 0) ami06N w=3e-06 l=6e-07 as=1.35e-12 ad=3.15e-12 \


\+29 (_36 _18 0 0) ami06N w=3e-06 l=6e-07 as=4.95e-12 ad=1.35e-12 \


\+28 (_37 _19 0 0) ami06N w=3e-06 l=6e-07 as=4.95e-12 ad=1.35e-12 \


\+25 (_18 Q1 0 0) ami06N w=3e-06 l=6e-07 as=4.5e-12 ad=4.5e-12 ps=6e-06 \












\+17 (_34 _8 _14 0) ami06N w=3e-06 l=6e-07 as=3.6e-12 ad=1.35e-12 \


\+16 (_35 _9 _15 0) ami06N w=3e-06 l=6e-07 as=3.6e-12 ad=1.35e-12 \


\+15 (_14 CLK _32 0) ami06N w=3e-06 l=6e-07 as=1.35e-12 ad=3.6e-12 \








\+11 (_12 _10 0 0) ami06N w=3e-06 l=6e-07 as=3.15e-12 ad=4.5e-12 \


\+10 (_13 _11 0 0) ami06N w=3e-06 l=6e-07 as=3.15e-12 ad=4.5e-12 \






\+7 (_30 CLK _10 0) ami06N w=3e-06 l=6e-07 as=3.15e-12 ad=1.35e-12 \




\+5 (_10 _8 _28 0) ami06N w=3e-06 l=6e-07 as=1.35e-12 ad=3.15e-12 ps=9e-07 \


\+4 (_11 _9 _29 0) ami06N w=3e-06 l=6e-07 as=1.35e-12 ad=3.15e-12 ps=9e-07 \


\+3 (_28 _16 0 0) ami06N w=3e-06 l=6e-07 as=4.95e-12 ad=1.35e-12 \


\+2 (_29 _17 0 0) ami06N w=3e-06 l=6e-07 as=4.95e-12 ad=1.35e-12 \


\+47 (Q1 _26 0 0) ami06N w=6e-06 l=6e-07 as=4.95e-12 ad=9e-12 ps=3.3e-06 \




\+27 (0 Q0 _20 0) ami06N w=6e-06 l=6e-07 as=9e-12 ad=4.95e-12 ps=9e-06 \








\+1 (0 CLK _8 0) ami06N w=6e-06 l=6e-07 as=9e-12 ad=4.95e-12 ps=9e-06 \




//Source

V2 (CLK 0) vsource type=pulse dc=0 val0=0 val1=5 period=200.0n rise=5n \

fall=5n width=100.0n

V0 (vdd! 0) vsource type=dc dc=5

V3 (gnd! 0) vsource type=dc dc=0

//Simulator Options

simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \

tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \

digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \

sensfile="../psf/sens.output" checklimitdest=psf

tran tran stop=2u errpreset=moderate write="spectre.ic" \

writefinal="spectre.fc" annotate=status maxiters=5

finalTimeOP info what=oppoint where=rawfile

modelParameter info what=models where=rawfile

element info what=inst where=rawfile

outputParameter info what=output where=rawfile

designParamVals info what=parameters where=rawfile

primitives info what=primitives where=rawfile

subckts info what=subckts where=rawfile

saveOptions options save=allpub

Report 3

4-Bit Counter

Shanthan Mudhasani, ECE 533, University of Tennessee, Knoxville

Abstract—This paper presents a report on the design of a 4-bit Up Counter using J-K flip-

flop that has a clocked input with Reset. Performing simulations of various output parameters including rise time, fall time, highlights the performance of the designed counter in Cadence.

INTRODUCTION: The project aims to design a 4-bit counter using a Flip Flop. The design is done using cadence and AMI C5N 0.6 µm Technology library. A JK-Flip Flop was used to design the counter.

DESIGN JUSTIFICATION A. Counter Design Justification

• A 4-bit has 16 states counting from 0 to 15.This means that to design a 4-bit counter we need 4 Flip Flops.

• The counter also has a reset pin that enables it to enter an all-zero state i.e. the output of the counter is '0' if the reset is '1' irrespective of the clock and the current state of the flip flops.

• The counter also has CLA (carry look ahead) out pin that stores the carry. The CLA pin can be used to modify the design. For example the counter can be upgraded to a 8-bit counter by adding an other 4-bit adder to the CLA output.

• The outputs of the counter are named F0, F1, F2, and F3. These outputs also represent current state of the flip-flops.

B. Choice of Flip-Flop • The counter designed has 4 JK-Flip Flops. The JK-Flip Flop triggers at every

negative going edge of the clock signal. • A latch is a level-sensitive device. The major problem with latch-sensitive devices

is that during the same level of the clock signal, a race around condition might occur thereby making the device prone to glitches. This is avoided using the edge-sensitive J-K flip-flop.

• Also, the rising/falling edge has to be very sharp. Hence a 1 ns delay is specified for the clock signal transition from one state to the other.

• JK-Flip Flop is versatile. A reset can be easily implemented using the set-reset mode of the JK Flip-Flop. And a D or a T Flip Flop can be easily implemented using a JK-Flip Flop.

• The aspect ratio (W/L) of PMOS and NMOS transistors is taken to be (6µ/600n) and (3µ/600n) respectively. The width of the PMOS transistor has been

approximately be set to 6µm, for the same gate lengths, to account for the slow hole mobility compared to the electron mobility.

J-K FLIP-FLOP DESIGN A J-K flip-flop in the Master-slave configuration was used to implement the 4-bit up counter. As seen from the schematic of the J-K flip-flop in fig.1, two 3-input NAND gates, six 2-input NAND gates and two inverters in a feedback loop. A change of state may occur when the flip-flop senses a negative edge of the clock signal. Also, a reset pin is incorporated by the inclusion of an inverter, AND and OR gate. The reset pin operates on active high logic, i.e. the output Q is forced to ‘0’ irrespective of the input levels at J and K. Table 1 shows the truth table of the J-K flip-flop with Reset. The schematic was laid out using Composer Schematic

Fig.1

and is as shown in fig. 2. It can be observed that the individual gates have been turned in order for the routing to be more convenient and also to make the layout more compact.

J K Qn+1 O O Qn 0 1 0 1 0 1 1 1 Q'n

Table 1

Fig. 3

4-BIT UP COUNTER DESIGN:

Fig. 3 shows the block diagram implementation of the counter. Four J-K flip-flops are connected in cascade and the outputs of each of the flip-flop forms the counter bits. The least significant bit (LSB) of the counter is the output of the first J-K flip-flop while the last flip-flop output forms the most significant bit (MSB). The inputs of the J-K flip-flop are tied together to form a T flip-flop. The output of the last JK FF is connected to an AND gate to produce the CLA (carry-look ahead) output bit. This pin can be used to cascade the counter to increase the number of states that can be counted by the counter. Fig.4 shows the symbol for the designed counter.

Fig.4

Table 2 below shows the states that can be counted by the counter. It is seen that the counter is able to count the states only when the reset pin is held low.

Counter States

Reset

R CLA F3 F2 F1 F0

Count

0 0 0 0 0 0 0

0 0 0 0 0 1 1

0 0 0 0 1 0 2

0 0 0 0 1 1 3

0 0 0 1 0 0 4

0 0 0 1 0 1 5

0 0 0 1 1 0 6

0 0 0 1 1 1 7

0 0 1 0 0 0 8

0 0 1 0 0 1 9

0 0 1 0 1 0 10

0 0 1 0 1 1 11

0 0 1 1 0 0 12

0 0 1 1 0 1 13

0 0 1 1 1 0 14

0 0 1 1 1 1 15

1 1 0 0 0 0 0

Table 2. Counter Truth Table

Fig. 5 shows the Pre-layout simulation of the counter. . It is observed that the LSB of the counter F0 alternates between 1 and 0 at every falling edge of the clock cycle, and this transition is propagated through to the MSB F3 of the counter. Fig. 6 shows the layout of the counter. Fig. 7 shows the extracted layout, which denotes the various capacitances between the various nodes of the circuit. Fig. 8 shows the Layout vs. Schematic (LVS) matching performed on the counter circuit. The ‘si.out’ file actually gives an account of all the nets, instances and other vital information regarding the extracted layout. It matches each of these essential parameters in both, the schematic and extracted layout to finally conclude that the

netlists match. Fig. 9 show the post-layout simulation of the counter applying the same input as that with the pre-layout simulation schematic. It is observed that the outputs match closely.

Fig 5

A certain degree of non-linearity is observed in the post-layout simulation, which can be attributed to the fact that the extracted layout takes into account all the various capacitances between the circuit nodes.

Fig. 6

Fig 7

Fig 8

Fig 9

PERFORMANCE PARAMETERS:

The performance of the designed counter is then tested by measuring the rise and fall times of the various output bits of the counter with zero load capacitance. Table 3 shows a qualitative comparison of the rise and fall times of these bits.

Output bits

Rise time

(ns)

Fall time

(ns)

F0 2.8 8.2

F1 2.8 6.4

F2 2.7 8.4

F3 2.6 8.7 Table 3. Rise and Fall time data

The rise time for each bit is less than the fall time for that bit. It means the discharging RC constant is grater than that of the charging one. The rise and fall times are calculated between 10% to 90 % of the output voltage level.

Another critical performance measurement parameter is the propagation delay at each individual bit of the counter. The propagation delay was measured as the time difference in attaining the 50% of the maximum signal level between the clock cycle and each output bit. The propagation delay varies greatly by changes in the capacitive load at the output of the counter. Thus the delay was measured for different values of load capacitances as seen from table 4. The delay times for ‘1’ to ‘0’ transitions are greater for each bit at every load than those for ‘0’ to ‘1’ transitions. Also a plot of the Delay vs. Load capacitance shows that the delay is linearly proportional to the increase in load capacitance.

Table 4 Propagation Delay for various output bits at different capacitive loads

Fig 10 Delay vs. Load capacitance

VI. PAD FRAME

Fig. 11 shows the connection of the counter to the pad frame layout. The input pins clk and R, the output pins F3, F2, F1, F0 and CLA along with the power supply connections VDD and ground are connected to individual pins on the pad frame. The connections to the pad frame need to be routed carefully so that the metal1 and metal2 layers do not cross each other at

points where a connection is not required. The pad frame adds a significant amount of load capacitance to the designed counter thereby increasing the rise and fall time of the circuit considerably.

Fig 11

APPLICATIONS: There are tremendous applications of a counter in the digital consumer electronics market. A counter can play a vital role in several circuits ranging from a simple display to complex microcontroller circuits. Some of the apparent applications of a counter are:

• Frequency divider in phase-locked loops • Frequency synthesizers • Signal generation and processing circuits • Microcontrollers and digital memories • In digital clock and timing circuits

CONCLUSION: The design of a 4-bit Counter has allowed us to implement the various digital VLSI concepts learnt in the course to put to practical use and experience a very powerful VLSI modeling tool in the form of Cadence. It is not only useful for laying out the actual circuit schematic that we have built but also allows us to understand the various capacitances affecting the circuit when laid out on a chip by means of showing them in the extracted layout. Also, by performing

simulations in Cadence, it is possible to understand the effect of the varying the transistor sizes to obtain the desired output parameters. It is also useful to get know-how of the various design rules learnt and how they should be avoided to ensure a good working design with minimum capacitances and occupying the minimum chip area.

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