1

Introduction toCMOS VLSI

Design

MOSFETs Lecture 3:Real World Effects

Peter KoggeUniversity of Notre Dame

Fall 2015,2018

Based on material fromProf. Jay Brockman, Joseph Nahas: University of Notre Dame

Prof. David Harris, Harvey Mudd Collegehttp://www.cmosvlsi.com/coursematerials.html

CMOS VLSI DesignMOSFETs-C Slide 2

Outline Lecture A

IEEE Notation and IV curves

MOS Gate

Water Model

nMOS Ideal Long Channel I-V Model

Supplementary Material – More Careful Computation

Lecture B Reading the I-V Curves

Sample Technologies

Load Lines and an NMOS Inverter

A CMOS Inverter

Lecture C DC Transfer Curves for an Inverter

Ideal vs Real

Real-World Effects

2

CMOS VLSI Design

Summary: Long Channel Model

MOSFETs-C Slide 3

0, Vgs < Vt Cutoff

β(VGT – Vds/2 )*Vds, Vgs > Vt and Vds < Vdsat Linear

βVGT2 / 2, Vds > Vdsat Saturation

Ids =

Where:• Cox = εox / tox

• β = (ox*/tox)*(W/L) = Cox**W/L• VGT = Vgs – Vt

• Vdsat = VGT

William Shockley 1st order transistor models1952 A Unipolar Field Effect Transistor

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, ox = 3.9

polysilicongate

CMOS VLSI Design

DC Transfer Characteristics

3

CMOS VLSI Design

Static Inverter DC Characteristics

“Perfect” digital circuits have I/O = 0V or Vdd

What if Vin between 0 and Vdd? What is Vout?

Assume βs same for N and P (P is wider)

Approach: Overlay IV curves as before

For each VGS = Vin, follow P and N curves until they intersect

Record the Ids and Vds

MOSFETs-C Slide 5

VDD

A Y

GND

Vin Vout

0

500

1000

1500

2000

2500

0 1 2 3 4 5 6

Id (uA)

Vds NMOS (Volts)

Inverter

CMOS VLSI Design

From The Book (Fig. 2.26)

MOSFETs-C Slide 6

Region Input P N Output

A 0 < Vin < Vtn Saturated Cutoff Vdd

B Vtn < Vin < Vdd/2 Saturated Linear >Vdd/2

C Vin ~ Vdd/2 Linear Linear Drops sharply

D Vdd/2 < Vin < Vdd-|Vtp| Linear Saturated <Vdd/2

E Vin > Vdd - |Vtp| Cutoff Saturated 0

VDD

A Y

GND

Vin Vout

4

CMOS VLSI Design

Let’s Do It

MOSFETs-C Slide 7

0

500

1000

1500

2000

2500

0 1 2 3 4 5 6

Id (uA)

Vds NMOS (Volts)

Inverter

54.543.532.521.510.50

Vin Ids Vds

0 0 5

0.5 0 5

1 0 5

1.5 80 4.8

2 200 4.6

2.5 400 2.5

3 200 0.5

3.5 80 0.2

4.0 0 0

4.5 0 0

5.0 0 0

0.05.0

4.5

4.0

3.5

3.0

2.52.01.5

0.5

2.0

3.0

1.5

2.5

3.5

1.0

CMOS VLSI Design

Graphing This

MOSFETs-C Slide 8

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0 1 2 3 4 5

Vout (V)

Vin (V)

0

50

100

150

200

250

300

350

400

450

0 1 2 3 4 5

Vout (V)

Vin (V)

Region Input P N Output

A 0 < Vin < Vtn Linear Cutoff Vdd

B Vtn < Vin < Vdd/2 Linear Saturated >Vdd/2

C Vin ~ Vdd/2 Saturated Saturated Drops sharply

D Vdd/2 < Vin < Vdd-|Vtp| Saturated Linear <Vdd/2

E Vin > Vdd - |Vtp| Cutoff Linear 0

A B C D E

Ids

5

CMOS VLSI Design

What If βs Not Same? (Fig. 2.28)

MOSFETs-C Slide 9

CMOS VLSI Design

Noise Margin

MOSFETs-C Slide 10

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0 1 2 3 4 5

Vout (V)

Vin (V) VIHVIL

VOH

VOL

VIH = min high input voltageVIL = max low input voltageVOH = min high output voltageVOL = max low input voltageNML = VIL – VOL

NMH = VOH - VIH

6

CMOS VLSI Design

Pass Transistor Drops (Fig. 2.31)

MOSFETs-C Slide 11

CMOS VLSI Design

Ideal vs Real

7

CMOS VLSI DesignMOSFETs-C Slide 13

Ideal nMOS I-V Plot

180 nm TSMC process

Ideal Models = 155(W/L) A/V2

Vt = 0.4 V

VDD = 1.8 V Ids (A)

Vds0 0.3 0.6 0.9 1.2 1.5 1.8

100

200

300

400

Vgs = 0.6

Vgs = 0.9

Vgs = 1.2

Vgs = 1.5

Vgs = 1.8

0

CMOS VLSI DesignMOSFETs-C Slide 14

Ideal vs Real

180 nm TSMC process

BSIM 3v3 SPICE models

What differs?

Vds

0 0.3 0.6 0.9 1.2 1.5

Vgs = 1.8

Ids (A)

0

50

100

150

200

250

Vgs = 1.5

Vgs = 1.2

Vgs = 0.9

Vgs = 0.6

Ids (A)

Vds0 0.3 0.6 0.9 1.2 1.5 1.8

100

200

300

400

Vgs = 0.6

Vgs = 0.9

Vgs = 1.2

Vgs = 1.5

Vgs = 1.8

0

Ideal 180 nm nmos Real Device (Spice Model)

8

CMOS VLSI DesignMOSFETs-C Slide 15

What’s Different?

Vds

0 0.3 0.6 0.9 1.2 1.5

Vgs = 1.8

Ids (A)

0

50

100

150

200

250

Vgs = 1.5

Vgs = 1.2

Vgs = 0.9

Vgs = 0.6

Ids (A)

Vds0 0.3 0.6 0.9 1.2 1.5 1.8

100

200

300

400

Vgs = 0.6

Vgs = 0.9

Vgs = 1.2

Vgs = 1.5

Vgs = 1.8

0

Ideal 180 nm nmos Real Device (Spice Model)

Less ON current

No square law

Current increases in saturation

CMOS VLSI Design

Lets Vary L and W With Constant W/L

MOSFETs-C Slide 16

W/L = 13.9

9

CMOS VLSI DesignMOSFETs-C Slide 17

W/L = 13.9

CMOS VLSI DesignMOSFETs-C Slide 18

W/L = 13.9

10

CMOS VLSI DesignMOSFETs-C Slide 19

W/L = 13.9

CMOS VLSI DesignMOSFETs-C Slide 20

W/L = 13.9

11

CMOS VLSI DesignMOSFETs-C Slide 21

W/L = 13.9

CMOS VLSI DesignMOSFETs-C Slide 22

W/L = 13.9

12

CMOS VLSI DesignMOSFETs-C Slide 23

W/L = 13.9

CMOS VLSI Design

Real World Effects

13

CMOS VLSI Design

Modifications to Model

Velocity Saturation

Channel Length Modulation

The Body Effect

MOSFETs-C Slide 25

CMOS VLSI DesignMOSFETs-C Slide 26

Velocity Saturation

We assumed carrier velocity is proportional to E-field v = Elat = Vds/L

At high fields, this ceases to be true Carriers scatter off atoms

Velocity reaches vsat at some Elat = Esat

• Electrons: 6-10 x 106 cm/s

• Holes: 4-8 x 106 cm/s

Better model

Esat00

slope =

Elat

2Esat3Esat

sat

sat / 2lat

sat satlat

sat

μμ

1

Ev v E

EE

Slide 37

toxL

e-source drain

Elat

Velocity SaturatedProportional

When Elat is small,denominator ~ 1and v ~ μElat

When Elat is large

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CMOS VLSI DesignMOSFETs-C Slide 27

Vel Sat I-V Effects

Ideal transistor ON current increases with VDD2

Velocity-saturated ON current increases with only VDD

Result: lower currents than ideal model

Real transistors are partially velocity saturated

Approximate with -power law model Ids VDD

1 < < 2 determined empirically

2

2

ox 2 2gs t

ds gs t

V VWI C V V

L

ox maxds gs tI C W V V v d

d

CMOS VLSI DesignMOSFETs-C Slide 28

-Power Model

Ids (A)

Vds0 0.3 0.6 0.9 1.2 1.5 1.8

100

200

300

400

Vgs = 0.6

Vgs = 0.9

Vgs = 1.2

Vgs = 1.5

Vgs = 1.8

0

-lawSimulated

Shockley

0 cutoff

linear

saturation

gs t

dsds dsat ds dsat

dsat

dsat ds dsat

V V

VI I V V

V

I V V

/ 2

2dsat c gs t

dsat v gs t

I P V V

V P V V

d

Velocity Saturationcompresses current

characteristics.

15

CMOS VLSI DesignMOSFETs-C Slide 29

Channel Length Modulation Reverse-biased p-n junctions form a depletion region

Region between n and p with no carriers

Width of depletion Ld region grows with reverse bias

Leff = L – Ld

Shorter Leff gives more current Ids increases with Vds

Even in saturation

n+

p

GateSource Drain

bulk Si

n+

VDDGND VDD

GND

LLeff

Depletion RegionWidth: Ld

Leff = “Effective Length”Typically less than Lphysical

CMOS VLSI DesignMOSFETs-C Slide 30

Chan Length Mod I-V

= channel length modulation coefficient not feature size

Empirically fit to I-V characteristics

Compute as “slope” of curve in saturation = ∆I/∆V

21

2ds gs t dsI V V V d

Vds

0 0.3 0.6 0.9 1.2 1.5

Vgs = 1.8

Ids (A)

0

50

100

150

200

250

Vgs = 1.5

Vgs = 1.2

Vgs = 0.9

Vgs = 0.6

Channel Length Modulationincreases drain current

in saturation.

∆I∆V

16

CMOS VLSI DesignMOSFETs-C Slide 31

Body Effect

Vt: gate voltage necessary to invert channel

Increases if source-to-body voltage increases because source is connected not to ground but drain of another transistor Effective source-to-body increases

Increase in Vt with VSB is called the body effect

Ground

VT of this transistoris “higher” becauseits source is not at ground

CMOS VLSI DesignMOSFETs-C Slide 32

Body Effect Model

s = surface potential at threshold

Depends on doping level NA

And intrinsic carrier concentration ni

= body effect coefficient

0t t s sb sV V V

2 ln As T

i

Nv

n

sioxsi

ox ox

2q2q A

A

NtN

C

ni = 1.45 X 1010 cm-3 for Silicon

T kT

q 26mv at 300°K

Key Point: transistors with source NOT at ground are harder to turn on.

17

CMOS VLSI Design

Question

MOSFETs-C Slide 33

Assume • One input changes only infrequently• Other changes frequentlyWhich input drives which transistor for faster gate?

Ground