mosfet i-v characteristics: general considerationee.sc.edu/personal/faculty/simin/elct563/16 mosfet...
TRANSCRIPT
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The channel current is: I = V (q nS μ W) /L = V q μ W (ci/q) × (VGS – VT) /L
MOSFET I-V characteristics:general consideration
The current through the channel is VI
R=
where V is the DRAIN – SOURCE voltage
Here, we are assuming that V << VT (we will see why, later on)
The channel resistance, R (W is the device width):
s
L LRq n aW q n Wμ μ
= =
-+ G
Semiconductor
The gate length L
DS
+-
V
VGS
I = μ W ci × (VGS – VT) V /L
where nS = (ci/q) × (VGS – VT)
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Key factors affecting FET performance (for any FET type):
In most MOSFET applications, an input signal is the gate voltage VGand the output is the drain current Id.The ability of MOSFET to amplify the signal is given by the output/input ratio: the transconductance, gm = dI/dVGS.
MOSFET transconductance
L I and gm
High carrier mobility μ and short gate length L are the key features of FETs
I = μ W ci × (VGS – VT) V /L
gm = V μ W ci /L
(V is the Drain – Source voltage)
From this:
μ I and gm
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Modern submicron gate FET
V-groove quantum wire transistor
Source Drain
Gate
Operating frequency – up to 300 GHz
2 μm
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When no drain voltage V is applied, the entire channel has the same potential as the Source, i.e. VCH = 0.In this case, as we have seen, nS = (ci/q) × (VGS – VT)
Drain current saturation in MOSFET
-+ G
Semiconductor
The gate length L
DS
+-
V
VGS
where VGS is the gate – source voltage and VT is the threshold voltage
When the drain voltage V is applied, the channel potential changes from VCH = 0 on the Source side to VCH= V on the drain side.In this case, the induced concentration in the channel also depends on the position.
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Drain current saturation in MOSFET
-+ G
Semiconductor
The gate length L
DS
+-
V
VGS
With the drain voltage V is applied, the actual induced concentration in any point x of the channel depends on the potential difference between the gate and the channel potential V(x) at this point.This is because this local potential difference defines the voltage that charges the elementary gate – channel capacitor.On the source end of the channel (x=0, VCH=0): nS(0) = (ci/q) × (VGS – VT).On the drain end of the channel (x=L, VCH= V): nS(L) = (ci/q) × (VGS – VT - V) < nS(0)At any point between source and drain,
nS(L) < nS(x) = (ci/q) × [VGS – VT – V(x)] < nS(0)
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L
nS
V=0
VGS > VT
x
Drain current saturation in MOSFET
V1 > 0
V2 > V1
V3 = VGS-VT
G
Semiconductor
DS
VVGS
Id
V
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MOSFET Modeling
1. Constant mobility model
Assuming a constant electron mobility, μn, using the simple charge control model the absolute value of the electron velocity is given by,
vn = μnF = μndVdx
With the gate voltage above the threshold, the drain current, Id, is given by
Id = WqμndVdx
ns Where W is the device width
Rewriting,Where VGT = VGS – VT.
d
n i GT
IdV dx
W c V V( )μ=
−
dV vs dx dependence represents a series connection of the elementary parts of MOSFET channel (for the series connection, voltages add up whereas current is the same).
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Integrating along the channel, from x=0 (V=0) to x=L (V=VDS), we obtain:
Id =W μn ci
L VGT VDS
Id =Wμnci
LVGT −
VDS2
⎛ ⎝ ⎜
⎞ ⎠ ⎟ VDS
For, VDS << VGT,
For, larger VDS ,
Linear region
Sub-linear region
dGT
n i
IV V ×dV dx
W c( )
μ− =
Sub-linear
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Channel pinch off and current saturationPinch off occurs when VG – VCH = VT at the drain end;
nS (L) =0; the current Id saturates
When,
VDS = VSAT = VGS − VT
where VSAT is the saturation voltage.
The saturation (pinch off) current,
Id = Isat =Wμnci
2LVGT
2
Id =Wμnci
LVGT −
VDS2
⎛ ⎝ ⎜
⎞ ⎠ ⎟ VDS
From the Id – V dependence, at VDS=VSAT = VGT,
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Transconductance
Defined as
gm =dId
dVGS VDS
From the equations for the drain current, Id, derived above, we find that
gm =βVDS , for VDS << VSATβVGT , for VDS > VSAT
⎧ ⎨ ⎩ β = μnci
WLwhere
High transconductance is obtained with high values of the low field electron mobility, thin gate insulator layers (i.e., larger gate insulator capacitance ci = εi/di), and large W/L ratios.
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2. Velocity saturation model
In semiconductors, electric field F accelerates electrons, i.e. the drift velocity of electron increases: v=μF
However, at high electric fields this velocity saturates
In modern short channel devices with channel length of the order of 1 µm or less, the electric field in the channel can easily exceed the characteristic electric, Fs field of the velocity saturation
Fs =vsμ n
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Electric field in the channel
the electric field in the channel in the direction parallel to the semiconductor-insulator interface
F =Id
qμ nns V( )W
0
0.2
0.4
0.6
0.8
1
1.2
0 1 2 3 4 5
Pot
entia
l (V
)
Distance (µm)
1
1.2
0
2
4
6
8
10
12
14
16
18
0 1 2 3 4 5
Ele
ctric
Fie
ld (k
V/c
m)
Distance (µm)
1
1.2
0 1 2 3 4 5Sur
face
Con
cent
ratio
n (1
012
1/cm
2 )
Distance (µm)
1
1.2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Potential, electric field, and surface electron concentration in the channel of a Si MOSFET for VDS = 1 and 1.2 V. L = 5 µm, di = 200 Å, µn = 800 cm2/Vs, VGS = 2 V, VT = 1 V.
vn = μnF = μndVdx
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Once the electric field at the drain side of the channel (where the electric field is the highest) exceeds Fs, the electron velocity saturates, leading to the current saturation.In short-channel MOSFETs, this occurs at the drain bias smaller than the pinch-off voltage VDS = VGT.
Field at drain
Saturation condition, Fs =ISAT
μ nci VGT − VSAT( )W
d
n i GT
IdV dx
W c V V( )μ=
−
dx L
n i GT DS
IdVF Ldx W c V V
( )( )μ== =
−
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Saturation current versus gate-to-source voltage for 0.5 µm gate and 5 µm gate MOSFETs. Dashed lines: constant mobility model, solid lines: velocity saturation model.
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MOSFET saturation current accounting for velocity saturation:
Isat =gchVGT
1 + 1 +VGTVL
⎛
⎝ ⎜
⎞
⎠ ⎟
2
where VL = FsL and the channel conductance gch = q µn ns W / L, where ns=ci VGT/q
When FS L >> VGT (MOSFET with long gate or no velocity saturation):
Isat =gchVGT
1 + 1 +VGTVL
⎛
⎝ ⎜
⎞
⎠ ⎟
22ch
sat GTg
I V≈ Id = Isat =Wμnci
2LVGT
2
(Expression obtained before on slide 9)
When FS L << VGT (MOSFET with short gate or early velocity saturation):
Isat =gchVGT
1 + 1 +VGTVL
⎛
⎝ ⎜
⎞
⎠ ⎟
2 sat ch LI g V≈
(Note that gch is controlled by VGT)
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Source and drain series resistances. Source and drain parasitic series resistances, Rs and Rd, play an important role, especially in short channel devices where the channel resistance is smaller.
Gate
DrainSource
I R s I Rd+ V +DS
R sR
d
ddV =ds
VGS = Vgs − Id Rs
VDS = Vds − Id Rs + Rd( )
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The measured transconductance (extrinsic)
gm =dIddVgs Vds =const
The intrinsic transconductance(VGS and VDS being intrinsic voltages)
gmo =dId
dVGS VDS=const
Where gd0 is the drain conductance gdo =dId
dVDS VGS =const
These parameters are related as gm =gmo
1 + gmo Rs + gdo R s + Rd( )
Similarly, extrinsic drain conductance can be written as,
gd =gdo
1 + gmo Rs + gdo Rs + Rd( )
In the current saturation region (VDS > VSAT), gd0 ≈ 0
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The saturation current in MOSFET with parasitic resistances:
Isat =gchoVgt
1 + gchoRs + 1 + 2gchoRs + Vgt / VL( )2
0
20
40
60
80
100
120
140
160
0 0.5 1 1.5 2 2.5
Dra
in C
urre
nt (m
A)
Drain-to-Source Voltage (V)
0
20
40
60
80
100
120
140
160
0 0.5 1 1.5 2 2.5
Dra
in C
urre
nt (m
A)
Drain-to-Source Voltage (V)
MOSFET output characteristics calculated for zero parasitic resistances and parasitic resistances of 5 Ω. Gate length is 1 µm
where VL = FsL and gcho = ciVgtµnW/L.
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MOSFET capacitance-voltage characteristics
To simulate MOSFETs in electronic circuits, we need to have models for both the current-voltage and the capacitance-voltage characteristics.As MOSFETs is a three terminal device, we need three capacitances: Cgs, Cgdand Cds. Capacitance (differential) is defined as C = dQ/dV. For example,
Cgs = dQs/dVgs (where Qs is the channel charge between S and G)Therefore, the total channel charge QN has to be divided (partitioned) between the source and drain charges. How should we partition QN between Qs and Qd? It is clear from the device symmetry that at zero drain bias Qs = Qd. If the total channel charge is QN, then Qs = 0.5 QN and Qd = 0.5 QN.
G
Semiconductor
DS
VVGS
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In this case, we let Qs = FpQN and Qd = (1 – Fp)QN, where Fp is the partitioning factor. In saturation, Fp > 0.5
The challenge using this model is to determine Fp as a function of Vgs and V
In the saturation regime, the charge distribution is no longer symmetrical: Qs > Qd
MOSFET capacitance-voltage characteristics
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Meyer model for MOSFET capacitance(used in SPICE)
22 13 2
GT DSgs i f
T DS
V VC C C
V V
⎡ ⎤⎛ ⎞−⎢ ⎥= − +⎜ ⎟−⎢ ⎥⎝ ⎠⎣ ⎦
Ci = ci × W × L is the channel capacitance
The capacitance Cf is the fringing capacitance.
C f ≈ βc εsWwhere βc ≈ 0.5
22 13 2
GTgd i f
T DS
VC C CV V
⎡ ⎤⎛ ⎞⎢ ⎥= − +⎜ ⎟−⎢ ⎥⎝ ⎠⎣ ⎦
In saturation, VDS has to be replaced by VSAT (where VSAT = VGT)
This results in CGS SAT = (2/3) Ci+Cf;CGd SAT = Cf
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Meyer model for MOSFET capacitance(used in SPICE)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VDS/VSAT
CGD/Ci
CGS/CiC
/Ci
0.0
0.1
0.2
0.3
0.4
0.5
0.6
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0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VDS/VSAT
CGD/Ci
CGS/CiC
/Ci