MOSFET Structure

Importance for LSI/VLSILow fabrication costSmall sizeLow power consumptionApplicationsMicroprocessorsMemoriesPower DevicesBasic PropertiesUnipolar deviceVery high input impedanceCapable of power gain3/4 terminal device, G, S, D, BTwo possible device types: enhancement mode; depletion modeTwo possible channel types: n-channel; p-channel

Symbolsp Channel MOSFETn Channel MOSFET

Current-Voltage Characteristic

Channel Formation

Analysis: Low VDS(A)

Intermediate VDS(B)

Increased VDS

Analysis: Intermediate VDSFirst Order ApproximationGate to Channel Voltage = VGS-VDS/2Extra term!

Large VDS: Saturation (C)

Analysis: Saturation (C)Pinch-offSubstitute for VDS(sat) in equation for IDS to get IDS(sat)

Avalanche and Punch-Through(D)For very large VDS, IDS increases rapidly due to drain junction avalanche.Can give rise to parasitic bipolar action.In short channel transistors, the drain depletion region may reach the source depletion region giving rise to Punch Through.

Structurep-type Silicon substraten+ ion implanted source and drain regionsHigh quality (thin) gate oxide (dry process)Overlaps slightly source and drain regionsThick field oxideProtection + carries contact tracksChannelRegion between source and drain and under gate.Enhancement Mode MOSFETn-channel with VG>VTSemiconductors:Si; Ge; GaAsInsulators:SiO3; Si3N4; Al2O3Most Important Combination:Si/SiO2Typical DimensionsLong channel MOSFETL>>WS, WDL ~ 5mmOxide Thickness50-100nmAnalysisMOSFET IV Characteristics {IDS, VGS, VDS}SimplificationsSource and bulk are groundedChannel mobility is less than substrate mobilityIncreased carrier scattering at surface!Assume

Distinctive Regions of CharacteristicA: Low VDSB: Intermediate VDSC: Large VDSD: Very Large VDSALow Drain Source VoltageVDS produces potential gradient in the channel0 at source; VDS at drainWeakens inversion in going from source to drain

However, if VDS is small then this gradient will be much smaller than the one in the perpendicular direction produced by the gate: [Gradual Channel Approximation]Ignore this effect for small VDS

When VGS>VT, get inverted channelIncreasing VGS increases inversionConductivity increasesDepletion width saturates (dmax) in inversionQD the depletion layer charge is unaffected

Carrier transport along the channel will be due to drift, I.e. due to VDSW is the channel width

W/L is known as the aspect ratio

For low VDS, IDS is linearly dependent on VDS.

VG-VT is constantIntermediate VDSMust take potential gradient along the channel into account!

Gives rise to a variation in potential between gate and substrate along the channel.

The net potential difference from the gate to the channel decreases towards the drain.

This results in a decrease in Qn along the length of the channel.A first approximation assumes that the gate to channel voltage is VGS-VDS/2Let VDS=VG-VT = VDS(sat)

Now the gate to channel voltage at the drain end is just sufficient to bring the channel there back to the point of inversion threshold.

There will be negligible free electron charge at the drain end.The channel pinches off.Current saturates or increases only slightly as the pinch-off region moves towards the source.As VDS increases above VDS(sat) two effects result:The channel length decreases.This would cause IDS to increase slightly.Depletion width increases.Increases resistance to current flow.Current should decrease.However, excess voltage [VDS-VDS(sat)] is dropped across the depletion region and compensates for the increased resistance.