4.1 Basic Physics and Band Diagrams for MOS Capacitors

Fig.4.1 (a) The schematic of a two-terminal MIS structure. (b) Band diagram of a two-terminal MIS structure at zero gate voltage, showing accumulation of holes near the surface. VFB is the flatband voltage, Xm is the metal work function, Xi is the electron affinity of the insulator, Xs is the electron affinity of the semiconductor, and Eg is the band gap of the semiconductor.

Two-terminal metal-insulator-semiconductor (MIS) structure: characteristic crucial to understand the operation of MOSFETs.

Assumptions:-Ideal MIS structure with no charges in the insulator layer and no surface states at the semiconductor-insulator interface.

-The insulator layer has infinite resistivity, thus there is no current across the insulator when a bias voltage is applied => Fermi level constant across the device.

Some definitions:-Work function: energy required to remove an electron from the Fermi level to the vacuum level (free space).-Electron affinity: energy required to remove an electron from the conduction band to the vacuum level.

At zero bias voltage, the band bending in the semiconductor layer is determined by the work function difference between the metal and the semiconductor, and it can be compensated by applying a voltage VFB to the gate

where VFB is called the flat-band voltage, Xm is the metal work function, and Xs is the semiconductor electron affinity.

Note: this equation for VFB is applicable for an ideal MIS structure; however, if there are charges in the insulator or at the insulator-semiconductor interface, then the gate voltage required to obtain flatband condition would change.

Fig.4.2 The band diagram of the two-terminal MIS structure under the flatband condition. Vg is the applied gate voltage.

EXAMPLE 4.1: A two-terminal Si MIS structure has a substrate doping of (p-type). Calculate the flatband voltage VFB of the structure if it employs (a) Al gate (Xm =

-poly gate. Assume that there is no charge in the oxide, Xs(Si) = 4.05 eV, and Eg(Si) = 1.12 eV.

SOLUTION: Ei EF = kT ln(NA/ni) = 0.026 ln[1016/(1.5 1010)] = 0.35 eV

Therefore, Si work function s = Xs + (Eg/2) + (Ei EF) = 4.05 + 0.56 + 0.35 = 4.96 eV(a) For Al gate, VFB = 4.1 4.96 = 0.86 V

Note: all these numbers can be equivalently represented either in volts or in electron-volts, depending on whether potential or energy is represented.

(b) -poly gate, hence, Xm = Xs = 4.05 eV

It is assumed here that the Fermi level of the n+-poly gate is coincident with the conduction band.

Therefore, VFB = 4.05 4.96 = 0.91 V

In Fig.4.1(b), note that Ev has come closer to EF near the semiconductor-insulator interface => hole concentration is greater near the interface than that in the bulk => this is referred to as the accumulation regime.

In Fig.4.2, note that after the application of a positive VFB to the gate, the bands in the semiconductor become flat => uniform concentration of holes throughout the semiconductor.

If the gate voltage is further increased, the holes near the insulator-semiconductor interface are pushed back deep into the bulk, leaving behind ionized acceptors near the surface and the bands bend downwards => formation of depletion region near the surface starts => referred to as the depletion regime [Fig.4.3(a)].

For even larger positive gate voltage, the band bending near the surface becomes so large that EF becomes closer to EC than to EV => the surface behaves like an n-type material => referred to as the inversion regime [Fig.4.3(b)].

Note: the increase in the band bending leads to an exponential increase in the electron concentration near the surface, e.g., an increase in the band bending by the amount of the thermal voltage VTH (= kT/q 26 mV at room temperature), increases the electron concentration by

Thus, a large change in the electron concentration near the surface can be accommodated by a small change in the surface potential Vs, and since the induced charge is proportional to the gate voltage Vg, hence, the derivative dVs/dVg becomes small in the inversion regime, whereas this derivative has a large value in the depletion regime.

When the difference between EF and Ei at the interface becomes equal and opposite of the bulk potential [ =(Ei EF)bulk = VTHln(NA/ni), where NA is the substrate doping

concentration and ni is the intrinsic carrier concentration], i.e., it is referred to as the onset of strong inversion.

The surface potential Vs is defined as (Ei,bulk Ei,interface)/q.

Operating regions:o VS < 0 => accumulationo > Vs > 0 => depletion

o => weak inversiono => strong inversion.

It is assumed that beyond strong inversion, the value of Vs does not change any more and it becomes pegged at .

An alternate definition has been proposed by Tsividis, which states that = |dVs/dVg| is quite large in the weak inversion regime, whereas it becomes relatively small in the strong inversion region.

Fig.4.3 The band diagram of a two-terminal MIS structure at (a) depletion and (b) inversion.

Thus, he defines Vs = as the onset of moderate inversion, and strong inversion actually takes place when Vs is greater than by several (3-5) VTH.

In today's context, the moderate inversion region (which can extend by 0.5 V or more) is extremely important for low power device applications in analog circuits.

However, for the time being, we would stick to the standard definition of strong inversion, and would discuss about moderate inversion later.

The surface electron and hole concentrations are given by

where pp0 = NA, and np0 = are the equilibrium hole and electron concentrations in the substrate respectively.

Note: at the onset of strong inversion Vs = , and also, that nsps = => consequence of zero current in the semiconductor (perpendicular to the semiconductor-insulator interface) => corresponds to constant (as a function of distance) EF in the semiconductor.

4.2 Surface Charge

The potential distribution in the semiconductor is described by the Poisson equation

where the space charge density with n(x) and p(x) expressed respectively as

where V(x) (Ei,bulk Ei(x))/q.

Note: deep into the bulk, from charge neutrality condition, NA = pp0 np0. Thus,

Using the definition of the electric field F = dV(x)/dx, the above equation can be rewritten as

Integrating this equation with respect to V, one gets

Thus,

Introducing the Debye length

the equation for F become

where

EXAMPLE 4.3: Draw the low- and high-frequency C-V characteristics, clearly showing all the relevant points, including the flatband capacitance, for a two-terminal MIS structure having 30 nm thick oxide and substrate doping of 1015 cm 3 (p-type). Assume VFB = 1 V.

SOLUTION: The oxide capacitance per unit area

The bulk potential

= (kT/q) ln(NA/ni) = 0.026 ln[1015/(1.5 1010)] = 0.29 V

The threshold voltage

The maximum width of the depletion region

The semiconductor capacitance per unit area at threshold

Therefore, the total capacitance per unit area at threshold

The Debye length

The flatband capacitance per unit area

The capacitance Csc becomes dominant in the strong inversion region, when the surface electron concentration is appreciable, since the band bending is largest at the surface.

Note: the electrons, which create the inversion region near the surface, are actually generated in the bulk due to thermal EHP generation.

Due to the electric field near the surface (recall that electric field points uphill in the band diagram), the electron and hole of the generated EHP are separated; the electron moves towards the surface and the hole moves towards the bulk => thus the rate of electron build-up near the surface proceeds at a rate limited by the rate of thermal EHP generation.

Fig.4.9 (a) The exact high-frequency equivalent circuit of a two-terminal MIS structure, and (b) its simplified equivalent.

Two new components in the equivalent circuit:o where T is the thickness of the semiconductor layer, and

is the hole mobility] is the resistance of the quasi-neutral p-region, ando Rgen (= dVs/dIgen) is a differential resistance, which is a characteristic of the EHP

generation process.

Igen is the generation current, given by is an effective generation time constant.

Thus, for gate voltages smaller than the threshold voltage VT,

In the small-signal equivalent circuit, the parameters Ceq and Req are given by

 

where

and

Note: both Ceq and Req are frequency dependent: in the limiting case of + Cdep, and in the other limiting case of

Fig.4.10 The C-V characteristics for a two-terminal MIS structure at different frequencies.

4.4.1 Extraction of Parameters from the C-V Characteristic

Fig.4.11 Parameter extraction from the C-V characteristic for a two-terminal MIS structure. The parallel shift in the characteristic after the bias-temperature stress test (described later) is also shown.

The maximum measured capacitance Cmax in the accumulation region gives the dielectric thickness

The minimum measured capacitance Cmin at high frequency gives the doping concentration (assumed uniform) in the substrate. Steps:

o First, determine the depletion capacitance Cdep in the strong inversion region from 1/Cdep = 1/Cmin 1/Cmax.

o Then, obtain the depletion region thickness fromo And, finally, calculate the doping concentration from the following two equations:

o These two equations need to be solved by iteration: first choose a suitable value for (say, 0.3 V), obtain NA, recalculate , obtain another fine tuned value of NA, and repeat the process until the desired accuracy is achieved.

It also gives the information about the flatband voltage VFB. Steps:o The device capacitance CFB under flatband condition can be given by CFB =

CiCs0/(Ci + Cs0) =

o Thus, o From a knowledge of di and NA, CFB/Cmax can be obtained, and the intercept can

be found on the C-V curve to yield VFB.

 

4.5 Non-ideality in an MIS Structure: Oxide Charges

In most of the commercially available MOS capacitors and MOSFETs, silicon (Si) is used as the semiconductor and silicon dioxide (SiO2) is used as the insulator.

Si being a crystalline material and SiO2 being an amorphous material, there is a sudden discontinuity in the lattice structure at the Si-SiO2 interface.

Fig.4.12 Different types of charges in the Si-SiO2 interface and in the SiO2 layer.

 

This interface has attracted considerable interest over the last few decades, and significant studies have been made on this structure, however, a detailed understanding of many of its features is still lacking.

The interface and the oxide contains various types of charges, which can be broadly categorized into the following:

o Charges due to fast surface states (or interface trapped charges) located at the interface.

o Charges due to mobile impurity ions located in SiO2.

o Charges due to traps ionized by radiation within SiO2.

o Fixed surface state charges located at the interface.

4.5.1 Fast Surface States

These are also referred to as Tamm and Shockley states, after their inventors. These are created at the interface due to the sudden termination of the crystal periodicity,

since all the bonds of the atoms at the surface are not fulfilled these unfulfilled bonds are referred to as the dangling bonds.

Obviously, the density of these states is a function of the crystal orientation (since (100) planes have lower atom density than (111) planes, MOSFETs are universally fabricated on (100) oriented Si).

Roughly, one fast surface state is assigned for every surface atom, resulting in a density

Proper cleaving of the surface and consequent heat treatment with H2 drastically reduces the density of these states to or so, since H2 compensates some of these dangling bond by the formation of SiH.

These states behave acceptor-like or donor-like, depending on the position of the Fermi level at the surface and the amount of band bending, and these are referred to as fast states, since they capture and release the carriers at a fast rate.

When the surface potential changes, the charges in the surface states change as well, and leads to a shift in VT and a change in the C-V characteristics.

Fig.4.13 The experimental C-V characteristics showing the difference between them due to the presence of fast surface states.

There is a shift of the C-V curve towards the left due to the fast surface states, which changes the flatband voltage.

In the equivalent circuit of an MIS structure, the fast surface states can be represented by an additional series combination of an equivalent capacitance Css of the surface states, and an additional resistance Rss, with the time constant RssCss representing the time response of the surface states.

Fig.4.14 The overall high-frequency equivalent circuit for a two-terminal MIS structure showing the additional components Css-Rss to account for the effects of fast surface states.

Measurements of frequency-dependent MIS capacitance and conductance give information about the density of the surface states.

4.5.2 Ionic Contamination

A major difficulty with early MOS devices was the instability of the threshold voltage VT, i.e., it used to vary with bias under elevated temperatures.

This happens due to the rearrangement of the mobile ions within the oxide, which are introduced into the oxide from the furnace walls during oxidation.

Fig.4.15 Shift in the C-V characteristic after the bias-temperature stress test due to ionic contamination in the oxide, and its partial recovery after annealing with gate-substrate shorted.

The initial C-V characteristic is marked by (1), while those observed after 30 minutes at 127 C with VG = +10 V applied is marked by (2), and after heating the device for 30 minutes at the same temperature with the gate shorted to the substrate yields characteristic marked by (3)- this experimental procedure is known as the bias-temperature stress test.

Fig.4.16 Charge distribution during the various stages of the bias-temperature stress test and post annealing.

Initially, all the positive ionic charges are located at the metal-SiO2 interface, exerting no influence on Si; after positive gate bias at high temperature, all these ionic charges cluster near the Si-SiO2 interface and induce all the image charges in Si; finally after recovery, the ions create an arbitrary distribution (x) within the oxide, inducing image charges in both the gate and the semiconductor.

For any arbitrary distribution of the oxide charges (x), the shift in the flatband voltage

can be given by

where di is the oxide thickness.

The menace created by mobile ions is reduced to a large extent in today's technology due to the improvements in the fabrication process.

EXAMPLE 4.4: In a two-terminal MIS structure having 40 nm thick oxide, the shift in the flatband voltage after a bias-temperature stress test was found to be 10 mV. Determine the mobile ionic contamination per unit area in the oxide in numbers per unit area.SOLUTION: The oxide capacitance per unit area

The shift in the flatband voltage due to the mobile ionic contamination after bias-temperature

stress test is given by Thus, the mobile ionic contamination per unit area in the

oxide

4.5.3 Radiation-Induced Space Charge

A positive space charge is seen to build up in SiO2 films when it is irradiated by ionizing radiation of various kinds, e.g., X-ray, gamma ray, low- and high-energy electron irradiation, etc. (potential danger during ion implantation).

The physical origin of this charge is completely different from the ionic contamination. Due to irradiation, EHPs will be generated within the SiO2. In the absence of any electric field within the oxide, these carriers will immediately

recombine; however, under a positive applied gate bias, due to the electric field within the SiO2, the generated electrons and holes would separate, with the electron moving towards the metal-SiO2 interface, and the hole moving towards the SiO2-Si interface.

Thus, a space charge layer starts to build up within the oxide due to these charges, thus creating an electric field within the oxide, which is opposite to that of the applied field => changes VFB, and, thus, VT.

These charges can be eliminated by thermal annealing.

4.5.4 Surface State Charges

A fixed charge is seen to exist within the oxide very near the Si-SiO2 interface, which results in a parallel translation in the C-V characteristics along the voltage axis these charges are called the surface state charges, and the density of these charges per unit area

is denoted by These surface states have the following properties:

o It is fixed, i.e., its charge states cannot be changed over a wide variation in the band bending.

o Unchanged under bias-temperature stress test and thermal annealing.

o It is located within 200 of the Si-SiO2 interface.o Its density is not significantly altered by the oxide thickness, or by the type or

concentration of impurities in Si.o Its density is a strong function of the oxidation and annealing conditions, and the

orientation of the Si crystal.

The ratio o f in (111), (110), and (100) Si are in the ratio 3:2:1, and is a strong function of the oxidation condition.

Popular theory: originates from the excess ionic Si in the oxide, which moves into the growing SiO2 layer during the oxidation process.

can be reduced by a large extent by H2 heat treatment

4.6 General Expression for the Flatband Voltage VFB

The general expression for the flatband voltage VFB can be given by

where where m is the metal work function and is the semiconductor

work function; is the oxide charges lumped at the Si-SiO2 interface, and is any arbitrary distribution of charges within the oxide.

 

4.7 Some Advanced Models

4.7.1 Unified Charge Control Model (UCCM) for MIS Capacitors

The standard charge control model (SCCM) postulates that the interface inversion charge of electrons qns is proportional to the applied voltage swing VGT = VG -VT.

This model is an adequate description of the strong inversion region of the MIS capacitor, but fails for applied voltages near and below VT (i.e., in the depletion and weak inversion regions).

A new model has recently been proposed which has been shown to model the device behavior adequately both in the weak and strong inversion regions, and is given as:

where is the permittivity of the gate insulator,

di is the thickness of the gate insulator, is an ideality factor, and is a correction to the insulator thickness related to the shift in the Fermi level in the inversion layer with respect to the bottom of the conduction band.

Note: Eq.(4.24) does not describe the mobile charge in the accumulation region, however, this region is not important for MOSFET operation.

This correction is dependent on the interface electron density, however, it can be approximately taken to be a constant for typical values of the interface electron density.

For Si-SiO2 MOS capacitors hence, it can usually be assumed that

The ideality factor reflects the gate voltage division between the insulator layer capacitance Ci and the depletion layer capacitance Cdep.

In the subthreshold regime, At the onset of strong inversion (VGT = 0), the surface potential Vs has the value Below threshold, we have the following approximate relationship:

Note: in general, is dependent on VGT, and at low substrate doping levels, is close to unity near threshold where the gate depletion width is large (corresponding to Cdep << Ci).

Usually, Cdep can be estimated as follows:

is an average width of the depletion region.

Equation (4.24) is an empirical equation, which can be justified by comparing the calculation results with experiments and more precise calculations.

Intuitively, the structure of the UCCM expression [Eq.(4.24)] seems reasonable, since in the strong inversion region, it reverts to the simple charge control model [i.e.,

while in the subthreshold region, it predicts that the inversion charge is an exponential function of the applied voltage, as expected.

Since UCCM is an empirical model, it is especially important to have a clear and unambiguous procedure for extracting model parameters from experimental data.

For the MIS structure, this extraction of parameters is based on the C-V characteristics, which shows a sharp increase in the capacitance (at low frequencies) during the transition from the depletion to the strong inversion region.

The voltage at which the derivative of the MIS capacitance reaches its maximum value is very close to the threshold voltage VT.

The first derivative of Eq.(4.24) with respect to VGT yields the following unified

expression for the metal-channel capacitance per unit area valid for all values of applied bias voltage:

The first derivative of this capacitance

reaches its maximum value for

Hence, the following sheet inversion charge density at threshold is obtained:

and the value for the unified capacitance per unit area at threshold becomes

Here, is the maximum value of Equation (4.33) serves as the basis for a very convenient and straightforward technique

for determining the threshold voltage from experimental data.

Fig.4.17 Measured gate-channel capacitance as a function of gate-source voltage for an n-channel MOSFET for different values of substrate bias.

From the experimentally determined gate-channel capacitance, the inversion carrier sheet density can be calculated as

According to UCCM, this should agree with Eq.(4.29), which can be written as

Hence, from a plot of versus and a can be found. The slope of this plot gives , while the intercept with yields a.

Fig.4.18 Inverse gate-channel capacitance plotted as a function of the inverse mobile sheet charge density (data obtained from Fig.4.17).

Fig.4.19 Measured dependence of (curves to the left) and -1 V (curves to the right). The threshold voltages determined by the two methods are also indicated.

The values of obtained from the slopes in Fig.4.18 agree very well with those determined directly from the subthreshold I-V characteristics, and the value of di calculated from a is in excellent agreement with that measured by ellipsometry.

In Fig.4.19, the value of VGS corresponding to the peak value of should coincide with the value of VGS at which the gate-channel capacitance has dropped to one-third of its maximum value.

In Fig.4.20, the agreement between the measured and the calculated data is excellent for the entire range of gate bias.

Fig.4.20 Measured (solid lines) and calculated (UCCM, symbols) ns versus VGS characteristics for different values of Vsub in (a) semilog scale and (b) linear scale. In (b), the results obtained from the simple charge control model (SCCM) are also shown.

The deviation in the measured curves found in the deep subthreshold region is due to two reasons: one is the C-V measurement error, and the other is the leakage current, which dominates deep subthreshold operation.

At deep subthreshold, the channel offers a large series resistance compared with the reactance of the capacitance.

4.7.1.1 Analytical Unified MIS Capacitance Model

Note: the UCCM does not have an exact analytical solution for the inversion charge in terms of the applied voltage even though an accurate approximate solution can be obtained.

Above threshold, the sheet density of carriers in the inversion layer can be given as

Below threshold, the electron sheet density in the channel can be written as

From Eq.(4.37), the following expression is obtained for the subthreshold differential channel capacitance per unit area

An approximate, unified expression for the effective differential metal-channel

capacitance per unit area is obtained by representing it as a series connection of the above threshold and the subthreshold capacitances, i.e.,

Hence, the unified carrier sheet charge density becomes

Equation (4.40) is similar to an interpolation formula, and calculations show that it is in excellent agreement with UCCM.

4.8 Quantum Theory of the Two Dimensional Electron Gas (2DEG)

Classically, the electrons induced at the semiconductor-insulator interface of an MIS capacitor form a classical electron gas and behave essentially in the same way as electrons in a bulk semiconductor.

This assumption is only correct if the thickness of the inversion layer is much larger than the deBroglie wavelength for electrons.

For the classical electron gas, this thickness d can be estimated as where Fs is the surface electric field, and using Gauss' law, this field can be approximated as

In this estimate, the condition of continuity of electric displacement across the semiconductor-insulator interface is used, and it is assumed that almost all of the applied voltage drops across the insulator.

Hence, In modern day MOSFETs, di can be well below 100 , and may become smaller than

the deBroglie wavelength, e.g., for di = 100

In this case, the quantization of the energy levels in the potential well at the semiconductor-insulator interface in the direction perpendicular to the interface must be taken into account.

Once quantization of energy levels take place, then the dispersion (E-k) relation in the direction parallel to the interface is given by:

where En is the electron energy, Ej is the energy level of the jth subband, and ky and kz are the wave vector components parallel to the interface.

Fig.4.21 Schematic diagram of energy subbands at the semiconductor-insulator interface (assuming constant effective field approximation).

For a relatively thick electron gas layer, the number of subbands is large and the energy difference between the bottoms of the subbands is small (<< kT).

For a relatively thin electron gas layer, only the lowest few subbands are important for electron occupation, and the energy difference between the bottoms of the subbands may become large compared to the thermal energy kT.

In this case, the electron gas is often referred to as a two-dimensional electron gas (2DEG).

The density of states D for each subband is given by which is a constant and independent of the subband energy Ej => the overall density of states has a staircase dependence on energy for a triangular quantum well, which is characteristic for the semiconductor-insulator interface of an MIS structure.

The number of electrons occupying a given subband j can be found by multiplying the density of states D for a single subband by the F-D distribution function, and integrating from Ej to infinity:

Fig.4.22 Energy levels (bottoms of subbands) and density of states for a triangular quantum well structure (j = 1, 2, …, correspond to the different subbands).

After evaluating this integral and adding the contribution from all subbands, one obtains

The quantized energy levels for the subbands can be found using a numerical self-consistent solution of the dinger and Poisson's equations.

However, an excellent approximation for the exact solution can be found by assuming a linear potential profile (i.e., constant effective field Feff) in the semiconductor and close to the semiconductor-insulator interface.

In this case, the energy levels are given by

where is the effective mass for electron motion perpendicular to the (100) surface, and Ec(0) is the minimum conduction band energy at the Si-SiO2 interface.

The effective field Feff is expressed through the surface field FS and the bulk field FB. For electrons, the relationship linking Feff, FB, and FS, giving the best fit to the self-

consistent solution of dinger and Poisson's equation is given by and Feff = (FS + FB)/2, where ns is the interface electron sheet

density, and qnB (= qNAddep(av)) is the sheet density of depletion charge. Similarly, for holes, FS = q(ps + where ps is the

interface hole sheet density, and qpB (= qNDddep(av)) is the sheet density of depletion charge.

In reality, it has been found that a slightly different form of the effective field Feff1 = (FS + 2FB)/3 gives a better fit to the measured data.

Solving these equations iteratively, one can obtain the relation between ns and the Fermi level [EF Ec(0)].

Fig.4.23 Comparison of the interface carrier density versus EF Ec(0) characteristics for different substrate doping densities in (a) semilog plot and (b) linear plot. Symbols: calculations based on a 2DEG formulation, solid lines: charge sheet model, straight line in b): linear approximation to 2DEG formulation, the slope gives

 

In the calculation, it can be assumed that the maximum value of nB is given by

In the subthreshold region, the calculation agrees reasonably well with the classical charge sheet model (CCSM) given by Brews:

especially at low levels of substrate doping.

The difference between the curves at high substrate doping levels is caused by the fact that the large bulk field quantizes the energy levels even in the subthreshold region.

However, at strong inversion, the difference between the charge sheet model and the 2DEG formulation is large.

As can be seen from Fig.4.23, the dependence of ns on EF in the above threshold regime can be approximated by a straight line: where EF0 is the intercept of this linear approximation with ns = 0.

This approximation means that a fraction of the applied voltage, equal to is accommodated by a shift in the Fermi level with respect to the bottom of the conduction band.

The shift in the Fermi level with respect to the bottom of the conduction band changes the

above-threshold capacitance from to where the parameter can be interpreted as a correction to the insulator thickness.

From the straight-line approximation in Fig.4.23b), is obtained, which is much

smaller than that of This difference is caused by

o a much larger effective mass in the conduction band in Si, which makes quantum effects much less pronounced, and

o the large difference in the dielectric constants between the insulator and the semiconductor for the MOS system.

Practice Problems

4.1 Clearly draw the band diagrams for an ideal MOS structure and no oxide charge) on n-type Si for i) accumulation, ii) depletion, and iii) inversion. If the oxide thickness tox = 40 nm and VG = 1 V, determine the magnitude and sign of the charge density in the semiconductor. What is the status of the surface?

4.2 Show that for an MOS structure on p-type Si, the electron and hole concentrations as

functions of position are given by where n0 and p0 are the equilibrium electron and hole concentrations respectively, and is defined by = [Ei(bulk) Ei(x)]/q.

4.3 Continuing with the derivation given in Section 4.2, show that the electric field E in the

semiconductor in an MIS capacitor can be given by where all the notations carry their usual meanings.

4.4 Sketch the electric field and voltage distribution in an MOS structure at the threshold gate voltage. Data: substrate voltage = 0, and VFB = 0. Compute the threshold voltage VTH from the voltage distribution.

4.5 Calculate and plot the semiconductor surface charge per unit area for an MIS structure as

a function of the surface potential

4.6 Starting from Eqn.(4.16), show that at flatband (i.e., when Vs = 0), the flatband capacitance

per unit area Hence, compute its magnitudes for substrate dopings of

4.7 Consider the energy band diagram of a metal-SiO2-Si-SiO2-metal structure as shown in Fig.P7. Assume symmetric bands with

(a) What is the flatband voltage for this structure?(b) Sketch the band diagram of the structure when the left metal plat is at 2 V and the right metal plate is grounded. Assume What is the strength of the electric field in Si? What are the positions of the Imrefs in Si? In the band diagram, all the appropriate voltage levels must be specified. Neglect induced charges in Si.

4.8 (a) Find the voltage VFB required to reduce to zero the negative charge induced at the

semiconductor surface by a sheet of positive charge located below the metal.

(b) In the case of an arbitrary distribution of charge in the oxide, show that

where = oxide capacitance per unit area = where d = oxide thickness.

4.9 Charge density of is distributed in the oxide (d = 40 nm) in a Si MOS capacitor. Assume Find the flatband voltage required to be applied at the gate to compensate these charges if: i) the charges are uniformly distributed in the oxide, ii) the charge distribution is linear with the peak at the metal-SiO2 interface and zero at the Si-SiO2 interface, and iii) same as ii) but now with the peak at the Si-SiO2 interface and zero at the metal-SiO2 interface. Physically justify the answers.

4.10 An Al-gate where m is the Al work function to vacuum) MOS

structure is made on p-type % where is electron affinity for

Si) substrate. The SiO2 thickness d = 50 nm, and the effective oxide interface charge

Find Wmax, VFB, and VTH. Sketch the C-V curve for this device giving all relevant details.

4.11 Find VTH for an MOS structure in Si with p-type substrate

and d = 80 nm. Repeat for n-substrate with the same parameters (note: the new can be calculated from the change in EF).

4.12. Calculate and plot the maximum width of the depletion region for an ideal (i.e., VFB = 0) MIS capacitor on p-type Si with as a function of the substrate bias Vsub for -2 V < Vsub < 0.1 V. Assume that the voltage difference between the inversion layer at the interface and the gate contact is maintained constant when the substrate potential is changed (charge screening), so that the substrate voltage reverse biases the inversion layer/p-type substrate junction. Also, calculate the threshold voltage VT, and the capacitance of the structure at low and high frequencies for V >> VT for Vsub = 0. Data: ni =

4.13 Calculate and plot the surface potential as a function of the gate voltage VG in depletion and inversion for a two-terminal MIS structure. Identify the weak inversion, moderate inversion, and the strong inversion regions in the plot (as per Tsividis). Can the plot be really linearized in subthreshold? Determine an effective value of in subthreshold from the plot.

4.14 Calculate and plot the gate-to-substrate capacitance Cmis as a function of the gate voltage VG

for a two-terminal MIS structure with area = The plot should show all the regions of operation (i.e., accumulation, depletion, weak inversion, and strong inversion). Mark Cso in the plot, with the magnitude shown. (Note: the externally measured capacitance includes the oxide capacitance).

4.15 Calculate and plot the temperature dependence of the surface charge per unit area for the surface potential i) in the temperature range between 150 K and 450 K. Data: effective densities of states in conduction and valence bands and

respectively at 300 K (with both of them having a dependence), and the energy gap Eg = 1.12 eV (the variation of the energy gap with temperature may be neglected).

4.16 From the equivalent circuit for an MIS structure, determine the expression for the impedance across its two terminals as a function of frequency. Hence, calculate and plot the effective capacitance of the structure as a function of the gate voltage VG (varying from -5 V to +5 V) for frequencies of

4.17 As a practice problem, draw any arbitrary C-V curve of your choice, and following the parameter extraction algorithm discussed in Section 4.4.1, obtain the i) oxide thickness, ii) threshold voltage, iii) substrate doping, iv) flatband capacitance, v) flatband voltage, and vi) fixed oxide charges.

4.18 The C-V curve of a two-terminal MIS structure shows a shift of 10 mV in the flatband voltage after a bias-temperature stress test. If the flatband voltage before

the stress test is -1 V, and the surface state density is determine the oxide fixed charges.

4.19 Derive Eqn.(4.40).

4.20 Derive Eqn.(4.43).

4.21 (a) Compute and plot the surface electron concentration ns as a function of [EF - EC(0)] under the 2DEG approximation for (b) Repeat part (a) under the 3D approximation (i.e., the 3D charge sheet model as given by Brews).Data: (Note: the

constant energy surface for Si consists of six ellipsoids of revolution, and ml ( ) and mt (

) represents the lateral and transverse effective mass respectively. For {100} direction four of these ellipsoids will lye on the surface and two ellipsoids will be perpendicular. Refer to Problem 22 also.)

4.22 In the classical limit, the separation of the energy subbands in a 2D electron gas is small compared to the thermal energy kT. In this case, the sheet density of the 2D electron gas is given by the classical charge sheet model, given by Eqn.(4.46), which is derived using a conventional 3D electron gas approach. Show that in this limit (i.e., Ej Ej 1 << kT), the equation

reduces to Eqn.(4.46). In the above equation, mpi is the parallel effective mass for the valley i, and Eji is the energy level of the jth subband in valley i. Note: the effective mass mpi is mt for two valleys, and for four valleys, where mt and ml is the transverse and lateral effective mass respectively.

METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS (MOSFETs)

Principle of Operation

Schematic diagram of an n-channel MOSFET, where two n+ source and drain regions are diffused into a p-type substrate, making it a four terminal (drain, source, gate, and substrate) device.

A four-terminal device obtained from an extension of the two-terminal MIS structure by diffusing or implanting two n+ regions into the p-type substrate in order to form two ohmic contacts called the source and the drain.

A thin layer separates the third contact (gate) from the channel region of the device, and a fourth contact (body or bulk or substrate) is connected to the substrate.

When a positive voltage is applied to the gate, a thin channel of electrons is created near the Si- interface, which provides a conducting link between the source and the drain => on state of the device.

In the absence of a conducting channel, no electrical continuity between the drain and the source exists => off state of the device.

The depletion regions between the p-type substrate and n+ regions and n-channel provide the required isolation from other devices fabricated on the same substrate.

In the on state of the device, an applied drain-to-source bias creates a drift field in the channel, and electrons move from the source to the drain => thus a current is established.

The electron concentration in the channel (and, thus, the channel conductance and device current) can be modulated by a variation in the gate voltage.

Note: the C-V characteristic of this device shows low-frequency behavior (of the two-terminal MIS structure) up to a fairly high frequency (of the order of the inverse transit time of the carriers across the channel), since the heavily doped source/drain regions provide an infinite reservoir, from which the carriers can move into the channel, or to which they can escape from the channel.

The I-V Characteristic

The Gradual Channel Approximation (GCA)

The GCA, proposed by Shockley, is used in order to calculate the I-V characteristic of the device.

This approximation states that the rate of variation of the lateral field within the channel

is much smaller than the rate of variation of the vertical field, i.e., , and the channel potential is assumed to be a gradually changing function of position.

Note: This approximation actually states that the channel potential varies very little along the channel over a distance of the order of the insulator thickness , i.e., this requires << L, where L is the channel length.

The gradual channel approximation (GCA): Fig (a) schematic comparison of the parallel and perpendicular electric fields in the channel, and Fig (b) qualitative potential profile in the channel.

However, modern MOSFETs have extremely short channel lengths, and this requirement is not often met; thus, the GCA fails for most of modern MOSFETs, nevertheless its discussion is important.

According to GCA, the charge induced at any position along the channel can be determined from the formulas derived for the MIS structure, provided the constant surface potential for an MIS structure is replaced by a variable channel potential in the expression for the surface charge density per unit area in the semiconductor.

Assumption: The device is operating in the above threshold regime, i.e., the gate voltage is sufficiently large to create strong inversion throughout the channel.

The induced surface charge density is then given by

where is the insulator capacitance per unit area, and the term within the square brackets is the voltage drop across the insulator.

Band diagrams at

Fig (a) the source side and Fig (b) the drain side of the channel for the direction perpendicular to the Si- interface.

Note: here we are considering an n-channel device, however, all the results are also applicable for a p-channel device, provided appropriate sign changes are made.

Assume that the source is grounded , the drain is connected to a potential , and the substrate is connected to the source

The density of the free electrons in the channel can be found from the difference

between the total surface charge density and the depletion charge density , i.e.,

Qualitative two-dimensional plot of the conduction band edge for an n-channel MOSFET.

Note: at the source side of the gate where = 0, is given by

however, elsewhere in the channel, the total band bending between the substrate and the

surface is , since the induced n-channel/p-substrate junction is reverse biased by the .

The band bending increases in the channel as one moves from the source to the drain, which leads to an increase in the width of the depletion layer and of the depletion charge

density, thus, the exact expression for can be given by

Since the drain current is carried entirely due to drift, its expression can be given by

where is the low-field electron mobility, and W is the channel width.

In writing this equation, it is assumed that the electron drift velocity is proportional to the component of the electric field parallel to the Si- interface, i.e., .

Note: for short channel devices, this electric field may be sufficiently high to cause velocity saturation in the channel.

Thus, the drain current equation can be rewritten as

Note: is a function of ; thus, substituting the expression for in the above equation, noting that is a constant throughout the channel, and integrating it from the source, i.e.,x = 0 ( = 0) to the drain, i.e., x = L ,

the following I-V characteristic is obtained:

This model is known as the Shockley model. This expression for is valid only if the inversion layer exists even at the drain side of

the gate, i.e., The condition is referred to as the pinch-off condition, and it occurs at the drain

side of the gate when

As (first-order approximation), where is the threshold voltage corresponding to the onset of strong inversion, and is given by

In the presence of a substrate bias , the expression for gets modified to

The band diagram of an n-channel MOSFET along the direction perpendicular to the Si- interface for a negative substrate bias.

Note: is the voltage difference between the inversion layer at the source end and the substrate contact, and its sign should be such that it never forward biases the inversion

layer-substrate junction (a small forward bias, much less than may be allowed in certain cases).

If the inversion layer-substrate (or the source-substrate or the drain-substrate) junction ever gets forward bias, a large leakage current would result, which would hamper normal MOSFET operation.

For both n- and p-channel MOSFETs, the magnitude of the threshold voltage VT increases with an increase in |Vsub|.

Physical Understanding of Saturation

A physical insight into the phenomenon of saturation may be obtained by analyzing the electric field distribution under the gate.

Integrating Eq.(5.6) from 0 to x, one gets :

  or

The electric field in the channel in the direction parallel to the semiconductor-insulator interface can be found from Eq.(5.5)

:

Solving Eqs.(5.12) and (5.13) together, the field profiles can be calculated.

Fig.5.6 The variation of the electric field along the channel for drain voltage nearly equal to the saturation voltage for gate voltages

Note: from the constancy of the drain current throughout the device, it can be seen that as and the electric field F(L) diverges.

The differential drain conductance

tends to zero when and the I-V characteristics may be extrapolated in the voltage region assuming a constant (independent of drain current

may be found by substituting from Eq.(5.8) into Eq.(5.7), which results in a highly complicated expression, however, it can be simplified for gate voltages close to the threshold voltage

Note: this approach is only valid when the channel electrons do not suffer any velocity saturation due to high electric fields.

Note: modern day MOSFETs have extremely small gate lengths, and the channel has high electric fields (more than the critical electric field required for velocity saturation), which creates the velocity saturation effects for the channel electrons.

Fig.5.7 The I-V characteristics of an n-channel MOSFET for different values of gate

voltage . The dashed line represents the drain-to-source saturation voltage.

Fig.5.8 The variation of the drain saturation current with gate voltage for three different values of substrate doping.

For very small the terms under the curly brackets in Eq.(5.15) can be expanded in Taylor series, leading to the following simplified expression for the I-V characteristics in the linear region:

A physical justification of Eq.(5.16) can be given as follows: At very small the charge induced in the channel is, to the first order, independent of

the channel potential, thus,(5.17)

Now, for small the electric field F in the channel is nearly constant, and is given by

The drain current is entirely due to drift, and is given by the electrons in transit model:

since

5.2.3 The Charge Control Model

A simplified description of the I-V characteristics of a MOSFET can be obtained by using the charge control model.

In this model, it is assumed that the concentration of free carriers induced in the channel is given by

Compare Eq.(5.19) with Eq.(5.2): in Eq.(5.19), the variation of the depletion charge

density with the channel potential has been neglected.

The drain current can now be given by

Compare Eq.(5.20) with Eq.(5.5). Equation (5.20) can be rewritten as

 

Integrating Eq.(5.21) from x = 0 (source side) to x = L (drain side), which corresponds to

a change in from the following expressions for the I-V characteristics are obtained:

Fig.5.9 The I-V characteristics of an n-channel MOSFET calculated using the charge control model (solid curve) and the Shockley model (dashed curve).

The differential transconductance is defined as

From Eqs.(5.22) and (5.23),

where is referred to as the device transconductance parameter, with

is referred to as the process transconductance parameter.

Thus, in order to achieve a high value for the transconductance gm, the following steps may be taken.

Higher value of low field electron mobility Thinner gate dielectric layers, which in turn gives large values for the insulator

capacitance per unit area Large widths (W) and short lengths (L). Note: for short channel devices, where velocity saturation effects are important, the

dependence of transconductance on the low-field electron mobility and the gate length gets strongly affected.

EXAMPLE 5.1: An n-channel MOSFET with the process transconductance parameter

the threshold voltage is biased at Determine the drain current ID, the transconductance and the drain conductance

SOLUTION:

i)

Hence, the device is under linear mode of operation

.

Note the huge change in transconductance in saturation as compared to the linear region: this is due to the square law dependence of current on the gate voltage in the saturation region (as against the linear variation in the linear region).

Drain Conductance

This is due to the independence of the saturation drain current on the drain voltage. In reality, channel length modulation creates a change in drain current with respect to the drain voltage in saturation, and finite drain conductance

Effect of Source and Drain Series Resistance

The analysis so far neglects the effects of the source/drain series resistance, and the entire voltage is assumed to drop along the channel.

However, for modern day MOSFETs, this effect cannot be ignored, due to smaller diffusion cross-sections and smaller drain currents.

The extrinsic (measured) voltages can be related to the intrinsic (device)

voltages by the following equations:

where are the source and drain resistances respectively.

The extrinsic transconductance is related to the intrinsic transconductance

where is the intrinsic drain conductance.

Similarly, the extrinsic drain conductance is related to the intrinsic drain conductance

Fig.5.10 The variation of the drain saturation current as a function of the gate voltage for

three different values of the series source resistance

Fig.5.11 The drain current drain-to-source voltage characteristics for different values of

The series source resistance reduces the drain current, and the series drain resistance increases the drain-to-source saturation voltage.

Both series source resistance and series drain resistance reduce the drain conductance at low drain-to-source voltages.

Velocity Saturation Effects in MOSFETs

In modern day MOSFETs, the channel length is very small, the electric field in the channel is very high, and the velocity saturation effects are very important.

The measured electron and hole mobilities in the inversion layer may be quite different than those measured in the bulk.

Note: the channel, in reality, is under a two-dimensional electric field, one directed

longitudinally from the gate to the substrate, and the other directed laterally along the length of the channel.

The effective inversion layer thickness is approximately given by thus, a large vertical field creates a narrow inversion layer, and vice versa.

Fig.5.12 The random path of electrons in the channel, undergoing surface scattering, which is more intense in narrow channels.

Electrons in the channel move in random directions, undergoing surface scattering, which increases for narrow channels thus their mobility drops.

Fig.5.13 The variation of the electron and hole mobilities in the channel as a function of the gate electric field.

The dependence of the electron and hole mobilities on the gate field can be crudely approximated by

where n0 and p0 are the electron and hole mobilities for

It is very interesting to note that in highly constricted channels or at low temperatures, the carrier mobility is seen to get enhanced.

This is because for these cases, the electron motion in the direction perpendicular to the

interface gets quantized, and the channel electrons behave like a two-dimensional electron gas (2DEG).

Thus, the surface scattering is not that important, and the impurity scattering is screened by a high density of electrons in the channel.

Such enhancement of electron mobility was observed in GaAs, and is exploited in high electron mobility transistors (HEMTs) or modulation-doped field effect transistors (MODFETs).

Effects of Velocity Saturation on the I-V Characteristic

For this derivation, a simple two-piece linear approximation for the electron velocity is used:

where is the electric field required for velocity saturation, and is the saturation limited thermal velocity.

Recall: in the linear region, the I-V characteristic can be given by:

where

The saturation current can now be found by assuming that the current saturation occurs when the electric field at the drain side of the channel exceeds the critical field

required for velocity saturation. This is a much more realistic assumption than the Shockley model, which assumes

saturation occurs when The constant mobility model is still used for drain voltages below the saturation voltage. The absolute value of the electric field in the channel at drain

voltages below the saturation voltage can be obtained from Eq.(5.21):

Integrating Eq.(5.35) from 0 to x, the following equation for the channel potential is obtained for drain voltages below the saturation voltage:

The solution of this equation is given by

Substituting Eq.(5.37) into Eq.(5.35), the following expression for the electric field as a function of distance is obtained:

and the electric field F(L) at the drain side of the channel (where it is the largest),

From the condition the drain saturation current can now be found as

At very large values of the term in the brackets in Eq.(5.40) may be expanded into Taylor series, which gives the following expression for the saturation drain

current for long channel devices: , which does not take into account the velocity saturation effects.

For long channel devices, as predicted by the constant mobility model, hence, the velocity saturation effects are not too important for long channel devices.

Example: assume then for channel length velocity saturation effects on the drain saturation current may be neglected.

However, for modern day MOSFETs, the typical gate length is much smaller than (recently, Intel has introduced processors using technology), where the velocity saturation effects are extremely important.

In the limiting case for short channel devices, when from Eqs.(5.40)

and (5.41), it is seen that

Note: for short channel device, the drain saturation current is times smaller than the value predicted by the constant mobility model; and it becomes linearly dependent on

instead of the familiar square law relation.

while plotted as a function of for a long channel device, shows a linear behavior; however, for short channel devices, it shows a significant departure from linearity a measure of whether the device is a short-channel or a long-channel device.

The drain saturation voltage is also much smaller than that predicted by the constant mobility model.

Fig.5.14 The variation of the drain saturation current as a function of the gate length for three different values of the gate voltage (3 V, 5 V, and 7 V). The drain saturation current predicted by the constant mobility model (shown by the dashed line) is also shown for comparison.

The effects of source/drain series resistance, for these cases, can be accounted for (as done earlier for long channel devices), and the following expressions for the drain saturation current and the drain saturation voltage are obtained:

Interpolated Relation

The following interpolation formula for the MOSFET I-V characteristic has been proposed by Shur, which describes both limiting cases

correctly:

This was one of the earlier formulas, and a huge amount of work has been done in this area for the last ten years or so, in order to further refine the description of the behavior of short-channel MOSFETs.

In practical devices, the I-V characteristics do not completely saturate at large drain-to-source voltages, and this is related to the short channel and other nonideal effects in MOSFETs.

In order to account for the finite slope of the output characteristics in saturation, the following modification to the drain current expression has been proposed:

where is referred to as the channel-length modulation parameter (an extremely important parameter for short channel device a measure of the nonidealities present in the device)

Short Channel and Nonideal Effects in MOSFETs

For long channel devices, the drain current becomes constant in saturation, whereas, for short channel devices, the drain current increases continuously with the drain-to-source voltage.

Fig.5.15 I-V characteristics of two n-channel MOSFETs: (i) L = 0.5 (dashed lines),

and (ii) L = 0.75 (solid lines).

Fig.5.16 The variation of the threshold voltage with the effective channel length.

Another interesting feature seen in short channel devices is that the saturation current increases as the device length is reduced.

Now, based on the existing model for the threshold voltage, which states that it is independent of the device length this behavior cannot be explained.

In reality, it has been shown that the threshold voltage is a strong function of the channel length (for short channel devices), and it actually decreases with a decrease in the channel length, which explains the reason behind the larger saturation current.

The Charge Sharing Model

The reduction of the threshold voltage with a reduction in the channel length can be explained by the charge sharing model.

Fig.5.17 The depletion charge profiles for (a) a long channel device, and (b) a short channel device.

For a long channel device, the depletion layer thickness at the source end of the channel and at the drain end of the channel are much less than the channel length L, and, thus, the depletion charge enclosed by these sections are much smaller than the total depletion charge under the gate.

However, for a short channel device, the widths of these depletion regions are a non-negligible fraction of the total depletion charge under the gate.

Note: essentially, the depletion regions near the source and the drain are contributed by the source-substrate and the drain-substrate bias, and gate has no role to play.

Under an applied drain-source bias, the depletion region thickness near the drain will obviously be larger than that at the source side.

The net effect is that the gate now has to compensate for a lower depletion charge density than that for a long channel device, which qualitatively explains the reduction of the threshold voltage with a reduction in the channel length.

The exact analysis of the charge sharing effects requires a two-dimensional analysis, however, to the first order, it is assumed that the effect of the depletion width at the drain side of the channel is to reduce the effective channel length in the saturation region

from L to where

Here, is the effective channel length, and the voltage dropped along this section is assumed to be equal to the drain saturation voltage , and is length of the pinched-off portion of the channel (related to the drain depletion width), where the excess drain voltage beyond , i.e., is dropped, where is the applied drain voltage.

With an increase in the length of the pinch-off region also increases, leading to a

reduction in the effective channel length . This effect is called the channel length modulation effect, and this effect leads to a higher

drain saturation current, and finite output conductance in the saturation region. A very crude estimate of the pinch-off length (also referred to as the drain region

length) can be obtained from the solution of the one-dimensional Poisson's equation:

A more accurate and realistic expression for may be obtained by assuming that the electrons are injected from the inversion layer into the drain depletion region, and they spread uniformly, leading to the current density

Here, is the diffusion depth of the drain region, and is the thickness of the

inversion layer It is also assumed that the velocity of electrons in this region is saturated, thus their

volume density can be given by Now, the one-dimensional Poisson's equation can be rewritten as:

The solution of this equation leads to the following complicated expression for :

For gate lengths larger than or about 1 , and drain-to-source voltages smaller than or about 10 V, this expression may be simplified to give

In short channel devices, the depletion charge under the channel [dependent on the channel potential and has been represented by the second term within the brackets in the right-hand side of Eq.(5.7)], which has been neglected in the charge control model [Eq.(5.19)], has to be accounted for.

This effect may be taken into account by introducing an additional parameter a into the equations of the charge control model, with the resulting equations given by

Linear Region

Saturation Region

For Si, the (empirical and fitting) parameter a describes the influence of the bulk substrate depletion layer on the device characteristics, and can be approximated by the following expression

The threshold voltage and the parameter K can be determined from the experimentally measured data for a given device.

In addition, the dependence of electron mobility on the longitudinal and transverse electric field in the channel should be included for a more realistic device modeling, however, this simple empirical model gives adequately good fit with the measured data.

Fig.5.18 The measured and calculated I-V characteristics for a Si n-channel MOSFET.

Similar to the short channel device, the threshold voltage of a narrow channel (along the width) device increases with a reduction in the effective device width Weff due to the fringing fields outside the gate region, and the change in the threshold voltage as a function of Weff can be given by

where is a constant.

Fig.5.19 Variation of the threshold voltage with the channel width.

Another non-ideal effect that may be especially important for short-channel devices is the injection of electrons from the channel directly to the gate dielectric, where these electrons get trapped => hot electron effect.

This phenomenon takes place because the carriers gain sufficient energy while traversing the drain depletion region, which contains a high electric field, and has been used to advantage in the FAMOS (Floating gate avalanche MOS) structures used in memories.

Avalanche breakdown of the drain-substrate junction can cause a sharp increase in the drain current, and can damage the device unless it is controlled by some external means.

Typically, avalanche breakdown for a heavily doped drain-moderately doped substrate junction takes place at approximately 8 to 10 V.

Another very important nonideal and potentially hazardous situation may arise due to punchthrough, where the drain and source depletion regions touch each other and cause abnormally large current to flow through the device: this effect is particularly severe for short channel devices.

Punchthrough effect creates a superlinear increase in the drain current with the drain voltage, even at gate voltages below the threshold voltage.

Subthreshold Conduction

So far, we have considered current flow in a MOSFET only when the gate voltage exceeds the threshold voltage.

However, in reality, a finite (nonzero) current does flow in a MOSFET even for gate voltages below the threshold voltage, and this effect is more marked for short channel length devices than their long channel counterparts.

This current is referred to as the subthreshold current, and it flows for when the surface potential lies between the ranges of the onset of weak inversion and the onset of strong inversion.

The mechanism responsible for subthreshold current is quite different for long-channel and short-channel devices. 5.6.1 Subthreshold Current in a Long Channel Device

In a long channel device, the situation is similar to a BJT, where the source plays the role of the emitter, the drain is equivalent to the collector, and the substrate is the base.

The drain voltage drops almost entirely across the drain-substrate depletion region. Thus, the component of the electric field parallel to the interface is small, and the

subthreshold current is contributed primarily by diffusion, just as the case for BJTs.

Fig.5.20 The depletion regions associated with a (a) long channel and (b) short channel device.

Thus, the subthreshold current can be evaluated as

where is the region where most electrons are located) is the effective cross-sectional area.

The electron density n at the surface is proportional to , and it decreases with y

(perpendicular to the interface) proportionally to

where is the vertical electric field, given by

Thus, the effective depth where most of the electrons are concentrated, can be

estimated as where y = 0 corresponds to the interface. If the diffusion length of electrons in the substrate is much greater than the channel

length L, then the electron density n should be a linear function of x, decreasing from the source towards the drain (just like the linear distribution of minority carriers in the base of a BJT):

where the volume concentrations for electrons at the source and the drain sides of the channel are given by

where V(y) is the potential given by is the length of the undepleted portion of the channel.

For long channel devices, it is assumed that the depletion widths at the source and the

drain sides of the channel are small compared to the channel length L, and Also, note that since Using all the relations given above, the subthreshold current for a long channel MOSFET

can be given by

The surface potential at the source can be expressed as a function of the gate voltage

by noting that thus,

where

Note: For the subthreshold current becomes independent of the drain voltage. This is expected since in a long channel device, most of the applied drain voltage drops at

the drain-substrate depletion region, and since the current is diffusive in nature, there is no change in the current with the drain voltage.

Also, for large since the gradient of n is not affected by the drain voltage: a situation similar to BJTs, where the collector current in the forward active mode is independent of the collector-to-emitter voltage.

Note: the subthreshold current is almost independent of the drain voltage The substrate bias shifts the threshold voltage to a more positive value, affects the surface

potential, and thus the subthreshold current changes.

Fig.5.21 The subthreshold characteristics for a long channel device as a function of the gate voltage for different values of drain and substrate voltages.

Subthreshold Current in a Short Channel Device

In a short channel device, the source and drain depletion widths may be a significant portion of the channel length L, and, hence, can not be neglected.

To account for this effect, the term L in Eq.(5.67) is replaced by another term Leff, where where

where is the built-in voltage of the source/drain-substrate junction, and the surface potential is now found from the solution of the following equation:

where

 

The curves clearly show shifts in the subthreshold current for different values of drain voltages, a characteristic typical of short channel devices.

The subthreshold current is a strong function of temperature as well

Fig.5.22 The subthreshold characteristics for a short channel device as a function of gate voltage for different values of drain and substrate voltages.

Fig.5.23 The subthreshold characteristics as a function of gate voltage for two different temperatures (77 K and 300 K).

MOSFET Capacitances and Equivalent Circuit

Note: in a MOSFET, the charges in the depletion region and the inversion layer depend on the gate, source, drain, and substrate potentials; and the derivatives of these charges with respect to the terminal voltages give rise to MOSFET capacitances.

The small signal equivalent circuit shown in Fig.5.24 is the one used by the popular circuit simulation package called SPICE, and it contains:

the drain-to-source current source IDS, two resistances (due to the quasi-neutral region resistances of the source and

drain respectively)

The gate-to-drain capacitance

The gate-to-body capacitance

The source-to-substrate capacitance

The drain-to-substrate capacitance

 

Note: in the presence of series source/drain resistances the intrinsic (internal to the device) conductance and transconductances are related to the

extrinsic (measured) transconductances and conductance by the following equation:

EXAMPLE 5.3: An n-channel MOSFET has

Determine

SOLUTION: The intrinsic body transconductance

The coefficient

Therefore, and respectively. Thus, significant

degradation in the transconductances and drain conductance may take place for large values of source/drain series resistances.

The two conductance terms appearing in the equivalent circuit shown in Fig.5.26(a) are the reverse-bias conductances of the source-substrate and drain-substrate diodes, and their values are very small (tending to zero).

Fig.5.26(b) The simplified equivalent circuit of a MOSFET.

A simplified equivalent circuit is shown in Fig.5.26(b). For the circuit shown in Fig.5.26(b), the small signal voltage gain expression can be

given by:

Note: at low frequencies, when the effects of the capacitances can be neglected, the voltage gain can be given by as expected.

Another simplified equivalent circuit, suitable for the calculation of the current gain, is shown in Fig.5.26(c).

Fig.5.26(c) The alternate simplified equivalent circuit for a MOSFET suitable for the calculation of the short circuit current gain.

From Fig.5.26(c), the short circuit current gain can be easily found to be:

Thus, the unity gain cutoff frequency (i.e., the frequency at which the absolute value of

the short circuit current gain is equal to unity) can be given by

where

Now, note that in the strong inversion region. Also, the drain current

Thus, Hence,

where is the transit time of electrons in the channel.

This equation gives the theoretical maximum value for Assuming the characteristic switching time for a MOSFET is obtained

as

In reality, the measured switching times for MOSFETs are at least several times larger than that predicted above due to the parasitic and fringing capacitances that has to be

added to the gate capacitance leading to the following modified expression for :

EXAMPLE 5.4: Calculate the unity-gain cutoff frequency for the MOSFET considered in

Example 5.2. Compare this value with theoretical maximum value for , assuming

SOLUTION: The unity-gain cutoff frequency

The theoretical maximum value for = = 7.96 GHz.

An actual device would show a cutoff frequency, which is smaller of the two, thus, the actual unity-gain cutoff for the device considered in Example 5.2 would be 2.82 GHz.

Types of MOSFETs

Broadly, MOSFETs can be categorized into two types: enhancement and depletion.

Enhancement type devices are normally off, i.e., channel does not exist for and

the applied must be greater than for the device to turn on. On the other hand, depletion type devices are normally on, i.e., channel does exist even

for and the applied must be reduced below for the device to turn off.

To put it simply, an n-channel enhancement type device has a positive , whereas an n-

channel depletion type device has a negative .

Similarly, a p-channel enhancement type device has a negative , whereas a p-channel

depletion type device has a positive . The threshold voltage can be changed either by doping or by ion implantation, where

high energy ions are made to bombard the surface and get embedded into it: since these are charged, they can change the charge state of the surface, and, hence, the threshold voltage.

The shift in the threshold voltage is related to the ion density by the relation:

eg., negative ions (like Boron) implanted in a p-channel (n-substrate) device will compensate some of the positive depletion charges and make the threshold voltage less negative, however, note the same ions would shift the threshold voltage to more positive for n-channel (p-substrate) device.

EXAMPLE 5.5: An n-channel MOSFET with has a threshold voltage Determine the type and dose of ion implantation required to make it a depletion

mode device with

SOLUTION: The oxide capacitance per unit area

The dose of ion implantation required

Since the threshold voltage is shifting towards negative value, hence, obviously, the type of implant required is positive ions (e.g., P, As, Sb, etc.), which would compensate the negative depletion charge of the substrate and push the threshold voltage towards negative direction.

Some Advanced Models

Unified Charge Control Model for MOSFETs

For MOSFETs, the UCCM equation for MIS capacitors [Eq.(4.24)] has to be modified to account for the channel potential, thus, the inversion charge is related to the gate-source and channel potential as follows:

where is the quasi-Fermi (electrochemical) potential measured relative to the Fermi potential at the source side of the channel, and the parameter accounts for the dependence of the threshold voltage on the channel potential in strong inversion, and, hence, on the position along the channel.

In order to get a better understanding of the term first consider the simplified version of

the charge control model, given by

Now, in reality, the threshold voltage depends on the depletion charge. Taking into account the dependence of this charge on the channel potential, one can write

the corresponding position dependent threshold voltage as

This makes the charge control equation nonlinear and difficult to use in device modeling.

However, if Eq.(5.90) is linearized with respect to V, one can write where now is the value of the threshold voltage at the source side of the channel.

Thus, one obtains A generalized solution for ns is used in UCCM, given by

This equation allows the direct determination of the carrier distribution along the channel

as a function of

Saturation Region: The Region of the Channel with Velocity Saturation

Of late, area of considerable interest, since an accurate modeling of the pinch-off region is essential in order to obtain an exact drain current model in saturation.

Important to find a solution for the longitudinal field in the channel. The model relies on the fundamental assumption that the carrier velocity in the saturated

part of the channel is constant and equal to the saturation velocity, which implies that the carrier sheet density in the saturated part of the channel is also constant.

Another assumption made is that the substrate is lowly doped: this assumption oversimplifies the true physics of the saturation region, however, it also leads to a manageable theory with qualitatively correct features, which gives a fairly good fit to experimental data with a judicious choice of parameters such as the saturation velocity and the effective channel thickness.

The intrinsic saturation voltage can be defined as the intrinsic drain-source voltage for which the longitudinal electric field at the drain end of the channel just becomes

equal to the saturation field

For the location in the channel where marks the boundary between the saturated and the non-saturated regions.

The boundary point moves towards the source with increasing drain-source voltage: this effect is called the channel length modulation.

Another important parameter is the channel potential at the boundary point

The two parameters and on the intrinsic gate-source voltage and have to be determined self-consistently using the models for the two regions with the

requirement that the potential, the electric field, and the velocity be continuous at For a description of the saturated region, it is necessary to consider a two-dimensional

Poisson's equation of the form