mos-ak group spring'05, strasbourgapril 8, 2005 b. diagne, f. prégaldiny, f. krummenacher, f....

MOS-AK Group Spring'05, StrasbourgApril 8, 2005

B. Diagne, F. Prégaldiny, F. Krummenacher,F. Pêcheux, J.-M. Sallese and C. Lallement

InESS / EPFL / LIP6

Design Oriented Model for Design Oriented Model for

Symmetric DG MOSFETSymmetric DG MOSFET

2 MOS-AK Group Spring'05, StrasbourgApril 8, 2005

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Scaling limits in BULK MOSFET

The Double-Gate (DG) MOSFET

Compact model for symmetric DG MOSFET

Model validation vs. 2D simulations

Model implementation in VHDL-AMS

Conclusion


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Conclusion


Scaling limits of BULK MOSFETScaling limits of BULK MOSFET

Limit for supply voltage (<0.6V)

Limit for further scaling of tox (<2nm)

Minimum channel length Lg=50nm

Discrete dopant fluctuations

Dramatic short-channels effects (SCE)


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Conclusion


How can we follow Moore’s lawHow can we follow Moore’s law ??

By moving to DG MOSFETs

DG might be the unique viable alternative to build nano MOSFETs when Lg<50nm

Because:

- Better control of the channel from the gates

- Reduced short-channel effects

- Better Ion/Ioff

- Improved sub-threshold slope (60mV/decade)

- No discrete dopant fluctuations


DG MOSFET structureDG MOSFET structure


Typical values for DG MOSFETTypical values for DG MOSFET

tox=1nm – tsi=10nm – Lg=25nm

Is the behavior still “classical” ?

Can we still use 3D DOS, drift-diffusion approach, surface potential concept ?

Yes and No…


Electrostatic considerationsElectrostatic considerations

Depending on tsi , 2D discrete levels cannot be ignored … in principle.

For very thin films (<5nm), 2D states are so confined that electrostatic correction can be ignored (FD-Baccarani).

For relatively thick films, 2D levels can be ignored, reverting to the more classical

description (3D+Boltz.-Taur).

For intermediate thicknesses, 2D states should be coupled to electrostatic (Ge &

Fossum).


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Conclusion


Model: Taur’s approachModel: Taur’s approach [1][1]

3D but with volume inversion

No more charge sheet approximation concept

Analytical solution of charges and current

However,

not a truly analytical model (iteration needed)

NO ANALYTICAL solution for Vds ≠ 0 … hence no solution for transcapacitances

[1] Y. Taur, X. Liang, W. Wang and H. Lu, IEEE Electron Device Letters, vol. 25, no. 2, pp. 107-109, 2004.


In the original approach, the mobile charges are evaluated through complex functions

No insight into “electrical” quantities…

For instance, the drain current is given by

2 22 2si si

ox

24 tan tan

2

S

D

oxD

si si

TW kTI

L T q T


Our new approachOur new approach

An EKV-like formulation [2] !

Normalization of charges and current as in EKV… but we have 2 gates:

0 4 ox TQ C U 24 /s ox TI C U W L

int 0/i siq e n t Q

[2] J.-M. Sallese, F. Krummenacher, F. Prégaldiny, C. Lallement, A. Roy and C. Enz, “A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism”, Solid-State Electronics, vol. 49, pp. 485-489, 2005.



Mobile charge density vs. potentials

And we still use the drift-diffusion concept

For tsi »1nm, we get the EKV relations(very interesting for the transcapacitances…)



Formulation of DG reverts to the classicalcharge sheet approximation for bulk and SOI MOSFETs

This implies that the transcapacitances can be obtained in the same way as in bulk MOSFETs [3]

In addition, the new model accurately describes important central characteristics such as gm /Id

[3] F. Prégaldiny, F. Krummenacher, D. Birahim, F. Pêcheux, J.-M. Sallese and C. Lallement, “A fully analytical compact model for symmetric DG MOSFETs”, submitted to ESSDERC.


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Conclusion


The 2D simulationsThe 2D simulations

Structures developed under Atlas (Silvaco)

tox=2nm – tsi=550nm – Lg=Wg=1µm


Model vs. exact Taur’s formulationModel vs. exact Taur’s formulation

Normalized inversion charge density as a function of Vgs

Symbols: Taur’s model ; lines: our analytical model


Model vs. 2D simulationsModel vs. 2D simulations

Drain current Ids as a function of Vgs at different Vds

Symbols: 2D results ; lines: our analytical model



Drain current Ids as a function of Vgs at different tsi



Transcapacitances as a function of Vgs at different Vds

Symbols: 2D results ; lines: our analytical model


The The ggmm //IIdd concept in DG MOSFETconcept in DG MOSFET

0

0.2

0.4

0.6

0.8

1

0.001 0.01 0.1 1 10 100 1000Normalized current

Tox

=2 nm

saturation

TSI

=50nm

TSI

=20nm

TSI

=5nm

bulk MOSFET

TSI

=200nm

TSI

=1 m

J.-M. Sallese, F. Krummenacher, F. Prégaldiny, C. Lallement, A. Roy and C. Enz, “A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism”, Solid-State Electronics, vol. 49, pp. 485-489, 2005.


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Conclusion


VHDL-AMS code: the VHDL-AMS code: the structurestructure

ENTITY mos_dg IS

generic (L:real:=1.0e-6; -- Gate length… / ...

port (terminal D,G1,G2,S:electrical);

end;

ARCHITECTURE equ OF mos_dg IS

. . .

BEGIN-- Drain current of the SOI DG MOSFET

ids == . . . qqi(Vg1n,Vsn)**2 . . . + . . qqi(Vg1n,Vdn)**2 ;-- Capacitances

Cgg == . . . ; . . . ; END;

-- Function definition (qqi)

pure function qqi(Vg1n,V:real) return real is … / ... end ;

ENTITY: parameters, terminals,...

ARCHITECTURE: charges, current and capacitances calculations

The structure


VHDL-AMS code: the VHDL-AMS code: the entityentity

library ieee;use disciplines.electromagnetic_system.all;use ieee.math_real.all;

ENTITY mos_dg IS

generic (W :real :=1.0e-6; -- Gate width

L :real :=1.0e-6; -- Gate length

tox1 :real :=2.0e-9; -- Gate 1 oxide thickness

tox2 :real :=2.0e-9; -- Gate 2 oxide thickness

tsi :real :=25e-9; -- Silicon film thickness

mu0 :real :=0.1; -- Low-field mobility

port (terminal D,G1,G2,S:electrical);

end;

d

g1 g2

s


VHDL-AMS code: the VHDL-AMS code: the function function qqiqqi

-- Function definition

pure function qqi(Vg1n,V:real) return real is variable alpha, delta, …, vt, vto, q0, . . . . :real;

- Precomputed parameters alpha := . . . ; -- Form factor vt := . . . ; vto := . . . .; -- Threshold voltage

begin if ((vg1n – vto – v) > vt) then . . . . . return –q0*(1.0+delta+(1.0 + 0.1*delta));

else . . . return –q0*(1.0+delta+(1.0 + 0.48*delta)); end if;

END ;

Definition of the function

To determine the normalized charge for both source and drain sides

Computed with no iteration !


VHDL-AMS code: the VHDL-AMS code: the architecturearchitecture ARCHITECTURE equ OF mos_dg IS

. . .quantity vg1n, vg2n, vsn, vdn :real;quantity Inf, Inr, Xf, Xr :real;quantity Csg, Cdg, Cds, Csd, Cgd, Cgs, Css, Cdd, Cgg :real;. . .

quantity Vd across D to electrical_ground; quantity Vg1 across S to electrical_ground; quantity Vg1 across G1 to electrical_ground;

quantity Vg2 across G2 to electrical_ground; quantity Ids through D to S;

. . .

-- Function definition pure function qqi(Vg1n,V:real) return real is

. . .

BEGIN-- Normalized voltages

vg1n == Vg1/UT; vg2n == Vg2/UT; vsn == Vsn/UT; vdn == Vg1/UT;

-- Drain current of the SOI DG MOSFET

ids == IDO*(-4.0*qqi(vg1n, vdn)**2.0 + 4.0* qqi(vg1n, vsn)**2.0 + …);

-- Capacitances Inf == … ; Inr == … ; Xr == … ; Xf == … ; Csg == … ; Cdg == … ; … / … ;

END;


Simulation resultsSimulation resultsperformed with performed with

the AMS software 4.0.2.1 from Mentor Graphicsthe AMS software 4.0.2.1 from Mentor Graphics

IDS(VGS) at VDS = 0.25, 0.5, 0.75, 1V

IDS

VGS


Simulation resultsSimulation resultsIDS(VDS) at VGS = 0.5, 0.75, 1V

IDS

VDS


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Conclusion


ConclusionConclusion

Undoped DG MOSFETs are promising candidatesfor ultra deep-submicron VLSI technology

The 2D simulations of different DG MOSFET structures have been carried out

A truly analytical compact model has been developed

All quantities in the model are expressed in terms of normalized variables helpful for developing efficient design methodologies

This long-channel core model would need to be augmented with second-order effects (mobility reduction, SCE, quantum effects…)

mos-ak group spring'05, strasbourgapril 8, 2005 b. diagne, f. prégaldiny, f. krummenacher, f....

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