monolithic pixel detectors in a deep submicron soi process, tipp, tsukuba, japan 11-17 march 2009 1...

Monolithic Pixel Detectors in a Deep Submicron SOI Process, TIPP, Tsukuba, Japan 11-17 March 2009

1email: [email protected]

Discussion of process features to target optimum monolithic SOI Pixel Detectors

Grzegorz DEPTUCH

Fermi National Accelerator Laboratory, Batavia, IL, USA

OUTLINE:

1) objectives of optimization,

2) conclusions from previous work,

3) Design details of pixel imaging detector „MAMBO”,

4) Achievements, observations and investigations,

5) Conclusions on current status of the technology,

6) Discussion around necessary changes to the process,

7) Conclusions.


2

Fabrication of detecting layer and electronics in Fabrication of detecting layer and electronics in

the same fabrication flow requires investigating the same fabrication flow requires investigating

potential improvements from different angles:potential improvements from different angles:

ObjectivesObjectives

Optimization of the SOI electronics for designs of

readout circuits with dominant presence of analog functions

Optimization of detector – grade handle wafer for carrier lifetime and charge transport properties

Cohesion of the detector layer and

the electronics, minimisation of

mutual detrimental coupling


3

Summary and conclusions from pre-SOPIX worksSummary and conclusions from pre-SOPIX works

F. Pengg, „Monolithic Silicon Pixel Detectors in SOI Technology”, CERN/ECP, RD19 collaboration, January 1996, Ph.D. thesis

work related to detection of ionizing radiationwork related to detection of ionizing radiation

J. Marczewski, et al., „Technology development for SOI monolithic detectors”, Nucl. Instr. and Meth. A, 560, 2006, 26-30

•Need for careful shileding between the SOI electronics and the detector underneath the BOX ()•Thick SOI (quasi-bulk process for optimum analog performance)

GOOD in CONCEPTS but NOT SUCCESSFUL – BECAUSE OF LACK OF SUFFICIENTLY ADVANCED

TECHNOLOGY

Coupling issue recognized!!!

Nested buried wells proposed!!!

Thick SOI layer


4

Summary and conclusions from pre-SOPIX worksSummary and conclusions from pre-SOPIX works

work related to visible light imagingwork related to visible light imaging

B.Pain, Ch.Sun, X.Zheng, S.Seshadri, T.J. Cunningham, „SOI-based Monolithic Imaging Technology for Scientific Applications”,2007 international image sensors workshop, June 6-10, 2007 Ogunquit, ME

W.Zhang; M.Chan; H.Wang; Ko, P.K.;,” Building hybrid active pixels for CMOS imager on SOI substrate”, SOI Conference, 1999. Proceedings. 1999 IEEE International,1999 , 102 - 103

X.Zheng, C.Wrigley, G.Yang, B.Pain;, ” High responsivity CMOS imager pixel implemented in SOI technology”, SOI Conference, 2000 IEEE International2000, 138 - 139

Pinning layer

implanted!!!

No attention to coupling

Excluded from sensitivity

Path

of e

volu

tion


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Implementation of buried P-well in current OKI processImplementation of buried P-well in current OKI process

n- -type

• BPW is helpful in maintaining constant potential under any circuitry that is placed at the periphery of the matrix of pixels. • The potential control underneath the BOX may be achieved by designing a closely spaced matrix of PSUB contacts. It was shown that this works relatively well on the fabricated circuits (the cost is a penalty of some are lost for multiple PSUB contacts).

• BPW is not providing any benefit for protection against charging of the BOX layer as a result of accumulation ionizing doses of the incident radiation. The circuitry is exposed directly to the modulation of conduction resulted from the charged oxide of the BOX.


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Review of role of BPW layerReview of role of BPW layer

Generally electric field in the p-on-n detector is not uniform in case of very

small p-type implant separated by large lateral distance

Potential pockets can be created with no electric field – thus no charge collectio

from some regions

The distribution of electric field can be improved by increasing effective sizes of

implants using BPW islandsSmaller distances between BPW islands may lead to shorts, especially if some residual p-type effective „doping” occurs underneath

the BOX


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Extension of effective size of diodes achieved by adding BPW over PSUB is not bringing any good inside pixels,

direct coupling paths sending all transient interferences to the input of an in-pixel amplifier, additionally multiple

feedback path are created taht may lead to instability of the processing chain


8


9

2 3 4 5 6 7 80

200

400

600

800

1000

1200

1400

pixel 5/6

(fully enclosed)

0..0.8V 1..1.8V

ind

uce

d e

q. e

lect

ron

s

Vback [V]

Depleted

No

t d

eple

ted

Yet

!!!

(as depletion grows into depth

capacitive coupling saturates)

• A

Ccoup=0.3 fF

2 3 4 5 6 7 80

200

400

600

800

1000

1200

1400

pixel 5/6

(fully enclosed)

0..0.8V 1..1.8V

ind

uce

d e

q. e

lect

ron

s

Vback [V]

Depleted

No

t d

eple

ted

Yet

!!!

(as depletion grows into depth

capacitive coupling saturates)

• A

Ccoup=0.3 fF

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.60

500

1000

1500

2000

2500

3000

indu

ced

eq.

ele

ctro

ns

U [V]

Equation y = a + b*x

Weight No Weighting

Adj. R-Square0.99998 Value Standard Error

J Intercept -43.71429 2.25921

J Slope 1883.14286 2.4848

pixel 5/5 (fully enclosed)

VB=6.5V

eq. coupling C = 0.3fF



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This is not BPW, but contamination that may

change effective conduction type to p type directly

underneath BOX

Generally electric field in the p-on-n detector is not uniform in case of very

small p-type implant separated by large lateral distance

Potential pockets can be created with no electric field – thus no charge collectio

from some regions

The distribution of electric field can be improved by increasing effective sizes of

implants using BPW islandsSmaller distances between BPW islands may lead to shorts, especially if some residual p-type effective „doping” occurs underneath

the BOX


11

Design details of pixel imaging detector „MAMBO”Design details of pixel imaging detector „MAMBO”


12

Achievements, observations and investigationsAchievements, observations and investigations

Transistor with floating body was used (poor precision SPICE models

gave wrong value of gds) –

later measurements showed very small equiv. resistance

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PMOS biased at PMOS biased at

VVGSGS=const as a feedback =const as a feedback

resistor (50 Mresistor (50 M))

0.15 m

0.20 m

shaper design in MAMBO II used shaper design in MAMBO II used

longer L & half-H-Gate design for longer L & half-H-Gate design for

feedback transitor (feedback transitor (SBCSBC))

As a result, required values of feedback

resistor were obtained.

Empirical approach is needed to compensate

for insufficient device modeling

W/L=0.63u/0.3u

MAMBO IMAMBO II

MAMBO I single pixel testMAMBO I single pixel test


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Achievements, observations and investigationsAchievements, observations and investigations MAMBO II single pixel testMAMBO II single pixel test


19


M. Connell, et all. Impact of Mobile Charge on Matching Sensitivity inSOI Analog Circuits, 2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference


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21



22



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Conclusions on current status of the technologyConclusions on current status of the technology

M. Connell, et all. Impact of Mobile Charge on Matching Sensitivity inSOI Analog Circuits, 2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference


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Discussion around necessary changes to the processDiscussion around necessary changes to the process minimum:minimum:

CURRENT VIEW

INCREASE THICKNESS OF BOX

this is only partial improvement!

ttBOXBOX=200nm, t=200nm, tGOXGOX=4.5nm, wide oxide areas favors positive charge trapping, =4.5nm, wide oxide areas favors positive charge trapping,

threshold voltage shifts, ions flows and transistors shows poor behavior threshold voltage shifts, ions flows and transistors shows poor behavior

Isolation of vertical contacts achieved naturaly as contact openings are etched in oxide

all is the same but bottom gate action all is the same but bottom gate action

is dcreased proportionally to tis dcreased proportionally to tBOXBOX

increase of tBOX may affect metrology on the production line

It is not believed that only only increase of tBOX will be enough


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real improvement (suggestion for minimum process complication) real improvement (suggestion for minimum process complication) shift from shift from

FD-SFD-SooI to quasiI to quasi--bulk-Sbulk-SooI – this is necessary!!!I – this is necessary!!!

Discussion around necessary changes to the processDiscussion around necessary changes to the process

I step: Grow epitaxial silicon on UNIBOND wafers from SOITEC

II step: blanket implantation of p-type film and n-type film island

The grown layer will be used for the substrate for transistors, no isolation of transistor islands!! to achieve screening

III step: cuts of contact holes, S/D implants, cuts of STI

Important is that p-type film is left around cuts, it is fully enclosed by n-film for self centering


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real improvment (prepared in such way that minimum modificatio)real improvment (prepared in such way that minimum modificatio)


After this step all processing is the same as it was for the original OKI-SOI process!

IV step: fill with oxide and planarization

P-type film areas left around opening will be left floating. After etching opening for S/D, poly-gate and diode openings there will not be needed to passivate walls with exposed p-type Silicon with oxide

Islands hosting pmos transistors will be AC-grounded

- It is wise to stay with n-type detector silicon - Transistors will be closer to bulk devices (advantage is that the continuous film will be AC-grounded, but each n and p type island will be fully isolated


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V step: etch contact opening and fill

Eacthing of contact opening is self centered, the fill material will be in contact wit p-type material but the opposite side of the diode will be grounded

- The contact between the fill metal and the floating p-type material will result in some extra capacitance, however it should not be meanigful for amplifiers based on the virtual ground principle – as it is the optimum implementation for the readout circuitry!


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ConclusionsConclusions The SOIPIX collaboration formed around KEK is a opportunity to explore new 0.15 The SOIPIX collaboration formed around KEK is a opportunity to explore new 0.15 m m

1P/5M and 0.20 1P/5M and 0.20 m 1P/4M FDSm 1P/4M FDSooI CMOS processes by OKI altered to allow charge collection I CMOS processes by OKI altered to allow charge collection

from H-R substratefrom H-R substrate,,

Within two available runs, we managed to obtain working design of the continuous time Within two available runs, we managed to obtain working design of the continuous time

pixel circuit,pixel circuit,

We have problems with counters switchable to shift registers for outputing the data; We have problems with counters switchable to shift registers for outputing the data;

problem is understood and could be avoided if parasitics extraction was available, problem is understood and could be avoided if parasitics extraction was available,

Effort spent on extensive tests led to conclusion on unavoidable deeper adaptations of the Effort spent on extensive tests led to conclusion on unavoidable deeper adaptations of the

process to make it suitable for monolithic detectors, process to make it suitable for monolithic detectors,

Guidance for the optimum process has been Guidance for the optimum process has been

drawn; can it be introduced by the foundry? drawn; can it be introduced by the foundry?

Our experience with 3D-IC using 0.18 Our experience with 3D-IC using 0.18 m FDSoI m FDSoI

process by MIT-LL and discussions with experts process by MIT-LL and discussions with experts

suggests excluding the use of FD-SoIsuggests excluding the use of FD-SoI for designs for designs

with analog, with analog,

more runs more runs and more efficient communication and more efficient communication

are needed to forge the design – dominant part of are needed to forge the design – dominant part of

learning occurs throughlearning occurs through experimenting (modeling experimenting (modeling

required), required),

monolithic pixel detectors in a deep submicron soi process, tipp, tsukuba, japan 11-17 march 2009 1...

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