monolithic 3-d integration of sram and image sensor using two layers of single-grain silicon

3954 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 11, NOVEMBER 2011

Monolithic 3-D Integration of SRAM and ImageSensor Using Two Layers of Single-Grain Silicon

Jaber Derakhshandeh, Negin Golshani, Ryoichi Ishihara, Mohammad Reza Tajari Mofrad, Michael Robertson,Thomas Morrison, and C. I. M. Beenakker

Abstract—In this paper, we report monolithic integration oftwo single-grain silicon layers for static random access memory(SRAM) and image sensor applications. A 12 × 28 silicon lateralphotodiode array with a 25-µm pixel size prepared on top of athree-transistor readout circuit with individual outputs for everypixel is demonstrated. 6T SRAM cells with two layers of stackedtransistors were prepared to compare the performance and areaof each cell in different configurations.

Index Terms—Excimer laser crystallization, image sensors,monolithic integration, 3-D integrated circuits (3-DICs), 6TSRAM cells.

I. INTRODUCTION

INTERCONNECT delay and manufacturing costs involvedin the lithography process are two important problems

for the downscaling of transistors in ultralarge-scale integra-tion. Three-dimensional ICs are the best solution to continueMoore’s law for the next generation of ICs [1]–[3]. As indicatedin Fig. 1, three approaches have been employed to stack activedevices, including device-, chip-, and wafer-level stacking[1]–[3]. The device-level or monolithic 3-D approach offershigh-density vertical interconnects and lower cost, compared toother methods.

Monolithic 3-D integration has been investigated for severalyears using different approaches such as high-temperature,metal-induced lateral crystallization (MILC), epitaxial-growth,and polysilicon thin-film transistor (TFT) processes [1], [3]–[6]. Each of these processes are either of high temperature(more than 950 ◦C) or only useful in some special applica-tions such as memories, or they result in a low-quality siliconlayer. Hence, for 3-D ICs (3-DICs), a low-temperature process(< 700 ◦C) and a high-quality silicon layer are required. Theµ-Czochralski process is one of the candidates to be used in3-DICs for some possible applications such as artificial retina,high-density and high-speed SRAMs, and high-resolution

Manuscript received March 15, 2011; revised June 2, 2011 and June 29,2011; accepted July 19, 2011. Date of publication September 12, 2011; dateof current version October 21, 2011. This work was supported by the DutchTechnology Foundation STW. The review of this paper was arranged by EditorJ. R. Tower.

J. Derakhshandeh, N. Golshani, R. Ishihara, M. R. Tajari Mofrad, andC. I. M. Beenakker are with the Laboratory of Electronics Components, Tech-nology and Materials, Delft Institute of Microsystems and Nanoelectronics,Faculty of Electrical Engineering, Delft University of Technology, 2628 Delft,The Netherlands (e-mail: [email protected]).

M. Robertson and T. Morrison are with the Department of Physics, AcadiaUniversity, Wolfville, NS B4P 2R6, Canada.

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2011.2163720

Fig. 1. Three approaches for 3-DIC, (right) chip-level, (center) wafer-level,and (left) device-level integration.

Fig. 2. Schematic of the µ-Czochralski process.

image sensors, because it can offer a high-quality Si layer witha low-temperature process [7]–[11].

In the µ-Czochralski process, as shown in Fig. 2, amorphoussilicon is deposited on an oxide layer containing small cavities,in order to initiate crystallization of the amorphous silicon froma seed using an excimer laser illumination [15]. The crystallinegrains are about 7 µm × 7 µm in size, which is large enoughto locate high-performance transistors within the grains. Thefabricated TFTs have mobility values of 600 and 300 cm2/V · sfor n-channel MOS (nMOS) and p-channel MOS (pMOS)transistors, respectively [4]–[8].

With repeating the µ-Czochralski process on several layersand using chemical mechanical polishing in between, it ispossible to realize monolithic 3-D ICs, as depicted in Fig. 3.CMP is a necessary step to avoid any influence and history ofthe previous layer on the following new layers.

0018-9383/$26.00 © 2011 IEEE

DERAKHSHANDEH et al.: MONOLITHIC INTEGRATION OF SRAM USING SINGLE-GRAIN SILICON 3955

Fig. 3. Employing the µ-Czochralski process for 3-DIC.

Fig. 4. Schematic circuit of a 6T SRAM cell.

The µ-Czochralski process is similar to the fully depletedsilicon-on-insulator (SOI) process, which has the advantages ofhigh-speed and low-power consumption for the circuits.

In this paper, we will detail the fabrication process and theperformance of SRAM cells and three-transistor active pixelsensor (3T APS) image sensors using single-grain technologywith two stacked layers.

II. DESIGNING SRAM CELLS AND 3T APS STRUCTURE

SRAM cells and arrays of photodiodes have been designedusing two layers of single-grain silicon transistors with a gatelength of 2 µm. The 6T CMOS SRAM cell is the most popularSRAM cell due to its superior robustness, low-power and low-voltage operation, short access time, high-frequency data rate,radiation hardness, operation in space, high temperature, andnoisy environments [14]. Fig. 4 shows the circuit schematic ofa 6T SRAM cell. It consists of six transistors, with four used intwo cross-coupled inverters as positive feedback and two accesstransistors for reading and writing data inside the cell.

For 6T SRAM cells, different combinations of the placementof the access, driver, and pull-up transistors have been designed,and the specifications of the different layouts are given inTable I. In this table, the area and number of VIAs betweenthe two layers have been compared for different placements.As indicated in this table, when only nMOS transistors are

TABLE IDIFFERENT COMBINATIONS OF ACCESS, DRIVERS, AND PULL-UP

TRANSISTORS FOR 6T SRAM CELLS TO BE PLACED IN TWO LAYERS

Fig. 5. Three-dimensional view of a 6T SRAM cell when the top transistorsare pMOS and the bottom transistors are nMOS.

Fig. 6. The photodiodes on the top layer are connected to the readout circuitin the bottom layer for each pixel.

fabricated on one layer and only pMOS transistors on the otherlayer, there is no mask required for source and drain doping.

This table shows that, when pMOS transistors are located onthe top layer and nMOS transistors are on the bottom layer, thearea is less, and we do not need to use any mask for sourceand drain implantations. The letter F is the smallest technologynode, which is used in the fabrication. Fig. 5 shows a 3-D viewof the two top pMOS transistors and the four nMOS transistorsexisting on the bottom layer.

The image sensor has three transistors on the bottomlayer and three parallel lateral photodiodes on the top layer


Fig. 7. Schematic circuit of an image sensor with a 12 × 28 pixel array and parallel outputs. The photodiodes are on the top layer, and the readout circuit is onthe bottom layer.

Fig. 8. Designed layout of one pixel, consisting of three parallel p-i-nphotodiodes.

constituting one pixel, as illustrated in Fig. 6. This structureis called a three-transistor active pixel sensor (3T APS), whichhas one transistor for resetting the photodiode, one transistor asa source follower for charge amplification, and one transistor toconvert the current to a voltage.

The image sensor was formed in a 12 × 28 pixel array with apixel width of 25 µm. As shown in Fig. 7, the image sensor has acommon reset for all pixels. After resetting the photodiodes, theimage is captured in parallel, and data are ready at the outputs.

The designed layout for one pixel has three parallel p-i-nphotodiodes, as displayed in Fig. 8. The intrinsic region of thelateral p-i-n photodiodes has a size of 2 µm by 6 µm, which islocated inside a single grain of crystalline silicon.

In this figure, the small squares are the locations of the grainfilters where crystallization originates. The intrinsic regionshould be far from the grain boundaries and the grain filter. Weused a minimum distance of 0.5 µm between the grain filter andthe intrinsic area. The big squares are contact holes in order tohave access to the P and N regions of the photodiodes. Using ametal mask, the p+ and n+ pads were connected together.

The APS readout circuit has three transistors placed on thebottom layer directly under the photodiodes. The cathode ofeach photodiode is connected to the APS transistors to convertthe photodiode charge to a voltage.

III. FABRICATION PROCESS

As discussed in the introduction, the µ-Czochralski processwas used to stack two layers of single-grain silicon [7]–[11].The substrate in this process is a p-type 〈100〉 silicon wafer;however, this process can also be applied to the glass substratesince the process temperature is lower than 500 ◦C. In this

Fig. 9. SEM image of crystallized and location-controlled grains.

Fig. 10. Schematic diagram of the fabrication process. After finishing thefirst- and second-layer devices, they were connected by the Al layer.

process, an excimer laser was used to crystallize a 250-nm-thick amorphous silicon film deposited on an oxide layer, whichcontained cavities measuring 1 µm by 1 µm and 750 nm.Amorphous silicon was deposited by means of the low-pressurechemical vapor deposition (LPCVD) process at 550 ◦C since itcan give a conformal layer inside the cavities [7], [15]. The low-temperature deposition process results in amorphous silicon.The amorphous silicon in the deep part of the holes actedas the seed for crystallization, controlling the location of grain.The size of the crystallized grains was about 7 µm × 7 µm,as indicated in Fig. 9.

The fabrication process flow is illustrated in Fig. 10. Aftercrystallization of the silicon and formation of the single-crystal grains, an island mask was applied to define the silicon


Fig. 11. SEM image of the opened holes on the top and bottom layers beforemetallization in the SRAM region.

Fig. 12. SEM image of the lateral p-i-n photodiodes on the top layers.

islands using a dry-etching process. A 30-nm-thick tetraethyl-orthosilicate (TEOS) plasma-enhanced chemical vapor deposi-tion (PECVD) gate oxide was then deposited, followed by a250-nm-thick LPCVD amorphous silicon layer as gate material.The gate mask was used to etch the gate and gate oxide layers.Next, using an nMOS mask, we implanted the source, drain,and gate regions of the transistors with phosphorous using anenergy of 30 KeV and a dose of 5 × 1015 ion/cm2. Similarly,for the PMOS transistors, boron was used as the dopant with animplantation energy of 20 KeV and dose of 5 × 1015 ion/cm2.According to the implantation table inside the silicon, 20-KeVB+ will have a 70-nm projected length, and P+ with 30 KeVhas a 30-nm projected range. These projected lengths areenough to make a good junction inside the 250-nm siliconlayer. Following this step, an excimer laser with an energydensity of 300 mJ/cm2 was used to activate the dopants. Aftercompleting the devices in the first layer of the structure, a

Fig. 13. (a) Cross-sectional BF TEM image of stacked single-grain siliconlayers. (b) and (c) High-magnification images of the first layer. (d) Photodiodeson the top layer after etching the Al from the intrinsic region of photodiodes.The light-sensitive region has been highlighted in the inset.

1.6-µm-thick isolating TEOS layer was deposited. The nextstep was planarization of the surface using CMP. We polisheddown about 550-nm oxide to get rid of any unsmoothed surface[17]. The fabrication process of the second layer was the sameas that of the first layer. We used Al as the gate material for thetop-layer devices, and after activating the source, drain, anode,


Fig. 14. Optical image of the fabricated chip with an area of 10 × 10 mm2.

and cathode dopants, the Al from the intrinsic region of thephotodiodes was removed. After making the top gate, we useda contact-hole-one (CO1) mask to reach the source, drain, andgate of the bottom devices. Subsequently, a 1.2-µm-thick layerof TEOS was deposited on the wafers, followed by a contact-hole-two (CO2) mask to reach the bottom and top devices. Theopenings of the CO1 and CO2 masks were 2.5 µm × 2.5 µmand 3.5 µm × 3.5 µm, respectively. Next, 3 µm of Al wasdeposited at 350 ◦C to make contact between the top and bottomdevices. The intrinsic region of the photodiodes was left with300 nm of TEOS oxide to increase the quantum efficiency ofthe devices. Alloying was the last step and was performed at400 ◦C for 20 min to maintain good ohmic contacts.

Fig. 11 is a SEM image of the opened contact holes of anSRAM device region before metallization, showing access tothe devices of both layers. The top-layer holes are smaller insize, compared with the bottom-layer cavities.

Fig. 12 is a SEM image of the completed device, illustratingthe photodiodes with an intrinsic region width of 2 µm andbottom-layer transistors. Contact holes and the opened intrinsicregion of the photodiodes are visible in this SEM image.

A collection of TEM images of the fabricated wafer is shownin Fig. 13. Fig. 13(a) is a cross-sectional bright-field (BF) TEMimage of both the bottom and top layers of the devices, as wellas the location of the grain filters. In the bottom layer, 250 nmof polysilicon and 250 nm of crystalline silicon are visible. Thetop-layer gate is 675 nm of Al, which has been undercut fromthe dry-etching step. The size of the single-crystalline grainswas about 5 µm for both layers. Higher magnification TEMimages of the bottom-layer transistors are shown in Fig. 13(b)and (c), where the crystalline silicon channel, 30-nm gateoxide, and polysilicon gate are highlighted. Fig. 13(d) is a BFTEM image of the top layer, which had the photodiodes andthe Al layer removed from the light-sensitive region of thephotodiodes. The inset shows a higher magnification image ofthe intrinsic silicon layer and interfacial 30-nm oxide layer.

The fabricated die had a dimension of 10 × 10 mm2 forboth the SRAM and the image sensor. These two areas arehighlighted in Fig. 14.

Fig. 15. Measured I–V curves for the (a) top and (b) bottom layers oftransistors. The left and right two images are for the nMOS and pMOStransistors, respectively.

IV. ELECTRICAL MEASUREMENTS AND DISCUSSION

The Id–Vg and Id–Vd curves of the fabricated TFTs fromboth layers were measured and plotted in Fig. 15, where thegate length of the transistors was 2 µm and the width was 4 µm.The plots given in Fig. 15(a), (b), (e), and (f) are for the top-layer devices, where (a) and (b) are from the nMOS devices,and (e) and (f) are from the pMOS devices. Similarly, plots


TABLE IIEXTRACTED ELECTRICAL PARAMETERS FOR nMOS AND pMOS

TRANSISTORS FOR BOTH LAYERS

Fig. 16. I–V curve of a lateral p-i-n photodiode with a surface area of36 µm2 under microscope light illumination (with an intensity of 89 mW/m2).

for the bottom-layer devices are given in Fig. 15(c), (d), (g),and (h).

The electrical parameters for both layers of transistors areshown in Table II. The calculated data of mobility are fieldmobilities based on the extracted gm from the Id–Vg curvewhen transistors are biased in the linear region using a drainvoltage of 0.2 V. The subthreshold slope of TFTs are slightlyhigher, as caused by the PECVD TEOS oxide and interface withsilicon. Using grown inductive coupled plasma oxide, the slopewill be improved significantly [16]. As it can be seen from thistable, the bottom-layer devices have slightly lower performancethan the top layer of transistors. We believe this to be an effectof the laser crystallization of the top-layer silicon, impacting thebottom-layer quality [10]. The parameters shown in this tablewere average values obtained from over 52 dies of a 4-in wafer.There was a process variation of 10%–20% measured betweenthe devices.

In order to characterize the optical response of the photo-diodes, we used a probe station equipped with a parameteranalyzer and normal microscope light with an intensity of89 mW/m2. The I–V curve measured from a photodiodefabricated on the top layer is shown in Fig. 16. The appliedbias voltage to the diode ranged between −1.0 V and 0.5 V,whereas the light was turned on and off. The surface area of thephotodiodes was 36 µm2, and there was a very low leakagecurrent of 19.4 µA/cm2 at −1-V reverse-bias voltage. The

Fig. 17. Measured quantum efficiency of a lateral p-i-n photodiode.

Fig. 18. Measured transient response of one APS pixel. (The circuit isdisplayed in Fig. 6.)

photodiodes displayed two-orders-of-magnitude sensitivity tothe microscope light between the on and off conditions.

The quantum efficiency of the photodiodes was measuredas a function of the wavelength over a range of 300–850 nm,as shown in Fig. 17. The photodiodes had a maximum quantumefficiency of 60% at a wavelength of about 310 nm, which de-creased with increasing wavelength. In the visible-wavelengthregime, the quantum efficiency is only 15% because of thepresence of the 250-nm-thick silicon layer. The calculatedresponsivity is 0.15 A/W at a wavelength of 300 nm.

Fig. 18 displays an oscilloscope image of the transient re-sponse of one pixel. The pixel was illuminated by the micro-scope light with an intensity of 89 mW/m2. The frequency ofthe applied electrical pulse (blue) to the reset signal was 100 Hzwith 10% duty cycle. As shown in this figure, the output voltagefrom one pixel dropped when exposed to continuous light.

As mentioned previously, 6T SRAM cells were designed andfabricated on both the top and bottom layers. Fabricated SRAMcells where the pMOS transistors are on the top layer and thenMOS transistors are on the bottom layer had the highest readand write static noise margin (SNM) value of 0.75 V at 5-Vsupply voltage, as plotted in Fig. 19. The SNM value for theother structures was about 0.5 V.

A comparison of the performance between our fabricated3-DIC SRAM cells and those of other researchers is presentedin Table III. Our SRAM cells displayed lower access time and


Fig. 19. Butterfly curves of SRAM cells showing that the metastable point isat the middle of the curve. The inset shows the 6T SRAM cell circuit used.

TABLE IIICOMPARISON OF THE PERFORMANCE OF FABRICATED 3DIC SRAM CELLS

WITH VALUES REPORTED IN THE LITERATURE

better stability since the transistors have high mobility and havebenefited from the advantages of SOI technology [9], [12], [13].

V. CONCLUSION

In this paper, we have demonstrated a monolithic 3-D inte-gration of two single-grain silicon layers. The fabricated nMOSTFTs had mobilities of 600 and 400 cm2/V · s for the top andbottom layers, respectively. In addition, there was 100 timesmore current when light was applied to the photodiode thanwhen dark. SRAM cells with 0.75-V SNM were fabricated ontwo layers of the crystalline silicon with an area of 128F2.

ACKNOWLEDGMENT

The authors would like to thank all DIMES clean roomstaff, especially K. H. Zwetsloot, in the DIMES TechnologyCenter, Delft University of Technology, for their assistance inthe preparation of these devices.

REFERENCES

[1] K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, “3-D ICs: A novelchip design for improving deep-submicrometer interconnect performanceand systems-on-chip integration,” Proc. IEEE, vol. 89, no. 5, pp. 602–633,May 2001.

[2] M. Koyanagi, H. Kurino, K. W. Lee, K. Sakuma, N. Miyakawa, andH. Itani, “Future system on chip LSI chips,” IEEE Micro, vol. 18, no. 4,pp. 17–22, Jul./Aug. 1998.

[3] A. W. Topol, D. C. La Tulipe, L. Shi, D. J. Frank, K. Bernstein,S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, andM. Ieong, “Three-dimensional integrated circuits,” IBM J. Res. Dev.,vol. 50, no. 4/5, pp. 491–506, Jul./Sep. 2006.

[4] V. W. C. Chan, P. C. H. Chan, and M. Chan, “Three dimensional CMOSintegrated circuits on large grain polysilicon films,” in IEDM Tech. Dig.,2000, pp. 161–164.

[5] Y. H. Son, J.-W. Lee, P. Kang, M.-G. Kang, J. B. Kim, S. H. Lee,Y. P. Kim, I. S. Jung, B. C. Lee, S. Y. Choi, U. Chung, J. T. Moon, andB. Ryu, “Laser-induced epitaxial growth (leg) technology for high density3-d stacked memory with high productivity,” in VLSI Symp. Tech. Dig.,Jun. 2007, pp. 80–81.

[6] T. Nishimura, Y. Inoue, K. Sugahara, S. Kusunoki, T. Kumamoto,S. Nakagawa, M. Nakaya, Y. Horiba, and Y. Akasaka, “Three dimensionalIC for high performance image signal processor,” in IEDM Tech. Dig.,1987, pp. 111–114.

[7] V. Rana, R. Ishihara, Y. Hiroshima, S. Inoue, T. Shimoda, W. Metselaar,and K. Beenakker, “Single-grain Si TFTs and circuits inside location-controlled grains fabricated using a capping layer of silicon dioxide,”IEEE Trans. Electron Devices, vol. 54, no. 1, pp. 124–130, Jan. 2007.

[8] J. Derakhshandeh, M. R. Tajari Mofrad, R. Ishihara, and C. I. M.Beenakker, “Analog and digital output lateral photodiodes fabricated byµ-Czochralski process at low temperature,” in Proc. Device Res. Conf.,2009, pp. 93–94.

[9] N. Golshani, J. Derakhshandeh, R. Ishihara, and C. I. M. Beenakker,“High speed 6T SRAM cells using single grain TFTs fabricated byµ-Czochralski process at low temperature,” Jpn. J. Appl. Phys. (JJAP),vol. 49, no. 3, pp. 03C A09-1–03C A09-6, Mar. 2010.

[10] M. R. Tajari Mofrad, J. Derakhshandeh, R. Ishihara, and C. Beenakker,“Monolithic stacking of single-grain thin-film transistors to realize highperformance three dimensional integrated circuits,” Jpn. J. Appl. Phys.,vol. 48, no. 3, pp. 03B 015-1–03B 015-4, 2009.

[11] R. Ishihara, J. Derakhshandeh, M. R. Tajari Mofrad, T. Chen, andC. I. M. Beenakker, “Monolithic 3D-ICs with single grain Si TFTs,” inProc. AMFPD, Tokyo, Japan, 2009.

[12] Y. H. Suh, H. Y. Nam, S. B. Kang, B. G. Choi, H. S. Mo, G. H. Han,H. K. Shin, W. R. Jung, H. Lim, C. K. Kwak, and H. G. Byun, “A256 Mb synchronous-burst DDR SRAM with hierarchical bit-line ar-chitecture for mobile applications,” in Proc. ISSCC Dig. Tech. Papers,Feb. 2005, pp. 476–477.

[13] H. Ebihara, N. Karaki, S. Hirabayashi, T. Kodaira, S. Inoue, andT. Shimoda, “A Flexible 16 kb SRAM based on low-temperature poly-silicon (LTPS) TFT technology,” in Proc. SID, Jun. 2006, vol. 37, no. 1,pp. 339–342.

[14] A. Amara and O. Rozeau, Planar Double-Gate Transistor: From Tech-nology to Circuit. New York: Springer-Verlag, 2009, p. 212.

[15] R. Ishihara, P. C. van der Wilt, B. D. van Dijk, A. Burtsev, J. W. Metselaar,and C. I. M. Beenakker, “Advanced excimer-laser crystallization processfor single-crystalline thin film transistors,” Thin Solid Films, vol. 427,no. 1/2, pp. 77–85, Mar. 2003.

[16] T. Chen, R. Ishihara, J. van der Cingel, A. Tajari, M.R. Mofrad,H. Schellevis, and C. I. M. Beenakker, “Integrated high performance (100)and (110) oriented single-grain Si TFTs without seed substrate,” in IEDMTech. Dig., Baltimore, MD, pp. 179–182.

[17] J. Derakhshandeh, M. R. Tajari Mofrad, R. Ishihara, J. Van der Cingel,and C. I. M. Beenakker, “A study on CMP effect on the quality of thinsilicon film crystallized by µ-Czochralski process,” J. Korean Phys. Soc.(JKPS), vol. 54, no. 925, p. 432, 2009.

Jaber Derakhshandeh was born in Tabriz, Iran,in 1974. He received the Bachelor’s degree fromthe University of Tabriz, Tabriz, the Master’s degreefrom Sharif University of Technology, Tehran, Iran,and the Ph.D. degree in electrical engineering fromthe University of Tehran, Tehran, Iran.

During his studies, he worked on automatingand repairing electronic systems, implementing anelectron beam evaporation system, low-temperaturepolysilicon thin-film transistors, and using carbonnanotubes for lithography purposes. He has taught

several undergraduate courses in electronics engineering. In 2006, he joined theLaboratory of Electronics Components, Technology and Materials, Delft Insti-tute of Microsystems and Nanoelectronics, Faculty of Electrical Engineering,Delft University of Technology, Delft, The Netherlands, where he is currentlyworking on monolithic 3-D integrated circuits, CMOS image sensors, carbonnanotubes, and low-energy electron photodiodes.


Negin Golshani was born in Orumieh, Iran, in 1974.She received the B.S. degree in electrical engineeringfrom the University of Tabriz, Tabriz, Iran, and theM.S. degree in microelectronics from Delft Univer-sity of Technology, Delft, The Netherlands, in 2009,working on monolithic 3-D integrated circuits forstatic random-access memory applications. She iscurrently working toward the Ph.D. degree in theLaboratory of Electronics Components, Technologyand Materials, Delft Institute of Microsystems andNanoelectronics, Faculty of Electrical Engineering,

Delft University of Technology, working on X-ray silicon drift detectors.

Ryoichi Ishihara was born in Japan in 1967. He re-ceived the B.E., M.E., and Ph.D. degrees from TokyoInstitute of Technology, Tokyo, Japan, in 1991, 1993,and 1996, respectively.

Since 1996, he has been with the Laboratory ofElectronics Components, Technology and Materials,Delft Institute of Microsystems and Nanoelectronics,Faculty of Electrical Engineering, Delft Universityof Technology, Delft, The Netherlands, where he iscurrently an Associate Professor. He is in charge ofa number of projects related to TFT technologies

for 3-D-ICs and flexible electronics. His research interests include excimer-laser crystallization of Si films, low-temperature chemical vapor depositionof silicon nitride films, and fabrication of amorphous-Si and poly-Si thin-filmtransistors (TFTs) on a glass substrate. His current research interests includelocation and orientation control of silicon grains through a novel excimer-laser crystallization process, and fabrication and characterization of high-performance TFTs inside a single grain.

Dr. Ishihara is a member of the IEEE Electron Devices Society, the Societyfor Information Display, the Material Research Society, and the Japan Societyof Applied Physics.

Mohammad Reza Tajari Mofrad was born inTehran, Iran, in 1982. He received the B.Sc. andM.Sc. degrees, in 2005 and 2007, respectively,from Delft University of Technology, Delft, TheNetherlands, where he is currently working towardthe Ph.D. degree in the Laboratory of ElectronicComponents, Materials and Technology (ECTM),Delft Institute of Microsystems and Nanoelectronics,Faculty of Electrical Engineering.

His research interests include excimer-laser crys-tallization of Si films, fabrication and characteriza-

tion of high-performance TFTs inside a single-crystalline grain, laser-inducedepitaxial growth of silicon, and stacking of transistor and sensor layers formonolithic 3-D integrated-circuit applications.

Michael Robertson was born in St. Catharines,ON, Canada, in 1964. He received the B.Sc. andPh.D. degrees in physics from the University ofWaterloo, Waterloo, ON, Canada, in 1988 and 1996,respectively.

He is currently the Canada Research Chair inMaterials Science and the Full Professor with theDepartment of Physics, Acadia University,Wolfville, NS, Canada. Prior to joining AcadiaUniversity, he was a Research Scientist and Managerin the pulp-and-paper and optoelectronics industries.

His current research interests include the application of correlative electronmicroscopy techniques to understand the optical, electrical, chemical, andstructural properties of semiconductors.

Thomas Morrison was born in Montreal, QC,Canada. He is currently working toward the B.S.degree in physics in Queen’s University, Kingston,ON, Canada.

He has been a Lab Assistant with the Depart-ment of Physics, Acadia University, Wolfville, NS,Canada. In the summer of 2011, he was awardeda grant from the Natural Sciences and EngineeringResearch Council of Canada to work on the dark-matter project at the Sudbury Neutrino Observatory.

C. I. M. Beenakker was born in Leiden, TheNetherlands, in 1948. He received the M.Sc. degreein chemistry and physics from Leiden University,Leiden, in 1971 and the Ph.D. degree fromFOM-Institute for Atomic and Molecular Physics,Amsterdam, The Netherlands, in 1974.

Thereafter, he joined Philips Research Laborato-ries, Eindhoven, The Netherlands. In 1982, he movedto the Philips Semiconductor Division, Nijmegen,The Netherlands, to become the head of the corporateassembly process and equipment development. In

1987, he resigned from Philips and became a cofounder of Eurasem, whichis a European hi-rel IC assembly company. In 1989, he joined the Labora-tory of Electronics Components, Technology and Materials, Delft Institute ofMicrosystems and Nanoelectronics, Faculty of Electrical Engineering, DelftUniversity of Technology, Delft, The Netherlands, and since 1990, he hasbeen a Full Professor with the Faculty of Electrical Engineering, Mathematicsand Computer Science (EEMCS). In 1999, he was appointed Chairman ofthe Department of Microelectronics and Computer Engineering. Since March2006, he holds an honorary guest professorship at Tsinghua University, Beijing,China. In March 2007, he was appointed Scientific Director of DIMES. In June2008, he was elected Chairman of the Academic Council of Point-One, whichis the Dutch initiative on nanoelectronics and embedded systems. His researchinterests include technology for thin films and ICs.

monolithic 3-d integration of sram and image sensor using two layers of single-grain silicon

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