Monitor-ing,

Basic IPHeaderProc.,

PacketClassi-fication

and

Routing

AP

IC D

rive

r R

cv S

ide

APIC

PluginCtl. Unit

. . .

Resource Controller

. . .

RcvInputSide

. . .

RcvOutput

Side

. . .. . .

. . .. . .

Pac

ket

Sche

dule

rP

acke

tSc

hedu

ler

. . .

AP

IC D

rive

r X

mit

Sid

e

. . .. . .

XmitInputSide

. . .

XmitOutput

Side

APICRegisterAccess

RegisterAccess

Software InterruptLevel APIC Driver

APIC Descs. &AAL5 frame

in mbufdata buffers

. . .

ip_input

tcp/udp_input

User Socket LayerKernel Socket Layer

ip_output

tcp/udp_output

APIC Descs. &AAL5 frame

in mbufdata buffers

IP Packetin chained

mbufs

ClassifiedIP Packetin chained

mbufswith route

IP Packetin chained

mbufs

APIC Descs. &AAL5 frame

in mbufdata buffers

RegisterAccess

SW Int

Cntxt

HW Int

Cntxt

Kernel SpaceUser Space

Interrupt

IP Opt

IP Path

Software InterruptLevel APIC Driver

User Layer CB SocketKernel Layer CB Socket

RegisterAccess

Data Structures: APIC Descriptor

Match/Checksum - - - -

BufAddrLo

BufAddrHi

BufLen NextDesc

V I SOECLX T Y

081624 31

Physical Addressof Data Buffer

Index into Desc TableBuffer Length orAmount Left Unused

O: Read Only,E: EOF, C: CRC OK,

T: Type, Y: Valid Bits

BufferData

Byte 0

Byte Buflen - 1

BufAddrLoBufAddrHi

Data Structures: mbuf

Step 0.1: APIC Driver Initializes Desc. and Buffers Structures

0xCAFE - - - -

BufAddrLo

BufAddrHi

2016 NextDesc

V I SO0

E0

C0LX T

00Y11 0xCAFE - - - -

BufAddrLo

BufAddrHi

2016 NextDesc

V I SO0

E0

C0LX T

00Y11

Pool X Chain Head

0xCAFE

BufAddrLo

BufAddrHi

2016

MBUFm_data

MBUFm_data

Step 0.2: APIC Driver Initializes Descriptors and Buffers

AP

IC D

rive

r R

cv S

ide

APIC

. . .

RcvInputSide

. . .Rcv

OutputSide

RegisterAccess

APIC Descs. &AAL5 frame

in mbufdata buffers

Interrupt

0xCAFE - - - -

BufAddrLo = 0

BufAddrHi = 0

0 NextDesc = 0

V I SO0

E0

C0LX T

00Y01

VC 101 Queue

For each VC that has been opened, the APIC Driverinitializes the per VC Current Descriptor register inthe APIC hardware to point to a descriptor that ismarked DONE_INVALIDLINK. Thus when the APIC starts getting data for this VC, it will be forced togo off and grab the next available Descriptor andre-write the current one with a pointer to the new one. The APIC driver keeps a structure for the VCthat keeps a pointer to this chain (our per VC queue!).

Y: Valid Bits (01: DONE_INVALIDLINK)

Step 0.3: APIC Driver Initializes Descriptors and Buffers

AP

IC D

rive

r R

cv S

ide

APIC

. . .

RcvInputSide

. . .Rcv

OutputSide

RegisterAccess

APIC Descs. &AAL5 frame

in mbufdata buffers

Interrupt

0xCAFE - - - -

BufAddrLo

BufAddrHi

2016 NextDesc

V I SO0

E0

C0LX T

00Y11 0xCAFE - - - -

BufAddrLo

BufAddrHi

2016 NextDesc

V I SO0

E0

C0LX T

00Y11

Pool X Chain Head

0xCAFE

BufAddrLo

BufAddrHi

2016

MBUFm_data

MBUFm_data

Step 1: APIC Hardware Writes 3016 byte AAL5 Frame to Memory

AP

IC D

rive

r R

cv S

ide

APIC

. . .

RcvInputSide

. . .

RcvOutput

Side

RegisterAccess

APIC Descs. &AAL5 frame

in mbufdata buffers

Interrupt

checksum ??? - - - -

BufAddrLo

BufAddrHi

0 NextDesc

V I SO0

E0

C0LX T

00Y00 checksum - - - -

BufAddrLo

BufAddrHi

1016 NextDesc ???

V I SO0

E1

C1LX T

00Y00

Pool X Chain Head

0xCAFE

BufAddrLo

BufAddrHi

2016

Need to show how theyget linked to the per VC

queue that exists.

VC 101’ Queue

PacketClassi-fication

andRouting

AP

IC D

rive

r R

cv S

ide

APIC

. . .

RcvInputSide

. . .

RcvOutput

Side

. . .. . .

RegisterAccess

APIC Descs. &AAL5 frame

in mbufdata buffers

IP Packetin chained

mbufs

Step 2: APIC Driver Chains Mbufs into IP Packet