module 2 - com bi national logic feb 2

8/4/2019 Module 2 - Com Bi National Logic Feb 2

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MODULE 2

COMBINATIONAL LOGIC

Monday, January 24th 2011


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Module 2: COMBINATIONAL LOGIC

2ECSE-221B

Assignment 1 due today (Monday Jan. 24th) by 5 pm

Assignment submitted through the course web page (WebCT)

by 5 pm today (Monday).

No handwritten assignment will be graded.

Penalty

- 5 % for submission between Monday 5:01 pm and Tuesday 5:00 pm

- 10 % for submission between Tues. 5:01 pm and Wed. 11:59 pm

- 100 % for submission on Thursday or later


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3ECSE-221B

Assignment 1 due today by 5 pm

For questions about C/Q5:

office hours today only Mohamed Kurdi 2:30-3:30 (5th Trottier)

Resources on WebCt:

Q5 from 2010 C program for multiplication instead of division.

Questions related to course material:

My regular office hours 2:45 4:00 MC531


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4ECSE-221B

Content

Combinational Logic: digital logic implemented by Boolean circuit

(e.g. using AND and OR gates) where the output is a function of

the present input (memoryless)

Logic Circuits & Switching Elements

Switching Elements in Series and in Parallel

Boolean Properties and Identities

Canonical Forms

Transformation of Forms

Logic Minimization Karnaugh Maps

Building Blocks

Digital Logic Technologies


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5ECSE-221B

References

General book references on Logic Design

Example: R.H. Katz, Contemporary Logic Design.

P&H (4th Edition): Appendix C The Basics of Logic Design.

This appendix is on the CD that comes with the book.


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6ECSE-221B

LOGIC DESIGN

PURPOSE: Implement Boolean functions by means of circuits.

Boolean functions have variables can only have two

possible values.

The smallest building blocks to implement a Boolean

function are called gates.


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7ECSE-221B

LOGIC DESIGN - CONVENTIONS

Digital circuits operate with two voltage levels of interest:

High (VH)

Low (VL)

We associate a value and a symbol to these voltages.

We also say that a signal is asserted (True value, High

voltage) or deasserted (False value, Low voltage).

Voltage Value Symbol

High True 1

Low False 0


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8ECSE-221B

TWO KINDS OF LOGIC CIRCUITS

Combinational Circuits: Output = Fct(Input)

These circuits have no memory: the output lines depend

only on the inputs. Fct is a logic function.

Sequential Circuits: Output = Fct(Input, State)

The circuits have memory: the output lines depend on the

input and on the State which are values stored in

memory.


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9ECSE-221B

TRUTH TABLES

How could we describe the values of the Outputvariables

for each possible values of the Inputvariables?

You build a Truth Table.

Ifn is the number of Input

variables (In1, In2, ..., Inn)

there are 2n possible entries,

one for each combination.

Inputs Outputs

In1 In2 In3 Out1 Out2 Out3

0 0 0 0 0 0

0 0 1 1 0 0

0 1 0 1 0 0

0 1 1 1 1 0

1 0 0 1 0 01 0 1 1 1 0

1 1 0 1 1 0

1 1 1 1 0 1


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10ECSE-221B

Logic circuit are comprised of switchingelements.

The 3 terminal device behaves as follows:

if Vin Vt, switch closed

(terminals 1-3 shorted)

if Vin < Vt, switch open

(terminals 1-3 open)

The properties of the switch are such that:0 Vt V

+ 3

(V+:Voltage supply Vt:Threshold voltage)

V+

VoutVin

1

3

2

Let Vin represent a binary-valued variable such that

logical 1 corresponds to V+ volts and logical 0corresponds to 0 volt.

The behaviour of the circuit can be expressed by atruth table.

The logical function performed by the circuit iscomplement, hence it is referred to as an

INVERTER.

Vin Switch State Vout

V+ CLOSED 0

0 OPEN V+

SWITCHING ELEMENTS

truth table

1 3

1 3


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11ECSE-221B

SWITCHING ELEMENTS cont.

In current implementations, switches are fabricated usingTRANSISTORS (BJT, MOS).

For the purposes of this course we will assume that theybehave as ideal switches.

The purpose of the resistor is to PULL UP the output to V+when the switch is open; the switch serves to PULL DOWNthe output to 0 when activated.

The configuration shown in the previous slide is referred to

as PASSIVE PULL UP/ACTIVE PULL DOWN.It has the advantage of being simple, but takes a lot ofspace in silicon (resistors have large geometry),consumes more power and has a number of switchinglimitations (will become clearer in ECSE-323).


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12ECSE-221B


The configuration shown here

gets around some of theseproblems.

Notice the bubble on the upperswitch.

It operates as follows:

- if Vin < Vt, 1-3 shorted

- if Vin Vt, 1-3 open

i.e., when the upper switch isclosed, the bottom switch isopen and vice-versa.

V+

VoutVin

1

3

2

5

4

This configuration shown is referred to as ACTIVE PULL UP/ACTIVE

PULL DOWN.


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13ECSE-221B

In the logic circuit below, what is Vout if Vin=V+?

1) 2) 3)

15%

76%

9%

V+

VoutVin

1

3

2

5

4

It acts as an inverter.

1) Vout=V+

2) Vout=Vt3) Vout=0

d l 2 CO O OG C


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14ECSE-221B


What happens when we swap pull-up and pull-down

elements?

This configuration is referred to as an

ACTIVE PULL UP/PASSIVE PULL DOWN.

When Vin > Vt, 1-3 shorted

Vout = V+

When Vin

Vt1-3 open

Vout = 0

The gate operates as a

non-inverting BUFFER.

V+

Vout

Vin

1

3

2

M d l 2 COMBINATIONAL LOGIC


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15ECSE-221B


Analogously to the inverter, we can replace the passive pull-down element with a complementary switching element asfollows:

It is easily verified that thecircuit acts as a non-invertingBUFFER.

if Vin Vt, Vout = V+

if Vin Vt, Vout = 0

V+

VoutVin

1

3

2

5

4



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16ECSE-221B


We can summarize the behaviour of the circuitsencountered thus far using the following table:

where active (1) switch closed if Vin Vt,

active (0) switch closed if Vin < Vt.

Vt is referred to as the threshold voltage of the switch.

The threshold voltage is a property of the particular devicecharacteristics along with the biasing arrangements.

Pull-up Pull-down Function

passive active (1) inverter

active (0) active (1) inverter

active(1) passive buffer

active(1) active(0) buffer



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17ECSE-221B


The 4 configurations listed in the table are generallyseparated into 2 classes, depending on whether a passiveelement (e.g. a resistor) is present or not.

This has strong implications on the semiconductorfabrication technology used to implement the circuits.

Within each class there are two configurations, buffers and

inverters, depending on whether the output logic level is the

input level or its complement, respectively.

More complex gates are built from these basic structures.



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18ECSE-221B

Lets consider what happens when we connect two inverters inseries as shown below. The behaviour of the circuit can be

described by a truth table.

The circuit corresponds to a 2-input NAND gate.

Larger NAND gates can be fabricated by placing additional activeswitches in series (up to the practical limit determined byelectronic circuit considerations).

V+

ELEMENTS IN SERIES NAND gate (passive pullup)

X

Y

Z

X Y

0 0

0 1

1 0

1 1

The truth table is easily

verified by noting that the onlycondition under which Z can be0 is for BOTH switches to beactive, i.e. X=1 and Y=1.

Z

1

1

1

0



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19ECSE-221B

Recall that an inverter is turned into a non-inverting buffer bytransposing the passive pull-up with the active (1) pull-down.

This suggests a way of converting a NAND gate into a AND gate.

This confirms our supposition that transposing pull-up and pull-down elements negates the initial function.

As with the NAND gate shown previously, multiple inputs areaccommodated by placing additional switch elements in series.

ELEMENTS IN SERIES AND gate (passive pull-down)

V+

X

Y

Z

X Y

0 0

0 1

1 0

1 1

The truth table is easily verified.

By default, Z = 0 if either switchis off. Hence the only way inwhich Z=1 is if BOTH X and Yare set to 1.

Z

0

0

0

1



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20ECSE-221B

The case of series connection of element switch an active pull-upor pull-down is slightly more complex since a switch can have

only a single control.

The circuit corresponds to a NAND gate with the additionalfeatures of smaller geometry (i.e. Size) and better switchingcharacteristics.

V+

ELEMENTS IN SERIES NAND gate

X

Y

Z

X Y

0 0

0 1

1 01 1

As before, we candetermine thefunction of the

circuit by exploringits true table.

If either X or Y is 0, one of the two serieselements is open, and one of the parallelelements closed so that Z = 1. The only

case in which Z = 0 is if both X and Y are 1.

Z

1

1

10



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21ECSE-221B

In the configuration below,what is Z if X = 0 and Y = 1?

1) 2) 3)

17% 15%

68%

V+

X

YZ

1) Z = 1

2) Z = 0

3)Neither



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22ECSE-221B

We would expect that swapping the pull-up and pull-downstructure should result in an AND gate.

Hence the circuit corresponds to an AND gate. To increase thenumber of inputs, additional pull-ups are connected in seriesand pull-downs in parallel.

ELEMENTS IN SERIES AND gate (active)

X Y Z

0 0 0

0 1 0

1 0 0

1 1 1

We can test this hypothesisby verifying the true tablecorresponding to the circuit

A 0 at X or Y opens the path to V+ andshorts the path to ground.

Only X and Y both 1 will set Z to 1.

V+

X

YZ



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23ECSE-221B

We now repeat our investigation for switching elements connectedin parallel. Consider what happens when two inverters are

connected in parallel as shown below.

It is easily verified from the truth table that the circuitcorresponds to a NOR gate.

This is not entirely unexpected and is related to the principle of

DUALITY which we will study shortly.

ELEMENT IN PARALLEL NOR gate (passive pull-up)

X Y

0 0

0 1

1 0

1 1

The truth table isdetermined (as before) byevaluating the circuit

output for each inputcombination.

The only possible way for Z to be 1is for both switches to be off.

V+

XY

Z

Z

1

0

0

0



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24ECSE-221B

Again, swapping the pull-up and pull-down elements shouldchange the sense of the gate, i.e., from NOR to OR.

The circuit corresponds to an OR gate as we suspected.

V+

ELEMENT IN PARALLEL OR gate (passive pull-down)

X

Y

Z

X Y Z

0 0 0

0 1 1

1 0 1

1 1 1

Evaluating the circuit for eachpossible input combinationyields the following truthtable.

The only possible case for a 0 output iffor both switches to be off.

Otherwise the output is pulled high ifeither or both switches are on.



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Parallel connection of elements with an active pull-up or pull-downinvolves replacing the passive element with active (0) switching

elements in series. First, consider the case where the active (0)elements are on top.

A 0 on both X and Y open circuits both of the lower switches andshort circuit the path to V+. From the truth table it can be seenthat the circuit corresponds to a NOR gate.

ELEMENT IN PARALLEL NOR gate (active)

X Y

0 0

0 1

1 0

1 1

The truth table correspondingto this circuit is determined

by evaluating the response toeach of the 4 possible inputcombination

A 1 on either X or Y open circuits the pathto V+ and short circuits the path to ground.

V+

X

Y

Z

Z

1

0

0

0



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26ECSE-221B

Finally, to obtain a positive OR gate using both active pull-up andpull-down elements, we swap the upper and lower elements as

follows.

The only combination that can result in 0 output is for both inputsto be 0, hence the circuit is a positive OR gate.

ELEMENT IN PARALLEL OR gate (active)

X Y

0 0

0 1

1 0

1 1

We can test this hypothesis byverifying the true tablecorresponding to the circuit

A 1 on X or Y open circuits the bottom legand closes one of the two switches inparallel, resulting in an output of 1.

V+

X

Y

Z

Z

0

1

1

1



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27ECSE-221B

BOOLEAN ALGEBRA

Logic functions, which we have represented thus far using

truth tables, can also be expressed in terms of logic

equations. This gives rise to Boolean Algebra (after the

mathematician, 1815-1864).

To a computer engineer:

Boolean algebra is a notation to describe logical relationship

between two-valued variables.

e = f(a,b,c,d), where {a, b, c, d, e} = [0,1]



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28ECSE-221B

BOOLEAN ALGEBRA

All variables have the values 0 or 1. There are threeoperators defined as follows:

The three operators are also referred to asA + B LOGICAL SUM

A B LOGICAL PRODUCTNOT LOGICAL NEGATION

Boolean algebra is governed by rules and axioms whichenable logic equations to be manipulated.

A B NOT A NOT B A + B A B

0 0 1 1 0 0

0 1 1 0 1 0

1 0 0 1 1 01 1 0 0 1 1



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29ECSE-221B

PROPERTIES & IDENTITIES

Properties of 0 and 1.

Identity law: A + 0 = A and A 1 = A

Proof by enumeration:

If A = 0, 0 + 0 = 0 If A = 1, 1 + 0 = 1

If A = 0, 0 1 = 0 If A = 1, 1 1 = 1

Zero and One laws: A + 1 = 1 and A 0 = 0

Proof by enumeration:

If A = 0, 0 + 1 = 1 If A = 1, 1 + 1 = 1

If A = 0, 0 0 = 0 If A = 1, 1 0 = 0


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MODULE 2

COMBINATIONAL LOGIC

Wednesday, January 26th 2011



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31ECSE-221B

What is the logic value of output Z if X = Y = 1 ?

1) 2) 3) 4)

10%

63%

23%

5%

V+

X

Y

Z

1) Z=X

2) Z=Y

3) Z=0

4) Z=1



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32ECSE-221B

Using Boolean algebra, simplify the following logicfunction:

1) 2) 3) 4)

4%

85%

4%7%

AAAA

1) A

2) A

3) 04) 1



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33ECSE-221B

PROPERTIES & IDENTITIES cont.

Inverse laws

and

Idempotence (i.e. doesnt change the results):

A + A = A and A A = A

Commutative laws:

A + B = B + A and A B = B A

1 AA 0 AA



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34ECSE-221B


Associative Laws: A + (B + C) = (A + B) + C

A (B C) = (A B) C

Distributive Laws: A (B + C) = (A B) + (A C)

A + (B C) = (A + B) (A + C)

Absorption Laws: A + (A B) = A

A (A + B) = A

DeMorgans Laws: BABA

BABA



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35ECSE-221B


All the properties in the previous slide come in pairs.

Each is formally obtained from its dual by:

1. Exchanging the operators and +

2. Exchanging the constants 0 and 1



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36ECSE-221B

CANONICAL FORMS

There are two fundamental algebraic forms to describe a

truth table:

MINTERM or SUM OF PRODUCTS form

MAXTERM or PRODUCT OF SUMS form.



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37ECSE-221B

CANONICAL FORMS cont.

Consider the truth table for a full-adder:

Cin A B Sum Cout

0 0 0 0 0 0

1 0 0 1 1 0

2 0 1 0 1 0

3 0 1 1 0 1

4 1 0 0 1 0

5 1 0 1 0 1

6 1 1 0 0 1

7 1 1 1 1 1

Cin = CarryCout = Carry from Cin + A + B

A + B = Sum

Cin+A+B = Sum + Cout



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38ECSE-221B


Minterm: CONJUNCTION of input variables

([Cin,A,B] in this case) that is true whenever the

corresponding output is true.

For example, notice that Sum is true (i.e. Sum = 1) when

[Cin,A,B]=[0,0,1].

The corresponding logical expression would then be:

BACin



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39ECSE-221B

Minterm - Sum of Products

Cin A B Sum Cout

0 0 0 0 0 0

1 0 0 1 1 0

2 0 1 0 1 0

3 0 1 1 0 1

4 1 0 0 1 0

5 1 0 1 0 1

6 1 1 0 0 1

7 1 1 1 1 1

Sum =

BACin

BACin

BACin

BACin



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40ECSE-221B


Using this approach we can completely specify the logical

functions for the output variables Sum and Cout by

taking the logical sum of each minterm as follows:

Sum = Cin A B + Cin A B + Cin A B + Cin A B,

Cout = Cin A B + Cin A B + Cin A B + Cin A B.

This form is referred to as a SUM OF PRODUCTS, often

abbreviated as .



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41ECSE-221B


With those two logical functions representing the full-adder,lets see if they give the right results.

For example, lets say the input to the full-adder is[Cin,A,B]=[1,0,1].

Sum = Cin A B + Cin A B + Cin A B + Cin A B

= 0x1x1 + 0x1x0 + 1x1x0 + 1x0x1

= 0 + 0 + 0 + 0 = 0Cout = Cin A B + Cin A B + Cin A B + Cin A B

= 0x0x1 + 1x1x1 + 1x0x0 + 1x0x1

= 0 + 1 + 0 + 0 = 1

Full-adder

Cin = 1

A= 0

B= 1

Sum= ?

Cout= ?



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42ECSE-221B


A maxterm is a DISJUNCTION over the input variables that

is false whenever the corresponding output is false.

Notice that Sum is false when [Cin,A,B]=[0,0,0].

The corresponding logical expression would be

Cin + A + B.



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43ECSE-221B

Cin A B Sum Cout

0 0 0 0 0 0

1 0 0 1 1 0

2 0 1 0 1 0

3 0 1 1 0 1

4 1 0 0 1 0

5 1 0 1 0 1

6 1 1 0 0 1

7 1 1 1 1 1

Sum =

BACin

BACin

BACin

BACin

Maxterm Product of sums



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44ECSE-221B


Using this approach we can write expressions for Sum and

Cout by taking the logical product of each maxterm as

follows:

Sum = (Cin + A + B)(Cin + A + B)(Cin + A + B)(Cin + A + B)

Cout = (Cin + A + B)(Cin + A + B)(Cin + A + B)(Cin + A +B)

This is referred to as a PRODUCT OF SUMS, .



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45ECSE-221B


Again, lets see if the would give the right results.

Lets say the input to the full-adder is [Cin,A,B]=[1,0,1].

Sum = (Cin + A + B)(Cin + A + B)(Cin + A + B)(Cin + A + B)

= (1 + 0 + 1)x (1 + 1 + 0)x (0 + 0 + 0) x (0 + 1 + 1)

= (1) x (1) x (0) x (1) = 0

Cout = (Cin + A + B)(Cin + A + B)(Cin + A + B)(Cin + A +B)

= (1 + 0 + 1)x( 1 + 0 + 0)x(1 + 1 + 1)x(0 + 0 + 1)

= (1) x (1) x (1) x (1) = 1

Full-adder

Cin = 1

A= 0

B= 1

Sum= ?

Cout= ?



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46ECSE-221B


If the SUM OF PRODUCT and PRODUCT OF SUMS forms both

describe the same function, then we should be able to

prove this algebraically.

Using the expression for Sum as an example, lets start by

writing and expression for its complement as sum of

products:




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47ECSE-221B

Minterm - Sum of Products

Cin A B Sum Sum Cout

0 0 0 0 0 1 0

1 0 0 1 1 0 0

2 0 1 0 1 0 0

3 0 1 1 0 1 1

4 1 0 0 1 0 0

5 1 0 1 0 1 1

6 1 1 0 0 1 1

7 1 1 1 1 0 1

Sum =

BACin

BACin

BACin

BACin



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48ECSE-221B



Apply de Morgans law ( ) to the right hand side:

Sum = Cin+A+B + Cin+A+B + Cin+A+B + Cin+A+B

Apply de Morgans law ( ) one more time:

Sum = (Cin+A+B)(Cin+A+B)(Cin+A+B)(Cin+A+B)

Which is exactly what is required.


BABA

BABA



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49ECSE-221B


So, given a truth table, we now have a mechanism for

expressing it as a logical function in one of two canonical

forms.

But what about its implementation as an electronic circuit?



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50ECSE-221B

COMMON BUILDING BLOCKS

Combinational logic is often defined in terms of standard

building blocks ranging from simple gates to complex

functions such as ALUs (arithmetic and logical units).

The Basic Gates:

AND Gate A B

NAND Gate A B

NOT Gate A

A B A AB AB

0 0 1 0 1

0 1 1 0 1

1 0 0 0 1

1 1 0 1 0



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51ECSE-221B

COMMON BUILDING BLOCKS cont.

OR Gate A + B

NOR Gate A + B

XOR Gate A B + A B

XNOR Gate

A B + A B

A B A+B A+B

0 0 0 1

0 1 1 0

1 0 1 0

1 1 1 0

A B AB+AB AB+AB

0 0 0 1

0 1 1 01 0 1 0

1 1 0 1


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MODULE 2

COMBINATIONAL LOGIC

Friday, January 28th 2011



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53ECSE-221B

What logic gate represents a NOR?

1 2 3 4 5

12%14%

4%2%

69%1.

2.

3.

4.

5.



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54ECSE-221B

CANONICAL FORMS TO LOGIC CIRCUITS

Given that we can transform a truth table into a logicequation, how do we transform the equation into an

equivalent logic circuit?

First, consider the expression we obtained earlier for thesum function expressed as a Sum of Products:


Each product corresponds to an AND gate, and the sum

which combines them together to an OR gate.



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55ECSE-221B

CANONICAL FORMS TO LOGIC CIRCUITS cont.

A direct circuit implementation might look as follows.

Notice how the expression maps DIRECTLY to the logic circuitimplementation.

Observe: the complexity of the resulting circuit is directly relatedto the complexity of the expression.

AND gate for the minterms

OR gate for the SUM

NOT gate



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56ECSE-221B


Next, consider the Product of Sums expression we

obtained earlier:


Each sum corresponds to an OR gate, and the productwhich combines them together to an AND gate.



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57ECSE-221B


A direct implementation of this expression results in thefollowing circuit:

Again, the complexity of the resulting circuit is directlyrelated to the complexity of the product-of-sumsexpression.

OR gate for the maxterms

AND gate for the Product

NOT gate



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58ECSE-221B


If we could somehow MINIMIZE these expressions, the

result would be a SIMPLER CIRCUIT.

This process is referred to as LOGIC MINIMIZATION.



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59ECSE-221B

TRANSFORMATION OF FORMS

In earlier notes we observed how logic gates could be negated by

swapping pull-up and pull-down elements.

While this is possible in theory, technological constraints often

make this impossible in practice.

For example, one family of logic, TRANSISTOR-TRANSISTOR

LOGIC (TTL), is based entirely on inverter structures.

AND/OR gates are fabricated by cascading NAND/NOR gates with inverters.

This adds additional switching delay, so circuits composed of

NAND and NOR gates are preferred.

We can achieve a suitable transformation by applying De Morgans

law to our canonical forms.



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60ECSE-221B

TRANSFORMATION OF FORMS

Example:


1. Negate terms

2. Change +s to s

3. Negate expression

Sum = Cin A B Cin A B Cin A B Cin A B

The resulting expression contains 4 NAND terms combinedtogether in a NAND.

We refer to this as NAND-NAND logic

ZYWXZYWX

ZYWXZYWX



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61ECSE-221B

TRANSFORMATION OF FORMS cont.

Compare the AND-OR and NAND-NAND circuits:

The NAND-NAND has about half the propagation delay ofthe AND-OR (excluding the inverters) for TTL.



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62ECSE-221B

We can apply De Morgans law to the form as well:

Applying De Morgan we obtain:

The resulting expression contains 4 NOR gates combinedtogether in a NOR.

We refer to this as NOR-NOR logic


BACinBACinBACinBACinSum




S O O O O S


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63ECSE-221B


The resulting expression contains 4 NOR gates combinedtogether in a NOR with the following equivalent circuit.

As with NAND-NAND, propagation delay is reduced.


LOGIC MINIMIZATION


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64ECSE-221B

LOGIC MINIMIZATION

The simplification of logic equations

to minimal form is referred to as

LOGIC MINIMIZATION.

This has a direct impact on the

complexity of the resulting circuit

implementation.

Consider the following truth table on

the right: 4 inputs and one output

16 possible combinations with 8 minterms and

8 maxterms

A B C D X0 0 0 0 0 1

1 0 0 0 1 0

2 0 0 1 0 0

3 0 0 1 1 1

4 0 1 0 0 1

5 0 1 0 1 0

6 0 1 1 0 0

7 0 1 1 1 0

8 1 0 0 0 1

9 1 0 0 1 0

10 1 0 1 0 1

11 1 0 1 1 1

12 1 1 0 0 1

13 1 1 0 1 0

14 1 1 1 0 1

15 1 1 1 1 0


LOGIC MINIMIZATION


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65ECSE-221B

LOGIC MINIMIZATION

The sum of products corresponding to the truth table in theprevious slide is:

DABCDCABCDBADCBA

DCBADCBACDBADCBAX


LOGIC MINIMIZATION t


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66ECSE-221B

LOGIC MINIMIZATION cont.

Algebraic minimization strategy:

Factor into terms that differ in 1 variable.

Repeat this procedure until no further simplification ispossible.

1.

Observe that the second term may be combined with eitherthe first or last term.

Idempotence says that any of the terms in the aboveexpression may be replicated without changing anything,so

BBDACAACDB

BBDCABBDCAX

DACCDBDCADCAX


LOGIC MINIMIZATION t


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67ECSE-221B

LOGIC MINIMIZATION cont.

2.

Now instead of requiring eight 4-input AND gates and one8-input OR gate, the circuit has been reduced to a total offour gates: one 3-input OR, one 3-input AND, and two 2-input ANDs (neglecting the inverters again).

These manipulations are not always obvious!

For this reason a convenient graphical method has beendeveloped Karnaugh Maps.

DCADACCDBDCADCAX

CCDACDBAADCX

DACDBDCX


KARNAUGH MAPS


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68ECSE-221B

KARNAUGH MAPS

Another more compact way of representing the truth table(on the left) is to use a KARNAUGH MAP (on the right)

Notice how each truth table entryis represented by a correspondingcell in the Karnaugh map.

X CD

00 01 11 10

AB 00 1 0 1 0

01 1 0 0 0

11 1 0 0 1

10 1 0 1 1

A B C D X

0 0 0 0 0 1

1 0 0 0 1 0

2 0 0 1 0 0

3 0 0 1 1 1

4 0 1 0 0 1

5 0 1 0 1 0

6 0 1 1 0 0

7 0 1 1 1 0

8 1 0 0 0 1

9 1 0 0 1 0

10 1 0 1 0 1

11 1 0 1 1 1

12 1 1 0 0 1

13 1 1 0 1 0

14 1 1 1 0 1

15 1 1 1 1 0


KARNAUGH MAPS cont


69/128

69ECSE-221B

KARNAUGH MAPS cont.

Also pay close attention to theordering! Each cell differs inexactly 1 variable when moving ina vertical or horizontal direction.

The map also wraps around theedges (bottom row to top row,leftmost column to rightmostcolumn).

Lets return to the minimizationexample shown earlier andexamine its relationship to themap shown here.

X CD

00 01 11 10

AB 00 1 0 1 0

01 1 0 0 0

11 1 0 0 1

10 1 0 1 1


KARNAUGH MAPS cont


70/128

70ECSE-221B

KARNAUGH MAPS cont.

Notice the 3 groups circles in different colors. What is their

significance?

Answer: they are comprised of minterms such that adjacententries DIFFER ONLY IN A SINGLE VARIABLE.

X CD

00 01 11 10

AB 00 1 0 1 0

01 1 0 0 0

11 1 0 0 1

10 1 0 1 1


KARNAUGH MAPS cont


71/128

71ECSE-221B

KARNAUGH MAPS cont.

Consider the group circled in red: 0000 0100 1100 1000.

In going from top to bottom (left to right in the group

outlined above), each successive minterm differs by onlya single bit.

The same is true for the blue group: 1100 1000 1010 1110

And also for the green: 0011 1011

X CD

00 01 11 10

AB 00 1 0 1 0

01 1 0 0 0

11 1 0 0 1

10 1 0 1 1


KARNAUGH MAPS cont


72/128

72ECSE-221B

The terms circled in red (first column) correspond to thefollowing minterm expression:

We already know that this reduces to the map simplymakes this relationship explicit.

Indeed, notice that the term is common to each celland that A and B each take on values of 0 and 1.

X CD

00 01 11 10

AB 00 1 0 1 0

01 1 0 0 0

11 1 0 0 1

10 1 0 1 1

DCBADCABDCBADCBAX

DC

DC

KARNAUGH MAPS cont.


KARNAUGH MAPS cont


73/128

73ECSE-221B

KARNAUGH MAPS cont.

In general, for an n-bit minterm:

A group of 2 minterms can be combined if they have n-1

variable in common 1 variable is eliminated.

A group of 4 minterms can be combined if they have n-2

variables in common 2 variables are eliminated.

A group of 8 variables can be combined if they have n-3

variables in common 3 variables are.


KARNAUGH MAPS cont


74/128

74ECSE-221B

So far weve identified 1 group of 4 ones. Are there any others?

The terms circled in blue correspond to the following minterm

expression:

Notice that the first two terms also appear in the previousexpression (circled in red). Thats OK, terms can be replicated as

needed (idempotence).

Again from the earlier algebraicmanipulation we know that thisreduces to .

This can be observed directly from theKarnaugh map each term hasin common with B and C taking on 0and 1.

KARNAUGH MAPS cont.

DCBADABCDCBADCABX

DA

DA

X CD

00 01 11 10

AB 00 1 0 1 0

01 1 0 0 0

11 1 0 0 1

10 1 0 1 1


KARNAUGH MAPS cont


75/128

75ECSE-221B

To complete the minimization procedure we have to accountfor each 1 that appears in the map. At this point the

terms A B C D and A B C D are left.Notice that they differ only in A the green circle shown on

the map which reduced to B C D.

Remember: each grouping has to contain a number of boxes equalto a power of 2 (4 boxes in a line, 4 boxes in a square, etc.).

X CD

00 01 11 10

AB 00 1 0 1 0

01 1 0 0 0

11 1 0 0 1

10 1 0 1 1

Combining the results weobtain the followingminimal expression for X:

X = C D + B C D + A D.

KARNAUGH MAPS cont.


I th K h h b l h t i th


76/128

76ECSE-221B

In the Karnaugh map shown below, what is theminimal expression for X

1) 2) 3) 4)

8%5%7%

80%

X CD

00 01 11 10

AB 00 0 1 1 0

01 0 0 0 0

11 0 0 0 0

10 0 1 1 0

BA

DB

BD

BABA

1)

2)

3)

4)


KARNAUGH MAPS cont


77/128

77ECSE-221B

As you might suspect (principal of duality) the Karnaughmap probably has something to do with maxterms as well.

We would probably suspect that variables A and B can beeliminated, i.e., that the minimal expressioncorresponding to this product of sums is (C + D).

KARNAUGH MAPS cont.

X CD

00 01 11 10

AB 00 1 0 1 0

01 1 0 0 0

11 1 0 0 1

10 1 0 1 1

DCBADCBADCBADCBA

First consider the terms circledin blue (the column under 01).The maxterm expression is:


KARNAUGH MAPS cont


78/128

78ECSE-221B

KARNAUGH MAPS cont.

Theres one way to find out simplify the expressionalgebraically. Heres a trick.

Take the dual form, i.e.,

Dual{(A + B + C + D) (A + B + C + D) (A + B + C + D)

(A + B + C + D)}

= (ABCD) + (ABCD) + (ABCD) + (ABCD)= (ACD)(B + B) + (ACD)(B + B)

= (ACD) + (ACD)

= (CD)(A + A) = CD

This gives us another expression that we can simplify muchmore easily. IT IS NOT EQUIVALENT. To convert back weneed to take the dual form of the result.

Dual{CD} = {C + D}


KARNAUGH MAPS cont


79/128

79ECSE-221B

KARNAUGH MAPS cont.

So the same properties of variable elimination also hold formaxterms. Lets complete the procedure by enumeratingthe remaining 0s

For the term circled in green (center of the map): (B + D)

and the term circled in blue: (C + D)

and the remaining term circled in red: (A + C + D)

X CD

00 01 11 10

AB 00 1 0 1 0

01 1 0 0 0

11 1 0 0 1

10 1 0 1 1


KARNAUGH MAPS cont


80/128

80ECSE-221B

KARNAUGH MAPS cont.

Combining all the maxterms, the minimal expression for X is

= (C + D)(B + D)(A + C + D)

For comparison, the minterm expression for X is

= CD + BCD + AD

X CD

00 01 11 10

AB 00 1 0 1 0

01 1 0 0 0

11 1 0 0 1

10 1 0 1 1


CIRCUIT IMPLEMENTATIONS


81/128

81ECSE-221B

CIRCUIT IMPLEMENTATIONS

We can use de Morgans law to convert each of thecanonical forms in NAND-NAND representation.

= C D + B C D + A D = C D B C D A D

NAND-NAND


CIRCUIT IMPLEMENTATIONS cont.


82/128

82ECSE-221B

CIRCUIT IMPLEMENTATIONS cont.

We can also use de Morgans law to in NOR-NOR representation aswell using the maxterm instead.

= (C + D)(B + D)(A + C + D)= (C + D)+(B + D)+(A + C + D)

NOR-NOR


DONT CARES


83/128

83ECSE-221B

DON T CARES

Consider the truth table shown here:

The ds in the output correspond todont cares, i.e. values for which theoutput is permitted to be either 0 or 1.

Since they can be taken either way, theyare usually selected so that thesimplest function is obtained.

C B A X

0 0 0 d

0 0 1 0

0 1 0 1

0 1 1 d

1 0 0 1

1 0 1 0

1 1 0 d

1 1 1 0


84/128

MODULE 2

COMBINATIONAL LOGIC

Monday, January 31st 2011


Which logic function below is the NOR-NOR


85/128

85ECSE-221B

Which logic function below is the NOR NORrepresentation of

1) 2) 3) 4)

16%

23%

10%

51%

CBACBACBAX

CBACBACBAX

CBACBACBAX

CBACBACBAX

CBACBACBAX 1)

2)

3)

4)


In the Karnaugh map shown below what is the


86/128

86ECSE-221B

In the Karnaugh map shown below, what is theminimal expression for X

1) 2) 3) 4) 5)

63%

27%

4%3%3%

X CD

00 01 11 10

AB 00 d 1 1 d

01 0 0 d 0

11 0 d d 0

10 d 1 1 d

B

DB

BAD D

1)2)

3)

4)

5) D


DONT CARES cont.


87/128

87ECSE-221B

O C co

Consider the Karnaugh map for this truth table

Notice how the dont cares are used to obtain

a minimal expression.

The ds corresponding to minterms 000 & 110are treated as 1s, and the remaining as 0.

This corresponds to X = A, instead of X = C B A + C B A

C B A X

0 0 0 d

0 0 1 0

0 1 0 1

0 1 1 d

1 0 0 1

1 0 1 0

1 1 0 d

1 1 1 0

X BA

00 01 11 10

C 0 d 0 d 1

1 1 0 0 d


TRUTH TABLE TO KARNAUGH MAP TO


88/128

88ECSE-221B

A B C D OUT

0 0 0 0 0 0

1 0 0 0 1 1

2 0 0 1 0 0

3 0 0 1 1 0

4 0 1 0 0 15 0 1 0 1 1

6 0 1 1 0 1

7 0 1 1 1 0

8 1 0 0 0 0

9 1 0 0 1 1

10 1 0 1 0 011 1 0 1 1 0

12 1 1 0 0 1

13 1 1 0 1 1

14 1 1 1 0 1

15 1 1 1 1 0

Karnaugh maprepresentation

Minimizedlogic function

Logic circuit

Transformation of forms

(e.g. NAND-NAND, NOR-NOR)

Truth Table


DIGITAL CIRCUIT TECHNOLOGIES


89/128

89ECSE-221B

Transistor-transistor logic (TTL):

Invented in 1961

Widely spread as general-purpose chipsChips integrate only a few logic gates

Used BJT type of transistors and resistors

5-volt power supply.

Metal-Oxide Semiconductor (MOS):

Use in modern integrated circuit

Fast, small, uses less power.

http://www.acroname.com

digikey.com

http://bwrcs.eecs.berkeley.edu/dcdg/chips/mixed-signal-maskless-lithography-chip/

http://www.heritage-audio.com/electronics.html

http://blog.onshoulders.org/?blogID=Spiderwheels


COMMON BUILDING BLOCKS - MULTIPLEXER


90/128

90ECSE-221B

The Multiplexer is a routing switch that selects 1 ofn inputlines to the output depending on the state of a set of

control inputs (S).The case for n = 2 is shown here.

S A B X

0 0 0 00 0 1 0

0 1 0 1

0 1 1 1

1 0 0 01 0 1 1

1 1 0 0

1 1 1 1

RoutingSwitch

(Multiplexer)

A

B

S

X


COMMON BUILDING BLOCKS MULTIPLEXER cont.


91/128

91ECSE-221B

We can synthesize this circuit using formal methods (e.g.

Karnaugh Map), but the logic equation is simple enough to

infer form inspection:

X = S A + S B

X AB

00 01 11 10

S 0 0 0 1 1

1 0 1 1 0

Can you see howthis NAND-NANDwas derived?


COMMON BUILDING BLOCKS MULTIPLEXER cont.


92/128

92ECSE-221B

Sometimes an additional control line is added to the basic

multiplexer as follows:

The enable (E) line is used to synchronize changes at X with

an external timing signal such as a clock line.

S A B E C D X1 0 0 0 1 1 11 0 1 0 0 1 11 1 0 0 1 1 1

1 1 1 0 0 1 11 0 0 1 1 1 01 0 1 1 0 1 11 1 0 1 1 1 01 1 1 1 0 1 1

D

C


Control lines: Enable & Select


93/128

93ECSE-221B

Select (S) in a multiplexer is the control line called select

will select one of the two inputs.

Enable (E): the control line called enable will enable the

circuit to perform based on the implemented truth

table. The logic circuit can be disabled such that theoutput is forced to a certain value regardless the

digital value at the inputs.


COMMON BUILDING BLOCKS - MULTIPLEXER cont.


94/128

94ECSE-221B

Larger multiplexers can be formed by cascading smaller

multiplexer like in a binary tree.

S0

D

C

B

A

S1

XRoutingSwitch

(Multiplexer)

RoutingSwitch

(Multiplexer)

RoutingSwitch

(Multiplexer)

4 input multiplexer (Input A, B, C, D)2 select lines (S0, S1)

Enable line not shown


PROPAGATION DELAY


95/128

95ECSE-221B

Propagation delay is defined as the interval between the

application of the input signal and the point at which theoutput produces a stable response.

Consider the case of the 2-input multiplexer. The

propagation delay is exactly 2 gate delays because of theNAND-NAND logic circuit (assuming S is stable).

The 4-input multiplexer, made from two 2-input

multiplexers, adds an additional 2 units of delay.One can fabricate an 8-input multiplexer, by combining two

4-input multiplexers using a 2-input multiplexers.


PROPAGATION DELAY cont.


96/128

96ECSE-221B

AB

2

2

2

2

2

2

2

2

2

2

2

2

select

16

inputmultiplexer

1

2

34 2 units of delay

2

2

2

stage

Total delay = Stage x 2 units of delay

= 8 units of delay


PROPAGATION DELAY cont.


97/128

97ECSE-221B

The structure corresponds to a BINARY TREE, where the

depth of the tree is given as:

Stages = Log2(# Inputs)

Each level of the tree corresponds to the propagation delayof a 2-input multiplexer, i.e., 2 gate delays.

Hence, a 256-input multiplexer built in this fashion wouldhave a propagation delay of 16 gate delays:

log2(256) = 8 stages

total delay = (# stages) x (delay per stage)

= (8) x (2) = 16 gate delay

4 inputs 2 stages8 inputs 3 stages16 inputs 4 stages


COMMON BUILDING BLOCKS - OVERFLOW DETECTOR


98/128

98ECSE-221B

The resulting minterm and maxtermexpressions are, respectively:

OF = A B + A B

= (B + ) (A + ) (A + B)

COMMON BUILDING BLOCKS OVERFLOW DETECTOR

Recall that overflow (OF) in 2s complement addition can be

determined from the sign of the most significant bit (MSB)

of the two arguments (A,B) and the resulting sum ().

A B OF

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 0

1 0 1 01 1 0 1

1 1 1 0

B

00 01 11 10

A 0 11 1

B

00 01 11 10

A 0 0 0 01 0 0 0


COMMON BUILDING BLOCKS - DECODERS


99/128

99ECSE-221B

As the name implies, a decoder takes an n-bit input andproduces 2n outputs, i.e., one output line is true per input

combination.The table shown below corresponds to a 3-bit decoder.

Inputs Outputs

S2 S1 S0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q00 0 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 1 0 0 0 0 0 0 1 0 0

0 1 1 0 0 0 0 1 0 0 0

1 0 0 0 0 0 1 0 0 0 0

1 0 1 0 0 1 0 0 0 0 0

1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0

0120 SSSQ

0121 SSSQ

0122 SSSQ

0123 SSSQ

0124 SSSQ 0125 SSSQ

0126 SSSQ

0227 SSSQ

On mintermper output


COMMON BUILDING BLOCKS DECODERcont.


100/128

100ECSE-221B

The circuit shown here matches the

input/output characteristics of the truthtable shown in the previous slide with one

minor exception the enable input (EN).

When enable is not asserted, i.e., logic 1 in

this case (notice the inversion bubble),

then outputs Q0..Q7 are all 0.Otherwise the decoder functions according to

the truth table shown in the previous slide.


COMMON BUILDING BLOCKS MULTIPLEXERcont.


101/128

101ECSE-221B

A Better Multiplexer

using the decoder

(less delay)

DECODER

0

11

1000

0000

0

0

0

0

0

0

0

1

1

1

1

1

D3

1

1

1

D3

D31 D3 NAND

1 0 1

1 1 0

1 0 1

1 1 0


COMMON BUILDING BLOCKS - ENCODERS


102/128

102ECSE-221B

The encoder performs the opposite function of the decoder,

it takes n inputs and produces m outputs, where n=2m

.

Inputs Outputs

I7 I6 I5 I4 I3 I2 I1 Q2 Q1 Q0

0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 1 0 0 1

0 0 0 0 0 1 0 0 1 0

0 0 0 0 1 0 0 0 1 1

0 0 0 1 0 0 0 1 0 0

0 0 1 0 0 0 0 1 0 1

0 1 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 1 1 1

n=2m m


COMMON BUILDING BLOCKS ENCODERS cont.


103/128

103ECSE-221B

Notice that the truth table does NOT contain 2n rows for all

possible input combination (i.e. 2

8

=256)!The implicit assumption is that only 1 input can be asserted at any

time.

Hence the logic equations corresponding to Q2, Q1, and Q0 are as

follows:

Q2 = I4 + I5 + I6 + I7

Q1 = I2 + I3 + I6 + I7

Q0 = I1 + I3 + I5 + I7


COMMON BUILDING BLOCKS - COMPARATORS


104/128

104ECSE-221B

A single-bit comparator takes 2 inputs A and B and asserts

one of the three outputs depending on whether:

A > B, A = B, or A < B, i.e.,

A Greater than B: G = 1 if and only if A > B

A Equal to B: E = 1 if and only if A = B

A Less than B: L = 1 if and only if A < B

Truth table

Inputs Outputs

A B G E L0 0 0 1 00 1 0 0 11 0 1 0 01 1 0 1 0


COMMON BUILDING BLOCKS COMPARATORS cont.


105/128

105ECSE-221B

Logic equations:

G = A BL = A B

E = A B + A B

Can be implemented with an AND gate, two invertersand an XNOR gate.


106/128

MODULE 2

COMBINATIONAL LOGIC

Wednesday, February 2nd 2011


In the implemented logic function, what is the value


107/128

107ECSE-221B

of the three output variables when A = 0 and B = 1?

1) 2) 3) 4)

20%

6%6%

69%1) L = 1; E = 1; G = 02) L = 1; E = 0; G = 0

3) L = 0; E = 0; G = 1

4) L = 1; E = 1; G = 0


In the implemented multiplexer shown below, what is


108/128

108ECSE-221B

the output variable Q if S2=S1=S0=1?

1) 2) 3) 4)

3%8%

19%

70%

DECODER

1) Q = D72) Q = D6

3) Q = 1

4) Q = D3


COMMON BUILDING BLOCKS FULL ADDER


109/128

109ECSE-221B

The truth table corresponds to

a FULL ADDER.

Using standard techniques, we

can derive a logic functiondescribing this table in either

of the two canonical forms.

Cin A B Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 11 1 1 1 1


COMMON BUILDING BLOCKS FULL ADDER cont.


110/128

110ECSE-221B

Notice that the expression for does not simplify in eithercanonical form.

= CinAB + CinAB + CinAB + CinAB

= (Cin+A+B)(Cin+A+B)(Cin+A+B)(Cin+A+B)

Cout = AB + CinB + CinA

= (A+B)(Cin+B)(Cin+A)

AB

00 01 11 10

Cin0 1 1

1 1 1

AB

00 01 11 10

Cin0 0 0

1 0 0

Cout AB

00 01 11 10

Cin

0 1

1 1 1 1

Cout AB

00 01 11 10

Cin

0 0 0 0

1 0

Cout does simply in both forms.


COMMON BUILDING BLOCKS FULL ADDERcont.


111/128

111ECSE-221B

Word Width Full Adders (awordis made ofn bits)

An n-bit full-adder can be fabricated by cascading togethern full-adder modules as shown above.

What are the PROPAGATION DELAYS corresponding to

and Co in each one-bit full adder?

3 gate delays for (negating inputs adds 1 delay)

2 gate delays for Co (there are no inverted inputs)


COMMON BUILDING BLOCKS cont.


112/128

112ECSE-221B

Then, what is the propagation delay for the n-bit adder?

(n-1) x 2 gate delays to propagate carry to the last full

adder in the chain (up to output Cn-2)

+

3 gate delays to produce the final sum (output n-1)

Total propagation delay = 2n + 1 gate delays


EXAMPLE: 7 SEGMENT DISPLAY


113/128

113ECSE-221B

These are common in counters, calculators, digital watches,

computer consoles, etc.

Principle: Seven light emitting diodes (lamps) separately

fed, with common return lead.

By lighting up different combinations

of the 7 segments, numerals and

some letters can be produced.




114/128

114ECSE-221B

The segments to be lit have no clear mathematical

relationship to numbers. They are related to numerals,

so a specially designed driving circuit is required.

Inputs Oct Display Code

B2 B1 B0 al a b c d e f g

0 0 0 0 1 1 1 1 1 1 00 0 1 1 0 1 1 0 0 0 0

0 1 0 2 1 1 0 1 1 0 1

0 1 1 3 1 1 1 1 0 0 1

1 0 0 4 0 1 1 0 0 1 1

1 0 1 5 1 0 1 1 0 1 1

1 1 0 6 1 0 1 1 1 1 1

1 1 1 7 1 1 1 0 0 0 0

?

B0

B1

B2

abcdefg

For displaying digits0 to 7 only




115/128

115ECSE-221B

Design Approach: Using standard technique, derive the 7 logicequations corresponding to the display code from the truth table.

A more straightforward approach is to use a 3-to-8 decoder as shownin the diagram below.

DECODER

BINARY -> OCTAL

a b c d e f g

1 5 2 14 76 4




116/128

116ECSE-221B

A 3-to-8 decoder is used to assert each octal code. Each

segment combines 1s (OR) or 0s (NOR), depending onwhich are fewer.

e.g. segment a is OFF for 1 & 4, therefore a = NOR(1,4)

segment e is ON for 0,2,6, therefore e = OR(0,2,6).


DIGITAL LOGIC TECHNOLOGIES cont.


117/128

118ECSE-221B

Programmable Array Logic (PALs)

Use to implement particular logic

functions with fewcomponents.

The PAL consists of a fixednumber of multiple-input AND

gates combined through ORterms.

Connections to each AND areprogrammable, so there isconsiderable flexibility in the

range of logic functions thatcan be implemented.

The only limitations is the fixednumber of minterms.




118/128

119ECSE-221B

The Programmable Logic Array (PLA) shown below is amore general structure than the PAL.

It is comprised of an AND plane and an OR plane.

In a PLA, connections areprogrammable in BOTHthe AND array and the OR

array.In a PAL, only the AND areprogrammable




119/128

120ECSE-221B

EXAMPLE:

Consider the following truth table:

The are seven unique terms with aleast one true value in the

outputs, so there will be sevencolumns in the AND planecorresponding to the minterms.

The number of rows in the ANDplane is three since there are

three inputs.There are three rows in the OR

plane since there are threeoutputs.

Inputs OutputsA B C D E F0 0 0 0 0 00 0 1 1 0 00 1 0 1 0 00 1 1 1 1 01 0 0 1 0 01 0 1 1 1 0

1 1 0 1 1 01 1 1 1 0 1

1

2

3

4

5

67




120/128

121ECSE-221B

Once programmed, the PLA has the circuit below.

1 2 3 4 5 6 7

AND

OR

BC

A

minterms

EF

D



( )


121/128

122ECSE-221B

READ-ONLY MEMORY (ROM)

Another form of structured logic that can be used to

implement logic functions is the read-only memory.It has a fixed set of locations usually set when being

fabricated that can be addressed and read.

There are also programmable ROM (PROM), and some that

can be erased and reprogrammed (EPROM).A ROM has N inputs (address lines) which can be used tospecify 2N memory locations. Each location is M bits wide,hence the output (data lines) has M lines.

address lines(input)

date lines(output)

N M



A ROM d l i f i di l f h h


122/128

123ECSE-221B

A ROM can encode a logic function directly from the truthtable with N inputs and M outputs. Each entry stores a

row of the truth table

ROMs are fully decoded: one full word for each possibleinput. So, a ROM always contains more entries than aPLA. As the number of inputs grows, the number ofentries grows exponentially. PLAs grow much slower withthe number of terms.

ROMs are however sometimes convenient when the logicfunction may change but the number of input and outputs

remains fixed.

address lines(input)

date lines(output)


LOOKUP TABLES

M lti l b d bi ti l l i


123/128

124ECSE-221B

Multiplexers can be used as combinational logic

Example: Full adder design using two 8-input multiplexers

Observe: multiplexer inputs are the output columns of thetruth table.

Can we be more clever?

C A B S Co0 0 0 0 00 0 1 1 0

0 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 1

1 1 1 1 1

1

23

4

5

6

7

0

Output results shown below is for [C,A,B]=[1,1,1]


LOOKUP TABLES cont.

M lti l bi ti l l i


124/128

125ECSE-221B

Multiplexers as combinational logic

S=B

S=B

S=B

S=BCo=0

Co=B

Co=B

Co=1

C A B S Co0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 1

1 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

C A B S

0 0 0 01 1

0 10 11 0

1 00 1

1 0

1 10 01 1

C A B Co

0 00 01 0

0 10 01 1

1 00 01 1

1 10 11 1


LOOKUP TABLES cont.

F ll dd d i i t 4 i t lti l


125/128

126ECSE-221B

Full adder design using two 4-input multiplexers

Can we implement using ROM?

S=B

S=B

S=B

S=B

Co=0

Co=B

Co=B

Co=1

Output results shown below is for [C,A,B]=[1,1,1]

C A B S

0 00 01 1

0 1 0 11 0

1 00 11 0

1 10 01 1

C A B Co

0 00 01 0

0 1 0 01 1

1 00 01 1

1 10 11 1


LOOKUP TABLES cont.

Direct implementation using ROM


126/128

127ECSE-221B

Direct implementation using ROM

Full adder design using a ROM

Inputs C, A, and B are used to form the 3-bit address to thePROM shown above, hence each input indexes a particularmemory cell.

C A B S Co0 0 0 0 00 0 1 1 0

0 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 1

1 1 1 1 1

Output results shown above is for [C,A,B]=[1,1,1]


LOOKUP TABLES cont.

Th ll di l d ith th t t


127/128

128ECSE-221B

The cells are correspondingly programmed with the outputsof the truth table.

If you used LogicWorks to generate a PROM, the entries tothis device would be, from lowest to highest address:0,2,2,1,2,1,1,3.

C A B S Co0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 1

1 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

1

2

3

0

2

21

1 Output results shown below is for [C,A,B]=[1,1,1]


Module 2 - Summary

Combinational Logic no memory


128/128

Combinational Logic no memory

Truth Table

Two Canonical forms: Minterms and Maxterms Karnaugh Map

Logic Minimization

Logic circuit using logical gates

Common building block

Multiplexer/Demultiplexer

Decoder/Encoder

Full adder

Overflow Detector

Segment Display

Digital Logic Technologies PALs & PLAs

ROM

module 2 - com bi national logic feb 2

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