IEEEJOURNALOFsOLIR-STATECIRCUITS,VOL.SC-3,NO.3, SEPTEMBER1968 285

N(IOS storage array has been described. This approachappears to be at an early stage in its development and,with appropriate work in this area, the future for thistypeof memory is bright.

ACKNOWLEDGMENT

The author wishes to thank J. D. Schmidt for hisoverall contributions and C. Ellenberger for processingthe devices.

REFERENCES[11 J . D. Schmidj, “In tegra ted MOS transistor random access

memory,” Sotzd Sta te Design , pp. 21–25~J anuary 1965.[21 P. Pleshko and L. M. TernIan, “An investigation of the

poten t ia l of MOS transistor memor ies,” IEEE !llan .s. Elec-tron ic Com puters, vol. EC-15, pp. 423-427, August 1966.

[31 S. Nissirn, G. V. Podraza, and D. E. Brewer, “Low powercomputer memory system,” 1967 Fall J oin t Com puter Conj.,AFIPS Proc. Washington , D. C.: Thompson , 1967, pp. 381-3W.

[41 D. Frohman-Bentchkowsky and L. Vadasz, “Computer -a ideddesign and character iza t ion of MOS in tegra ted circuit s,” 1968MS (7C Digest of Tech . Papers, vol. 11.

Modeling and Simulation of Insulated-Gate Field-EffectTransistor Switching Circuits

u

HAROLD SHICHMAN, MEMBER, IEEE, AND DAVID A. HODGES, MEMBER, IEEE

Abstract-A new equivalent circuit for the insulated-gate field-effect transistor (IGFET) is described. This device model is par-t icu la r ly usefu l for computer -a ided analysis of monolith ic in te-gra ted IGFET switch ing circu it s. The result s of computer simul-a t ions using the new equiva len t circu it a re in close agreemen twith exper imen ta l observa t ions. As an example of a pract ica l ap-plica t ion , simula t ion result s a re shown for an in tegra ted circu itIGFET memory cell.

I. INTRODUCTION

c

OMPUTER circuit analysis programs are signifi-cant aids to integrated circuit design becausethey can reduce or eliminate the expense and

delay of cut-and-try design approaches [1].Mathematical approximations, or models, for the elec-

trical characteristics of electronic devices are essentialin any circuit analysis procedure. A mathematical modelrepresented by a combination of circuit elements (re-sistances, capacitances, dependent sources, etc.) is calledan equivalent circuit. These representations of mathe-matical models are not necessary for computer-aidedcircuit analysis. However, they aid understanding, par-ticularly in the evolution of new circuit and deviceconcepts.This paper describes a new equivalent circuit for the

insulated-gate field-effect transistor (IGF’ET). The equiv-alent circuit has been used with good results for corn-

Manuscr ipt r eceived Apr il 1,1968.The authors a re with Bell Telephone Labora tor ies, Inc., Mur-

ray Hill, N. J ,

puter analysis of the dc and transient characteristics ofIGFET switching circuits. computer-aided analysistechniques have proven particularly useful for IGFETintegrated circuits because the behavior of these circuitsis often dominated by the nonlinear characteristics ofIGFETs and by multiple intradevice capacitances. Man-ual analysis of IGFET switching circuits usually re-quires gross approximations that can lead to invalidresults.The new IGFET model is used with a general-purpose

circuit analysis program that employs state-variabletechniques. The program derives first order differentialequations from input data defining circuit topologyand device parameters. The dc solution is obtained bysetting the derivatives in the differential equations equalto zero, and solving for the steady-state voltages usingan iterative function [2]. The transient solution isobtained by numerically integrating the complete set ofdifferential equations. A new technique for numericalintegration has been developed to reduce computer run-ning time for circuit analysis [3].

II. FEATURES OF THE MOnEL

The new IGFET model has several key features thatenhance its usefulness in computer-aided analysis ofintegrated circuits. Separate drain, gate, source, andsubstrate terminals are available. Full representation ofthe effect of substrate bias on gate threshold voltage isincluded. The model is equally applicable to both en-hancement-mode and depletion-mode devices, whether

286

p-channel or n-channel. Simulation results are valid forany combination of terminal voltages that do not causeelectrical breakdown in the actual device.The number of state variables generated in computer

analysis is minimized by making no distinction between“intrinsic” and “parasitic” elements in the equivalentcircuit. A minimum number of state variables is de-sirable to limit the computation time in circuit analysis.This approach has the further advantage of simplyingthe evaluation of the elements in the equivalent circuit.Equivalent circuit parameters may be evaluated either

with measurements, employing a curve tracer and ca-pacitance bridge, or with direct calculations from devicegeometry and material parameters. The above combina-tion of features is not available with previously reportedIGFET equivalent circuits [4], [5].

III. DEVICE ANALYSIS

The present approach to the modeling problem is in-fluenced by the nature of results desired in simulationand by the typical IGFET geometry in integrated circuitrealization. Because large-signal switching and recoverytimes are the transient characteristics of greatest in-terest, average values of device capacitances (ratherthan voltage-dependent representations) can be oftenused without undue sacrifice of accuracy. However, ifnecessary,, voltage-dependent capacitances may directlyreplace fixed capacitances in the equivalent circuit andin the computer program.Fig. 1 shows a typical short-channel IGFET such as

is used for switching and gating functions. Half or moreof the total gate area overlaps the heavily doped sourceand drain regions. When the capacitances of metallizedwiring and other parasitic elements are included, thedistributed gate-channel capacitance of the short-chan-nel device typically comprises less than one third of thetotal gate node capacitance. In this case, the gate-channel capacitance may be divided equally betweenthe lumped gate-source and gate-drain capacitances.Results shown elsewhere may be used if a more precisetreatment is necessary [6].At first glance, the above approach appears invalid

for the long-channel devices sometimes used as high-impedance load elements. The distributed gate-channelcapacitance of such devices comprises a large fractionof the total gate node capacitance. However, becausethe gate of an IGFET used as a load element is tiedto a fixed potential, the exact way in which the gate-channel capacitance is modeled has little influence onsimulation results. For simplicity, the gate capacitancemay be divided as for the short-channel devices.The foregoing simplifications are further justified

when one considers that waveforms at internal nodesof an IGFET integrated circuit are not readily observ-able because node capacitances are typically of theorder of 0.1 pF. At external nodes, packaging and ex-

IEEE JOURNALOF SOLID-STATECIRCUITS,SEPTEMBER1968MGEJ$EL INSULATING

~+ OXIDESOURCE> \ ~OR::N / ‘

/DRAIN-SUBSTRATEDEPLETION REGION /. ,

5-OHM. CM n- TYPE SUBSTRATE

25 !.lhlI I

Fig. 1. Cross-sect iona l view of a typica l in tegra ted-circu it IGFET.

ternal circuitry largely determine total capacitance load-ing and hence transient performance. It appears thatlittle additional insight into circuit performance can beobtained by a more detailed representation of gate-channel capacitance in practical IGFET integrated cir-cuit, Moreover, it would be particularly difficult to con-firm experimentally the validity of a more elaboraterepresentation.Practical IGFETs are observed to have a significant

output conductance as a result of channel-length modu-lation and electrostatic drain-source coupling. An ap-proximate representation of these effects is included inthe model.

Iv. IGFET EQUIVALENT CIRCUIT

Complete IGFET circuit models are shown in Figs. 2and 3 for n-channel and p-channel devices, respectively.Resistors RI and R2 represent the series resistance be-tween the ohmic contacts and the active region. R3 andR1 are the spreading resistances from source and drainjunctions into the substrate region. In many cases, thelumped resistances shown here are only a crude approxi-mation of reality. However, in typical operation, thevoltage drops across these elements are so small (in themillivolt range) that they have little effect on circuitperformance. CGS and CG~ are the two lumped compo-nents of gate capacitance, as previously discussed. Thevalue chosen for CGs and C~~ is one half of the gate-channel capacitance.The two diodes represent the junctions between the

drain and substrate and between the source and sub-strate, respectively. The capacitances CsD and Css, whichare drawn in dotted lines, are the depletion capacitancesof these junctions. They are shown separately in Figs.2 and 3 to define the capacitances Cs~ and C~s, whichwill be used later. The charge-control diode modelshown in Fig. 4 is used to characterize the source-to-substrate and drain-to-substrate junctions [7]. Note thatthe junction depletion capacitance is a part of themodel. The application of the charge-control modelpermits consideration of minority carrier charge storage,which is present if these junctions become forwardbiased.The dependent drain current source Id represents the

current flowing between the drain and source via the

SHICHMAN ANDHODGES: INSULATED-GATEFIELD-EFFECTSWITCHING

GATE

TDRAIN

53R2vsD csD

+

CGD +VGD

+

R3.SUBSTRATEo Id

+ vGsCGS _ R4

+

I I

SOURCE

Fig. 2. n-channel IGFET circuit modelconventions.

DRAIN

1 1

GATE

>

R2

+CGD _

4

VGD

id

CGS ;VGS

R!

+rJ--l

and polarity

-L+CSDVso–1

R3LSUBSTRATE

-LR4

–1

%s +%s+ --I 1

ASOURCE

Fig. 3. p-channel IGFET circuit model and polarityconventions.

I Vd+–

*ANODE

1 ‘(q-o”

Fig. 4. Charge-control diode model used to represent source-substrate and drain-substrate junctions.

VT= VTo+K2[(- VsD+~)l’2-V1’2] VSD>VSS

= VTO + K2[(-vss++)’/2-v’/2] lv~s>vso

id = KI (F I- F2)(I+YIVGS-VGDI)

[( )

o v&J < vTwhere Fl= VGS– VT 2 vG~2VT1

[)‘2= (:G@T 2 ‘:: ‘:]

I.lcw;K,. T ~ K2=~(&y2

Fig. 5. The de equations for p-channel and n-channel devices.

287

IINCREASINGI ‘GS I

+DRAIN VOLTAGE vG~- VGD

ABOVE KNEE:

Id=K, (VGS-VT)2 ([+ II VGS–VGDI )

Fig. 6. IGFET dra in volt age–cur ren t charar te;ist ics, showingthe effect of channel-length modulation.

channel. The equations relating Id to the various volt-ages and material parameters are shown in Fig. 5. Theequations were developed from results given elsewhere [8]through a change of variables and through the addi-tion of the term (1+ Z/VGs– VGDI) to represent channel-Iength modulation and electrostatic drain-source cou-pling. Fig. 6 illustrates that these effects result in a finiteslope of the characteristic curves, beyond pinchoff,which is proportional to the current at the pinchoffpoint. A more detailed representation of the drain cur-rent source may be used [9]. However, our experienceindicates that the equations shown here are adequatefor simulation of large signal switching circuits.The equations in Fig. 5, despite the complexity aris-

ing from the conditional equalities, are easily pro-grammed on a digital computer.

V. EXPERIMENTATION VERIITCATION

For confirmation of the validity of the model, thecascaded inverter circuit of Fig. 7 was simulated andthe results compared with experimental measurements.The devices used were discrete p-channel enhancement-mode IGFETs having a geometry similar to integrateddevices and with a separate substrate contact availableat a fourth lead. This permitted a common substrateconnection for all devices, as would be found in an in-tegrated circuit. All capacitances, as well as the con-stants All, K2, V~o) and 1 were measured. other deviceparameters were calculated from device geometry, diffu-sion specifications, and appropriate physical constants.The results of the measurements and the predicted

response for the output voltage of the cascaded invertercircuit are shown in Fig. 8. The dotted line” was obtainedexperimentally. The solid line was computed using theIGFET model and the circuit analysis program. A sin-gle curve shows the input for both the analytical andexperimental input signal. It should be noted that no

288 IEEE JOURNALOl?SOLID-STATECIRCUITS,SEPTEMBER1968

ALL DEVICES:

CGS= i.3pF RI=40Jl Ki= 2X10-4 A/V2

CGD= 1.3PF R2=40fl K2= .756v I12

csD = 2.4 PF R3 = IOOJ3 y=o.7v

css = 2.4PF R4=100n VT”. 1,1vJ= 0.1

Fig. 7. Cascade of two IGFET inver t er stages.

o—

<“IN

-1.0 -

---20 -

-3.0 -

-4.0 , I , 10 100 200 300400 500600

Fig. 8. Measured (dotted trace) and computed (solid trace)switching response of two-stage cascade.

shift of either vertical or horizontal axis was requiredto obtain the agreement between experimental andanalytic curves shown in Fig, 8. The computed outputis within 5 percent of the experimental result, whichwas taken with a chart recorder driven from a samplingoscilloscope. The computer time for this problem wasless than one minute using a GE 645.

VI. PRACTICALAPPLICATION OF IGFET MODEL

Fig. 9 is a photmmicrograph of an integrated circuitIGFET memory cell. Fig. 10 is a schematic of the mem-ory cell that shows the IGFET model substituted forthree of the devices on the right half of the cell. The20-pF capacitors and the 6.8-k~ resistors simulate theloading effect of other components that would be presentin a memory system. The predicted performance of thememory cell during the entire read–write cycle is shownin Fig. 11.The initial conditions are chosen such that the left side

of the flip-flop is conducting. The cycle begins when theword line W is brought down to zero volts. Currentflows out through the left-hand gating IGFET andbegins to charge the 20-pF digit line capacitance. Thewaveform is shown in the lower left corner of Fig 11.This signal is the input to a detector that generates alogic-level data output pulse.Following the read operation, a signal is. applied to

point D to write new information into the cell. The

Fig. 9. Photomicrograph of an in tegra ted-circu it IGFET mem-ory cell. Devices a re let t ered to cor respond to let ters shownin Fig, 10.

+10 KIS= 25 X 10-6 AIVZ

KtL= 2.5 XIO-6

1.06K,G= 10 X 10-6

1000

xq~

3

K2= .75v1Z2

QS 100 v~~ = 2.5 V

.22s

~=1”–9 s

.44y= 0.7V

100 1=011000

~.06 e

,“Yw&D

+----J + .-

1 II G I

I 4’”07

22

C IN PF

R IN OHMS

w

Fig, 10, IGFET memory cell circu it .

f-y”“0,;~oo80p&U.-.-J20 6,8 6k8 ~CPF k

-’k ‘ ‘~[ 2000 200 0 200

Fig. 11. Result s of two computer simula t ion runs. Solid t racesshow cell switch ing; dot t ed t races show cell r etu rn ing toor igina l sta te,

SHICHMAN ANDHODGES: lNsULATED-(MTEFIELD-EFFECTSWITCHING 289

solid traces show the drive signal and response whenthe desired change of state takes place. The dotted tracesshow the results of a second simulation in which thedrive signal was not adequate to cause the desired changeof state.The cell readout behavior and switching sensitivity,

as shown in Fig. 11, have been confirmed by experi-mental measurements. It should be noted that a directcomparison of experimental and analytical data at in-ternal nodes of this circuit is not practical. The capaci-tance of a probe would alter significantly the actualcircuit response.Less than

was requiredFig. 11.

three minutes of GE 645 computer timeto compute each set of curves shown in

LIST OF SYMBOLS

threshold voltage with and without source-substrate bias;channel surface potential = (2k T/q) ln(N/n,);carrier mobility in channel;capacitance per unit area of gate;channel width and length;dielectric constants of silicon and of gateinsulator;carrier concentration in substrate;gate insulator thickness;electronic charge;

1=?1, =

channel-length modulation constant;intrinsic concentration in substrate.

ACKNOWLEDGMENT

The authors are indebted to H. J. Boll and H. E.l.Yigh for providing experimental devices, to C. W. Wel-ler for technical assistance, and to G. T. Cheney andW. van Gelder for helpful discussions. Special thanksgo to J. H. Wuorinen for numerous useful ideas andcomments, as well as for encouragement and support.

REFERENCES

[11 F. F. Kuo, “Networli analysis by digital computer,” Proc.IEEE, vol. 54, pp. 820-829, June 1966,

[21 J. 1?.Traub, Iterative Methods for the Solu t ion of Equatwns.Englewood Cliffs, N. J .: Pren t ice-Hall, 1964.

[31 I. W. Sandberg and H. Shichman, “Numerical integration ofsystems of stiff nonlinear differential equations,” Bell S ’ys.T ech . J ., vol. 47, April 1668.

[41 H. K. J. Ihantola and J. L. Moll, “Design theory of a sur-face field-effect transistor,” S o2icl-S tate Electron ., pp. 423-430.1964.

[5] B. ‘D. Roberts and C. O. Harbourt, “Computer models ofthe field-effect transistor;’ Proc. IEEE, vol. 55, pp. 1921-1929,November 1967.

[61 C. T. Sah and H. C. Pao, “The effect s of fixed bulk cha rgeon the character ist ics of meta l-oxide-semiconductor t ran-sistors,” IEEE Tram . Electron Devices, vol. ED-13, pp.393-409, Apr il 1966.

[71 D. Koeh ler , “The charge-con t rol concept ,” Belt S VS . Tech . J .,vol. 46, pp. 523-576,March 1967.

[81 J. T. Wallms.rk and H. Johnson, Eds., Fiek-17flect Tran-sistors. Edgewood Cliffs, N. J ., Pren t ice-Hall, 1966, pp. 113-155.

[91 Il. Froman-Bentchkowsky and L. Vadasz, “Computer-aideddesign and characterization of MOS integrated circuits;’1968 LS SCC Digest of Tech . Papers, pp. 68-69.