modeling and design of on-chip inter-block decoupling capacitors for psn and emi reduction

IDEW’06 Barcelona, September 5, 2006 1

Modeling and design of on-chip inter-block decoupling capacitors

for PSN and EMI reduction

Josep Rius1 and Maurice Meijer2

UPC

2 Digital Design and Test Group Philips Research Laboratories, The Netherlands

1 Departament d’Enginyeria Electrònica Universitat Politècnica de Catalunya, Spain


Motivation

Featuresize[nm]

gate switching time [ps]

… 45 70 100 130 ….

10

This work concerns a model and design procedurefor on-chip MOS decaps targeting PSN and EMI reduction

high frequency content of PSN

Small gateswitching times

ChipPackagePCBPower supply

~mm

~ cm

~ 10cm

Dimensions comparable to the wavelength of the HF componentsEMI

On-chip decoupling capacitors (decaps)• Effective solution to reduce power supply noise (PSN)• Decreases current loops thereby reducing EMI• Design constraints: performance, leakage, …


Proposed Decap Model

Model characteristics:• Distributed RGC model to take into account HF effects • Gate leakage modeled by a voltage-dependent current source

(B)

rGGND

VDD

c

rB

n+n+

cB

p+ p+

GND

substrate

l

i(v) r

rG = poly gate resistance

r = channel resistance

c = gate to channel capacitance

cB = channel to substrate capacitance

rB = substrate resistance

i(v) = direct tunneling gate current

ALL PARAMETERS ARE PER UNIT LENGTH

NMOS decap:


Proposed Decap Model (cnt’d)

Model simplification:• Exploit symmetry of the decap• Poly gate resistance (rG) << channel resistance (r)• Channel-to-substrate capacitance (CB) neglected

(B)

GND

VDD

c

rB

n+n+p+ p+

GND

substrate

l

i(v) r

rG = poly gate resistance

r = channel resistance

c = gate to channel capacitance

cB = channel to substrate capacitance

rB = substrate resistance

i(v) = direct tunneling gate current

ALL PARAMETERS ARE PER UNIT LENGTH

NMOS decap:


MOS Decaps: Analytical Solution

2

02

v vrc I gv r

x t

Diffusion equation with proper boundary and initial conditions

VDD

GND

x

0 l

r, cv(x,t)

-l

i(v)

Gate leakageterm

Channelterm

Steady-state response can be separated into DC+AC solution

0 0cosh

( )cosh

DC DD

x grI Iv x V

g gl gr

cosh( , ) Re

coshAC M

j tx gr j rc

v x t V el gr j rc


Example DC response.

l = 10m , w = 3m, w = 3m, 65nm CMOS

Drop voltage along the channel increases with channel length

Drop voltage along the channel increases as tOX is reduced

Normalized distance alonga half of channel length

90nm CMOS

65nm CMOS

45nm CMOS

l = 5m

l = 10m

l = 20m

Normalized voltagealong the channel

+l0+l0


Example AC response. No leakage case

( , ) ( ) cos( )ACv x t A x t

2

rc

VM ejt

r, c

x+l0-l

v(x,t)

1.1

1

0.9

0.8 0 L

Normalized voltage along the channel

Amplitude A(x) changes along the channel. It depends on r and c as well as

0 L



0 l

maximum effective decap length


Example AC response. Leakage case

VM ejt

r, c

x+l0-l

v(x,t)

g

1.1

1

0.9

0.8 0 L


Now L can be approximated by

21

12

L

g gc c


0 L


L

0 l

Amplitude A(x) changes along the channel. It depends on r , c and g as well as

( , ) ( ) cos( )ACv x t A x t


Input Impedance of a MOS Decap

ZIN

r, c

2

1if Cl f

rcl

g 0 cothINZ Z l

0

rZ

g j c

r g j c

l

2

2

1LL C

grll f

rcl

if

Critical frequency at l=• The frequency that separates lumped and distributed behaviour• Lower critical frequency in case of gate oxide leakage

NO LEAKAGE: LEAKAGE:


1E-3

10E-3

100E-3

1E+0

10E+0

100E+0

1E+3

10E+3

100E+3 1E+6 10E+6 100E+6 1E+9 10E+9 100E+9

Frequency [Hz]

No

rma

lize

d R

es

ista

nc

e

45nm

65nm

90nm - no leakage

90nm Analytical modelPSTAR simulations

10E-3

100E-3

1E+0

10E+0

100E+0

1E+3

10E+3

100E+3 1E+6 10E+6 100E+6 1E+9 10E+9 100E+9

Frequency [Hz]

No

rmal

ized

Cap

acit

ance

45nm

65nm

90nm - no leakage

90nm

Analytical modelPSTAR simulations

Re

1

Im

EQU IN

EQUIN

R Z

CZ

EQU

EQU

R

C

R

lrC

lc

normalized

normalized

Normalized R and C as a function of frequency


Intra-block and Inter-block MOS decaps

Digital logic block System-on-Chip

• Intra-block decaps have constrained dimensions– For example, the are implemented in the standard-cell template

• Inter-block decaps do not suffer from this constraint– Typically, used for EMI reduction purposes


WS

(B)

Y

YVDD

LF

(A)

Z Z

GND

VDD

LF LF LF LF LF LF

Z Z Z Z Z Z Z

GND

VDD

VDD

Example Inter-Block Decap: Gate length must be limited


Stripe

VDD

GND

VDD

GND

VDD

Stripe

Finger

Example Inter-Block Decap: Fingers and Stripes


2

2

1 OXLC

OX

g r lf

r C l

LEAK OX DD OXI WL g V I

OX

OX

OX

r

C

g

I

WL

Inter-Block Decap Model Parameters

Channel sheet resistance [/□]

Gate capacitance per unit area [F/m2]

Gate oxide conductance per unit area [S/m2]

Gate current density per unit area [A/m2]

Critical frequency

Total gate-oxide leakage

Total gate area [m2]

• Model parameters are defined to be independent of length and width


Procedure for Optimum Inter-Block Decap Design

1. Define the total decoupling capacitance CDEC to be included in the IC

2. Determine the effective total area as

3. Obtain the gate length of a finger LF0 to get the maximum frequency fC for which the decap needs to perform

4. Define the number of gate fingers as

5. Obtain the gate length of a single decap as

6. Define the number of stripes as where WMAX is the maximum allowed gate width

7. Obtain the gate width of a single decap as

8. Calculate total leakage

DECC

OX

CA

C

20

20

1

OX FLC

OX F

g r Lf

r C L

0/ C Fn A L

/F CL A n

/ C MAXm A W

/S CW A m

LEAK C OX DD OXI A g V I


Example

• 90nm GP technology• Required decap CDEC = 1nF• Three gate-oxide thicknesses

90nm GP

1

10

100

1.00E+07 1.00E+08 1.00E+09 1.00E+10

fC [Hz]

LF

[u

m]

red : tox = 6.5 nmmagenta: tox = 5 nmblack: tox = 1.6 nm

90nm GP

0.0E+00

5.0E+04

1.0E+05

1.5E+05

2.0E+05

2.5E+05

3.0E+05

3.5E+05

1.00E+07 1.00E+08 1.00E+09 1.00E+10

fC [Hz]

Are

a to

tal

[um

2]

Results:• Area factor = 1.01 to 1.23• Total leakage current

– ILEAK = 1.1 mA

red : tox = 6.5 nmmagenta: tox = 5 nmblack: tox = 1.6 nm

Total decap area vs. fC

Gate length of a finger vs. fC


Conclusions

• Distributed decap model based on physical grounds• Relevant parameters for each technology node are easily obtained• Such parameters are independent of dimensions for inter-block decaps

• Critical Frequency fC qualifies decoupling performance• Defines the border between full and reduced decap performance• Relevant expressions have been derived

• Simple procedure to design inter-block decaps based on the proposed model

modeling and design of on-chip inter-block decoupling capacitors for psn and emi reduction

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