modeling a 4g lte system in matlab - mathworks.com coding mimo ofdm adapt everything . 3 why...
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1 © 2011 The MathWorks, Inc.
Modeling a 4G LTE System in MATLAB
Part 3: Path to implementation (C and HDL)
Houman Zarrinkoub PhD.
Signal Processing Product Manager
MathWorks
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LTE Downlink processing
Advanced
channel coding
MIMO OFDM
Adapt
Everything
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Why Engineers translate MATLAB to C today?
Integrate MATLAB algorithms w/ existing C environment
using source code or static libraries
Prototype MATLAB algorithms on desktops as
standalone executables
Accelerate user-written MATLAB algorithms
Implement C/C++ code on processors or hand-off to
software engineers
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Algorithm Design and
Code Generation in
MATLAB
With MATLAB Coder, design engineers can
• Maintain one design in MATLAB
• Design faster and get to C/C++ quickly
• Test more systematically and frequently
• Spend more time improving algorithms in MATLAB
Automatic Translation of MATLAB to C
verify /accelerate
iterate
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Java
visualization
graphics
nested functions
sparse
variable-sized data
arrays
struct
numeric
fixed-point
functions
complex
System objects
global
persistent
malloc
classes
MATLAB Language Support for
Code Generation
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Supported MATLAB Language
Features and Functions
Broad set of language features and functions/system
objects supported for code generation.
Matrices and
Arrays Data Types
Programming
Constructs Functions
• Matrix operations
• N-dimensional arrays
• Subscripting
• Frames
• Persistent variables
• Global variables
• Complex numbers
• Integer math
• Double/single-precision
• Fixed-point arithmetic
• Characters
• Structures
• Numeric classes
• Variable-sized data
• System objects
• Arithmetic, relational,
and
logical operators
• Program control
(if, for, while, switch )
• MATLAB functions and sub-functions
• Variable length argument lists
• Function handles
Supported algorithms
• > 400 MATLAB operators and
functions
• > 200 System objects for
• Signal processing
• Communications
• Computer vision
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Fixed-Point Design: Motivation
ASIC/FPGA or fixed-point DSP implementation
Saves power and/or cost
Introduces quantization errors
Integer + sign fractional
L
L-N N
Quantization overflow
Word length and Fraction Length must be specified
– For every variable
Degradation must be analyzed
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Doing Fixed-Point in C is Hard
No native fixed-point math libraries
No built-in overflow / underflow checks
No tools to determine optimal integer and fractional bits
No visualization of floating and fixed-point
representations
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Fixed-Point Specification in MATLAB
Quantizing data:
x_fxp = fi( x, 1, 16, 15) % 16 bits, 15 fractional bits
Architecture specification:
– 16,32,40 bits (DSP) vs flexible number of bits (FPGA)
– Arithmetic rules: full precision, keep MSB
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MATLAB Accelerates Fixed-Point Design
Streamline conversion of floating-point algorithms to fixed-point
– NumericTypeScope tool
Simulate fixed-point algorithms – Directly in MATLAB
– Handle large data sets
– Simulate with compiled-C-code speed
Generate efficient and portable C code with MATLAB Coder
– codegen command
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Path to implementation
Bring it all to Simulink
Elaborate your design
– Model System-level inaccuracies
– Compensate
– Add fixed-point
– Generate HDL
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12 © 2011 The MathWorks, Inc.
MATLAB to Hardware
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Analog I/O
Digital I/O
ARM
Bridge
DSP
Memory Memory
Memory
Customized interfaces to
peripherals
High-speed communication
interfaces to other
processors
Finite state machines,
digital logic, timing and
memory control
High speed, highly parallel
DSP Algorithms
FPGA Analog I/O
Digital I/O
ARM
Bridge
DSP
Algorithms
Memory Memory
Memory
We are going
to focus on
this use case
today
Why do we use FPGAs?
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FPGA Designer
Separate Views of DSP Implementation
System Designer
Algorithm Design
Fixed-Point
Timing and Control Logic
Architecture Exploration
Algorithms / IP
System Test Bench
Environment Models
Algorithms / IP
Analog Models
Digital Models
RTL Design
IP Interfaces
Hardware Architecture
RTL Verification
Functional Simulation
Static Timing Analysis
Timing Simulation
Behavioral Simulation
Back Annotation Implement Design
Map
Place & Route
Synthesis
Hardware
FPGA Requirements
Hardware Specification
Test Stimulus
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What we will learn today MATLAB to Hardware
Convert design to fixed-point
– Use Fixed-point Tool
– Use NumericTypeScope in MATLAB
– Verify against floating-point design
Serialize design
Implementation using HDL Coder
– Verify through software and/or hardware co-simulation
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OFDM Transmitter
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MATLAB to Hardware
ifft(x, 2048, 1)
Issue #1
– „x‟ is 2048x4 matrix
– MATLAB does 2048-pt FFT along first dimension
– Output is also 2048x4
– Cannot process samples this way in hardware!
– Serialize design
Issue #2
– MATLAB does double-precision floating-point arithmetic
– Floating point is expensive in hardware (power and area)
– Convert to fixed-point
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HDL Workflow
Floating Point Model – Satisfies System Requirements
Executable Specification
– MATLAB and/or Simulink Model
Model Elaboration – Develop Hardware Friendly Architecture in Simulink
– Convert to Fixed-Point Determine Word Length
Determine Binary Point Location
Implement Design – Generate HDL code using Simulink HDL Coder
– Import Custom and Vendor IP
Verification – Software co-simulation with HDL simulator
– Hardware co-simulation Verification
Implement Code Generation
Model
Elaboration
Contin
uous V
erific
atio
n
Floating Point
Model
System
Requirements
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Divide and conquer Save simulation data to use in development
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MATLAB-based FFT
Can be done
Resources
– 120 LUTs (1%)
– 32 Slices (1%)
– 0 DSP48s
Need 2048-point FFT
32-point FFT chokes
synthesis tool!
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Re-implement using Simulink blocks compare against original code
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Convert to fixed-point compare against original code
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What you just saw
Simulink Fixed-Point to
model fixed-point data types
– Word lengths
– Fraction lengths
Fixed-Point Tool – monitoring signal
min/max, overflow
– optimization of
data types
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Use original testbench to optimize settings
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Analyze BER to determine word length
Anything beyond
8 bits is “good
enough”
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Recall
ifft(x, 2048, 1)
Issue #1
– „x‟ is 2048x4 matrix
– MATLAB does 2048-pt FFT along first dimension
– Output is also 2048x4
– Cannot process samples this way in hardware!
– Serialize design
Issue #2
– MATLAB does double-precision floating-point arithmetic
– Floating point is expensive in hardware (power and area)
– Convert to fixed-point
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Serial & Fixed-point “HDL ready”
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Automatically Generate HDL Code Simulink HDL Coder
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What You Just Saw - Workflow Advisor
Program FPGA
Physical Design and Critical Path Highlighting
Generate HDL Code
Prepare Model For HDL Code Generation
Select ASIC, FPGA, Or FPGA Board Target
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What You Just Saw – Generated HDL Code
Readable, Portable
HDL Code
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LTE Frame Structure (FDD)
1 Frame = 10ms
10 sub-frames per frame
2 slots per sub-frame (1 slot = .5ms)
7 OFDM symbols per slot
– 2048 subcarriers in our simulation
– IFFT output sample time
0.5𝑚𝑠7
2048= 3.4877 × 10−8𝑠 𝐎𝐑 28.672𝑀𝐻𝑧
(30.72MHz after cyclic prefix)
#0 #1 #2 #3 #19 …..
10ms
0.5 ms
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Frame and Slot Structure
But we need a cyclic prefix
=> Choose to have 14 symbols/ms (1 sub-frame)
– Split into two slots of 7 symbols
30.72 MHz = 15000 * 2048
If we do 2048-length FFT, we can have 15 of
them per millisecond
25 * cdma2000 = 8 * W-CDMA = 30.72 MHz
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Review: Automatic HDL Code Generation
Readable, portable HDL code
Target ASIC and FPGA
Standard Simulink libraries
Push-button programming of
Xilinx and Altera FPGA
Optimize for area and speed
Code traceability between model
and code
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MATLAB® and Simulink®
System and Algorithm Design
Synthesizable
RTL
Behavioral Simulation
Implement Design
Map
Place & Route
Synthesis
Back Annotation
Verification
Static Timing Analysis
Timing Simulation
Functional Simulation
FPGA Hardware
FPGA Prototyping
Shorter iteration cycles
– Automatic HDL code generation
– Integrated HDL verification
Flexible automatic HDL
Code generation
– Speed Optimization
– Area Optimization
– Power saving options
– Resource utilization
– Validation models
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HDL Coder Generate VHDL and Verilog Code for FPGA and ASIC designs
HDL
Coder
MATLAB Simulink
Verilog and VHDL
Automatic floating-point to
fixed-point conversion
HDL resource optimizations
and reports
Algorithm-to-HDL traceability
Integration with simulation &
synthesis tools
New: MATLAB to HDL
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HDL Verifier Verify VHDL and Verilog code using cosimulation and FPGAs
Support for 15 Altera and
Xilinx FPGA boards
• Use with:
• HDL Coder
• Hand-written HDL code
New:
FPGA Hardware-in-the Loop Verification MATLAB Simulink
ModelSim® and Incisive®
Xilinx® and Altera® boards
HDL
Verifier
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HDL Workflow
Floating Point Model – Satisfies System Requirements
Executable Specification
– MATLAB and/or Simulink Model
Model Elaboration – Develop Hardware Friendly Architecture
– Convert to Fixed-Point Determine Word Length
Determine Binary Point Location
Implement Design – Generate HDL code using HDL Coder
– Import Custom and Vendor IP
Verification – Software co-simulation with HDL simulator
– Hardware co-simulation Verification
Implement Code Generation
Model
Elaboration
Contin
uous V
erific
atio
n
Floating Point
Model
System
Requirements
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Communications Prototyping with USRP2
UDP
UDP
MATLAB + Simulink
Communications Model
Gigabit Ethernet
USRP2
MATLAB and Simulink for
communications system design
and verification
– Behavioral modeling, fixed-point,
C/HDL code-gen
Reuse simulation model as
verification environment with
interface to USRP2 radio
Experiment and verify with real-
world signals and systems
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Summary
MATLAB is an ideal language for LTE
modeling and simulation
Communications System Toolbox extend
breadth of MATLAB modeling tools
You can accelerate simulation with a
variety of options in MATLAB
– Parallel computing, GPU processing,
MATLAB to C
Address implementation workflow gaps
with
– Automatic MATLAB to C/C++ and HDL
code generation
– Hardware-in-the-loop verification