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Lecture planCode & name of subject: 141402 Microprocessors & Microcontrollers

Unit no: 1

UNIT I

THE 8085 AND 8086 MICROPROCESSORS (9)

8085 Microprocessor architecture-Addressing modes- Instruction set-Programming the8085

1 INTRODUCTION TO MICROPROCESSOR BASED SYSTEM

The microprocessor is a semiconductor device (Integrated Circuit)manufactured by the VLSI (Very Large Scale Integration) technique. It includes the ALU,register arrays and control circuit on a single chip. To perform a function or useful task we haveto form a system by using microprocessor as a CPU and interfacing memory, input and outputdevices to it. A system designed using a microprocessor as its CPU is called a microcomputer.

The Microprocessor based system (single board microcomputer) consists of microprocessor asCPU, semiconductor memories like EPROM and RAM, input device, output device andinterfacing devices. The memories, input device, output device and interfacing devices are called

peripherals. The popular input devices are keyboard and floppy disk and the output devices areprinter, LED/LCD displays, CRT monitor, etc.

The above block diagram shows the organization of a microprocessor based system. In this

system, the microprocessor is the master and all other peripherals are slaves. The master controlsall the peripherals and initiates all operations.The work done by the processor can be classified into the following three groups.

1. Work done internal to the processor2. Work done external to the processor

3. Operations initiated by the slaves or peripherals.

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Unit no: 1The work done internal to the processors is addition, subtraction, logical operations, data transfer

Operations, etc. The work done external to the processor are reading/writing the memory andReading/writing the J/O devices or the peripherals. If the peripheral requires the attention of themaster then it can interrupt the master and initiate an operation.

The microprocessor is the master, which controls all the activities of the system. To perform a

specific job or task, the microprocessor has to execute a program stored in memory. The programconsists of a set of instructions. It issues address and control signals and fetches the instructionand data from memory. The instruction is executed one by one internal to the processor and basedon the result it takes appropriate action.

BUSES:

The buses are group of lines that carries data, address or control signals. The CPU Bus has multiplexed lines, i.e., same line is used to carry different signals.The CPU interface is provided to demultiplex the multiplexed lines, to generate chip selectsignals and additional control signals.

The system bus has separate lines for each signal.All the slaves in the system are connected to the same system bus. At any time instantcommunication takes place between the master and one of the slaves. All the slaves have tristatelogic and hence normally remain in high impedance state. Only when the slave is selected itcomes to the normal logic.

PERIPHERAL DEVICES:

The EPROM memory is used to store permanent programs and data. The RAM memory is used to store temporary programs and data. The input device is used to enter the program, data and to operate the system.

The output device is used for examining the results.Since the speed of I/O devices does not match with the speed of microprocessor, an interface

device is provided between system bus and I/O devices. Generally I/O devices are slowdevices.

Advantages of Microprocessor based system

1. Computational/processing speed is high.

2. Intelligence has been brought to systems.3. Automation of industrial processes and office administration.

4. Since the devices are programmable, there is flexibility to alter the system by changing thesoftware alone.5. Less number of components, compact in size and cost less. Also it is more reliable.

6. Operation and maintenance are easier.

Disadvantages of Microprocessor based System1. It has limitations on the size of data.2. The applications are limited by the physical address space.

3. The analog signals cannot be processed directly and digitizing the analog signals introduceserrors.

4. The speed of execution is slow and so real time applications are not possible.5. Most of the microprocessors does not support floating point operations.



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Unit no: 1

8085 Microprocessor:

The salient features of 8085 p are:

It is a 8 bit microprocessor.

It is manufactured with N-MOS technology.

It has 16-bit address bus and hence can address up to 216 = 65536 bytes (64KB) memorylocations through A0-A15. The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 AD7. Data bus is a group of 8 lines D0 D7. It supports external interrupt request.

A 16 bit program counter (PC)

A 16 bit stack pointer (SP)

Six 8-bit general purpose register arranged in pairs: BC, DE, HL. It requires a signal +5V power supply and operates at 3.2 MHZ single phase clock.

It is enclosed with 40 pins DIP (Dual in line package).

ARCHITECTURE:

The architecture of.8085 is shown in figure given below. The internalarchitecture of 8085 includes the ALU, timing and control unit, instruction register and

decoder, register array, interrupt control and serial I/O control.



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Unit no: 1

INTEL 8085 Pin Diagram & Description



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OPERATIONS PERFORMED BY 8085

The ALU performs the arithmetic and logical operations. The operations performed

by ALU of 8085 are addition, subtraction, increment, decrement, logical AND, OR, EXCLU8IVE -OR, compare, complement and left / right shift. The accumulator and temporaryregister are used to hold the data during an arithmetic / logical operation. After an operation theresult is stored in the accumulator and the flags are set or reset according to the result of theoperation.



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Unit no: 1

FLAG REGISTER:

There are five flags in 8085, which are sign flag (8), zero flag (Z), auxiliary carry

flag (AC), parity flag (P) and carry flag (CY). The bit positions reserved for these flags in theflag register

are shown in figure below.

After an ALU operation, if the most significant bit of the result is 1, then sign flag is set. The zeroflag is set, if the ALU operation results in zero and it is reset if the result is non-zero. In an

arithmetic operation, when a carry is generated by the lower nibble, the auxiliary carry flag is set.After an arithmetic or logical operation, if the result has an even number of 1 's the parity flag isset, other wise it is reset.If an arithmetic operation results in a carry, the carry flag is set otherwise it is reset. Among the five flags, the AC flag is used internally for BCD arithmetic and other

four flags can be used by the programmer to check the conditions of the result of an operation.

TIMING & CONTROL UNIT:

The timing and control unit synchronizes all the microprocessor operations with the clock andgenerates the control signals necessary for communication between the microprocessor and

peripherals.

INSTRUCTION REGISTER & DECODER:

When an instruction is fetched from memory it is placed in instruction register. Then it is decodedand encoded into various machine cycles.

REGISTER ARRAY:

Apart from Accumulator (A-register), there are six general-purpose programmable registers

B, C, D, E, H and L. They can be used as 8-bit registers or paired to store l6-bit data. The allowed pairs are B-C,

D-E and H-L. The temporary registers W and Z are intended for internal use of the processor and it cannot

be used by the programmer.

STACK POINTER (SP):

The stack pointer SP, holds the address of the stack top. The stack is a sequence of RAMmemory locations defined by the programmer. The stack is used to save the content of

registers during the execution of a program.

PROGRAM COUNTER (PC):

The program counter (PC) keeps track of program execution. To execute a program the



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Unit no: 1starting address of the program is loaded in program counter. The PC sends out an address to

fetch a byte of instruction from memory and increment its content automatically. Hence,when a byte of instruction is fetched, the PC holds the address of the next byte of theinstruction or next instruction.

Memory Program, data and stack memories occupy the same memory space. The total addressable

memory size is 64 KB.

Program memory - program can be located anywhere in memory. Jump, branch and call

instructions use 16-bit addresses, i.e. they can be used to jump/branch anywhere within 64 KB.All jump/branch instructions use absolute addressing. Data memory - the processor always uses 16-bit addresses so that data can be placed anywhere.

Stack memory is limited only by the size of memory. Stack grows downward.

First 64 bytes in a zero memory page should be reserved for vectors used by RST instructions.

Interrupts

The processor has 5 interrupts. They are presented below in the order of their priority (from

lowest to highest): INTRis maskable 8080A compatible interrupt. When the interrupt occurs the processor fetchesfrom the bus one instruction, usually one of these instructions:

One of the 8 RST instructions (RST0 - RST7). The processor saves current program counterinto stack and branches to memory location N * 8 (where N is a 3-bit number from 0 to 7supplied with the RST instruction). CALL instruction (3 byte instruction). The processor calls the subroutine, address of which isspecified in the second and third bytes of the instruction.

RST5.5 is a maskable interrupt. When this interrupt is received the processor saves the contentsof the PC register into stack and branches to 2CH (hexadecimal) address.

RST6.5 is a maskable interrupt. When this interrupt is received the processor saves the contents

of the PC register into stack and branches to 34H (hexadecimal) address. RST7.5 is a maskable interrupt. When this interrupt is received the processor saves the contentsof the PC register into stack and branches to 3CH (hexadecimal) address.

TRAP is a non-maskable interrupt. When this interrupt is received the processor saves thecontents of the PC register into stack and branches to 24H (hexadecimal) address.

All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5,

RST6.5 and RST7.5 interrupts can be enabled or disabled individually using SIM instruction.

Reset Signals

RESET IN: When this signal goes low, the program counter (PC) is set to Zero, p is reset andresets the interrupt enable and HLDA flip-flops.

The data and address buses and the control lines are 3-stated during RESET and because of

asynchronous nature of RESET, the processor internal registers and flags may be altered byRESET with unpredictable results.

RESET IN is a Schmitt-triggered input, allowing connection to an R-C network for power-onRESET delay. Upon power-up, RESET IN must remain low for at least 10 ms after minimum Vcc has been

reached.

For proper reset operation after the power up duration, RESET IN should be kept low aminimum of three clock periods.



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Unit no: 1 The CPU is held in the reset condition as long as RESET IN is applied. Typical Power-on

RESET RC values R1 = 75K, C1 = 1F.

RESET OUT: This signal indicates that p is being reset. This signal can be used to reset other

devices. The signal is synchronized to the processor clock and lasts an integral number of clockperiods.

Serial communication Signal

SID - Serial Input Data Line: The data on this line is loaded into accumulator bit 7 whenever aRIM instruction is executed.

SOD Serial Output Data Line: The SIM instruction loads the value of bit 7 of theaccumulator into SOD latch if bit 6 (SOE) of the accumulator is 1.

DMA Signals

HOLD: Indicates that another master is requesting the use of the address and data buses. The

CPU, upon receiving the hold request, will relinquish the use of the bus as soon as the completion

of the current bus transfer. Internal processing can continue. The processor can regain the bus only after the HOLD isremoved.

When the HOLD is acknowledged, the Address, Data RD, WR and IO/M lines are 3-stated.

HLDA: Hold Acknowledge: Indicates that the CPU has received the HOLD request and that itwill relinquish the bus in the next clock cycle.

HLDA goes low after the Hold request is removed. The CPU takes the bus one half-clock cycleafter HLDA goes low.

READY: This signal Synchronizes the fast CPU and the slow memory, peripherals.

If READY is high during a read or write cycle, it indicates that the memory or peripheral is

ready to send or receive data.

If READY is low, the CPU will wait an integral number of clock cycle for READY to go highbefore completing the read or write cycle.

READY must conform to specified setup and hold times.

Registers

Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and load/storeoperations.

Flag Register has five 1-bit flags.

Sign - set if the most significant bit of the result is set.

Zero - set if the result is zero.

Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the result.

Parity - set if the parity (the number of set bits in the result) is even.

Carry - set if there was a carry during addition, or borrow duringsubtraction/comparison/rotation.

General Registers

8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When used as a pair

the C register contains low-order byte. Some instructions may use BC register as a datapointer.



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Unit no: 1 8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When used as a pairthe E register contains low-order byte. Some instructions may use DE register as a data

pointer.

8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When used as a pair

the L register contains low-order byte. HL register usually contains a data pointer used toreference memory addresses.

Stack pointer is a 16 bit register. This register is always decremented/incremented by 2during push and pop.

Program counter is a 16-bit register.

INSTRUCTION EXECUTION AND DATA FLOW in 8085

The program instructions are stored in memory, which is an external device. To execute

a program in 8085, the starting address of the program should be loaded in program counter. The8085 output the content of program counter in address bus and asserts read control signal low.Also, the program counter is incremented.The address and the read control signal enable the

memory to output the content of memory location on the data bus. Now the content of data bus isthe opcode of an instruction. The read control signal is made high by timing and control unit after

a specified time. At the rising edge of read control signals, the opcode is latched intomicroprocessor internal bus and placed in instruction register.The instruction-decoding unit, decodes the instructions and provides information to timing and

control unit to take further actions.

INSTRUCTION FORMAT OF 8085

The 8085 have 74 basic instructions and 246 total instructions. The instruction set of 8085 isdefined by the manufacturer Intel Corporation. Each instruction of 8085 has 1 byte opcode. With8 bit binary code, we can generate 256 different binary codes. In this, 246 codes have been usedfor opcodes.

The size of 8085 instructions can be 1 byte, 2 bytes or 3 bytes. The 1-byte instruction has an opcode alone. The 2 bytes instruction has an opcode followed by an eight-bit address or data.

The 3 bytes instruction has an opcode followed by 16 bit address or data. While storing the 3bytes instruction in memory, the sequence of storage is, opcode first followed by low byte ofaddress or data and then high byte of address or data.

ADDRESSING MODESEvery instruction of a program has to operate on a data. The method of specifying the

data to be operated by the instruction is calledAddressing. The 8085 has the following 5 differenttypes of addressing.



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Unit no: 11. Immediate Addressing

2. Direct Addressing3. Register Addressing4. Register Indirect Addressing

5. Implied AddressingImmediate Addressing

In immediate addressing mode, the data is specified in the instruction itself. The data will be apartof the program instruction. All instructions that have I in their mnemonics are of Immediateaddressing type.

Eg. MVI B, 3EH - Move the data 3EH given in the instruction to B register.

Direct Addressing

In direct addressing mode, the address of the data is specified in the instruction. The data will bein memory. In this addressing mode, the program instructions and data can be stored in differentmemory blocks. This type of addressing can be identified by 16-bit address present in theinstruction.

Eg. LDA 1050H - Load the data available in memory location 1050H in accumulator.

Register AddressingIn register addressing mode, the instruction specifies the name of the register in which the data isavailable. This type of addressing can be identified by register names (such as A, B, ) in the

instruction.Eg. MOV A, B -Move the content of B register to A register.

Register Indirect AddressingIn register indirect addressing mode, the instruction specifies the name of the register in which the

address of the data is available. Here the data will be in memory and the address will be in theregister pair. This type of addressing can be identified by letter M present in the instruction.

Eg. MOV A, M - The memory data addressed by HL pair is moved to A register.

Implied Addressing

In implied addressing mode, the instruction itself specifies the type of operation and location ofdata to be operated. This type of instruction does not have any address, register name, immediate

data specified along with it.Eg. CMA - Complement the content of accumulator.

INSTRUCTION SET

The 8085 instruction set can be classified into the following five functional headings.

Group I - DATA TRANSFER INSTRUCTIONS:Includes the instructions that moves ( copies) data between registers or between memory

locations and registers. In all data transfer operations the content of source register is not altered.Hence the data transfer is copying operation.Ex: i) MOV A,B ii) LDA 4600 iii) LHLD 4200

Group II - ARITHMETIC INSTRUCTIONS:

Includes the instructions which performs the addition, subtraction, increment or decrementoperations. The flag conditions are altered after execution of an instruction in this group.Ex: i) ADD B ii) SUB C iii) INR D iv) INX H



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Unit no: 1Group III - LOGICAL INSTRUCTIONS:

The instructions which performs the logical operations like AND, OR, Exclusive-OR,complement, compare and rotate instructions are grouped under this heading. The flag conditionsare altered after execution of an instruction in this group.

Ex: i) ORA B ii) XRA A iii) RAR

Group IV - BRANCHING INSTRUCTIONS:

The instructions that are used to transfer the program control from one memory location toanother memory location are grouped under this heading.Ex: i) JZ 4200 ii) RST 7 iii) CALL 4300

Group V - MACHINE CONTROL INSTRUCTIONS:

Includes the instructions related to interrupts and the instruction used to halt program execution.Ex: i) SIM ii) RIM iii) HLT

The 74 basic instructions of8085 are listed inTable. The opcode of each instruction, size,

machine cycles, number of T -state and the total number of instructions in each type are alsoshown in table in next page. The instructions affecting the status flag are listed in table followed



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TIMING DIAGRAM for various machine cyclesThe machine cycles are the basic operations performed by the processor, while

instructions are executed. The time taken for performing each machine cycle is expressed in

terms of Tstates. One T-state is the time period of one clock cycle of the microprocessor.The various machine cycles are1. Opcode fetch .. - 4 / 6 T

2. Memory Read . - 3 T3. Memory Write . - 3 T

4. I/O Read .. - 3 T5. I/O Write . - 3 T6. Interrupt Acknowledge - 6 / 12 T7. Bus Idle - 2 / 3 T



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PROGRAMMING EXAMPLES:

1. Write an ALP using 8085 to multiply two 8-bit numbers by repeated addition.

MVI A, OO ; Accumulator contents are clearedMVI C, OO ; C Register contents are clearedMVI B, data#1 ; I Operand is loaded into B RegisterMVI D, data#2 ; II Operand is loaded into D RegisterLoop: ADD B |JNC next |

INR C }Multiplication by repeated addition.Next: DCR D |JNZ loop |STA 4200H ; Storing of results into memory locationMOV A,C

STA 4201H ; Storing of carry into next memory location

3. Write an ALP using 8085 to evaluate the expression C=A2+B2

Let A be Data#1 and B be Data#2MVI B, Data#1 ; Data #1 is stored in register B

MOV C, B ; Copy of Data #1 is made in register CMVI D, Data#2 ; Data #2 is stored in register DMOV E,D ; Copy of Data #2 is made in register E

XRA A ;Accumulator content is clearedAgain: ADD B ]

DCR C }A2 is calculated by repeated Addition

JNZ Again ]MOV H,A ; Calculated A2 value is stored in register H

XRA A ;Accumulator content is clearedLoop: ADD D ]

DCR E }B2 is calculated by repeated AdditionJNZ Loop ]ADD H ;A2+ B2 is determined,

by adding result in A



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Unit no: 1and register content H

STA 4200H ;Result is stored in memory location 4200H



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Lecture plan

Code & name of subject: 141402 Microprocessors & Microcontrollers

Unit no: 2

UNIT II8086 SOFTWARE ASPECTS 9Intel 8086 microprocessor-Architecture-Signals-Instruction Set-Addressing Modes-Assembler

Directives-Assembly Language Programming-Procedures-Macros-InterruptsAnd Interrupt ServiceRoutines-BIOS function calls.Introduction to 8086 MicroprocessorFeatures:

Intel 8086 was launched in 1978.

It was the first 16-bit microprocessor.

This microprocessor had major improvement over the execution speed of 8085.

It is available as 40-pin Dual-Inline-Package (DIP).

It is available in three versions:a. 8086 (5 MHz)b. 8086-2 (8 MHz)c. 8086-1 (10 MHz)

It consists of 29,000 transistors.Architecture of 8086 Microprocessor



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Bus Interface Unit (BIU):The function of BIU is toFetch the instruction or data from memory.Write the data to memory.Write the data to the port.Read data from the port.

Instruction Queue

1. To increase the execution speed, BIU fetches as many as six instruction bytesahead to time from memory.2. All six bytes are then held in first in first out 6 byte register called instructionqueue.3. Then all bytes have to be given to EU one by one.4. This pre fetching operation of BIU may be in parallel with execution operation ofEU, which improves the speed execution of the instruction.



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Unit no: 2

Execution Unit (EU)

The functions of execution unit are

To tell BIU where to fetch the instructions or data from.To decode the instructions.To execute the instructions.

The EU contains the control circuitry to perform various internal operations. A decoder inEU decodes the instruction fetched memory to generate different internal or external controlsignals required to perform the operation. EU has 16-bit ALU, which can perform arithmetic andlogical operations on 8-bit as well as 16-bit.

General Purpose Registers of 8086

These registers can be used as 8-bit registers individually or can be used as 16-bit inpair to have AX,BX, CX, and DX.1. AX Register: AX register is also known as accumulator register that stores operands for

arithmetic operation like divided, rotate.2. BX Register: This register is mainly used as a base register. It holds the starting baselocation of a memory region within a data segment.3. CX Register: It is defined as a counter. It is primarily used in loop instruction to store loopcounter.4.DX Register: DX register is used to contain I/O port address for I/O instruction.

Segment RegistersAdditional registers called segment registers generate memory address when combined

with other in the microprocessor. In 8086 microprocessor, memory is divided into 4 segments asfollow:

1. Code Segment (CS): The CS register is used for addressing a memory location in the CodeSegment of the memory, where the executable program is stored.



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2. Data Segment (DS): The DS contains most data used by program. Data are accessed in theData Segment by an offset address or the content of other register that holds the offsetaddress.

3. Stack Segment (SS): SS defined the area of memory used for the stack.4. Extra Segment (ES): ES is additional data segment that is used by some of the string to holdthe destination data.

Flag Registers of 8086:

Flags Register determines the current state of the processor. They are modified automatically byCPU after mathematical operations, this allows to determine the type of the result, and todetermine conditions to transfer control to other parts of the program. 8086 has 9 flags and theyare divided into two categories:1. Conditional Flags2. Control Flags(1) Conditional FlagsConditional flags represent result of last arithmetic or logical instruction executed. Conditionalflags are as follows:

Carry Flag (CF)This flag indicates an overflow condition for unsigned integer arithmetic.It is also used inmultiple-precision arithmetic.Auxiliary Flag (AF):If an operation performed in ALU generates a carry/barrow from lower nibble (i.e. D0 D3)to upper nibble (i.e. D4 D7), the AF flag is set i.e. carry given by D3 bit to D4 is AF flag. Thisis not a general-purpose flag, it is used internally by the processor to perform Binary to BCDconversion.Parity Flag (PF):This flag is used to indicate the parity of result. If lower order 8-bits of the result contains even

number of 1s, the Parity Flag is set and for odd number of 1s, the Parity Flag is reset.Zero Flag (ZF):

It is set; if the result of arithmetic or logical operation is zero else it is reset.Sign Flag (SF):In sign magnitude format the sign of number is indicated by MSB bit. If theresult of operation is negative, sign flag is set.Overflow Flag (OF):It occurs when signed numbers are added or subtracted. An OF indicates that the result hasexceeded the capacity of machine.Control FlagsControl flags are set or reset deliberately to control the operations of the execution unit.



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Control flags are as follows:1. Trap Flag (TP):

It is used for single step control.

It allows user to execute one instruction of a program at a time for debugging. When trap flag is set, program can be run in single step mode.

2. Interrupt Flag (IF): It is an interrupt enable/disable flag.

If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the interrupt is

disabled.

It can be set by executing instruction sit and can be cleared by executing CLI

instruction.3. Direction Flag (DF):

It is used in string operation.

If it is set, string bytes are accessed from higher memory address to lower memory

address.

When it is reset, the string bytes are accessed from lower memory address to higher

memory address.

8086-Minimum mode of operation



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Unit no: 2

Minimum Mode InterfaceAddress/Data bus: 20 bits vs 8 bits multiplexedStatus signals: A16-A19 multiplexed with status signals S3-S6 respectively.S3 and S4 togetherform a 2 bit binary code that identifies which of the internal segment registers was used togenerate the physical address that was output on the address bus during the current bus cycle.S5 is the logic level of the internal interrupt enable flag, S6 is always logic 0.Control Signals:

Address Latch Enable (ALE) is a pulse to logic 1 that signals external circuitry when avalid address is on the bus. This address can be latched in external circuitry on the 1-to-0edge of the pulse at ALE.IO/M line: memory or I/O transfer is selected (complement for 8086)DT/R line: direction of data is selected

SSO (System Status Output) line: =1 when data is read from memory and =0 whencode is read from memory (only for 8088)BHE (Bank High Enable) line : =0 for most significant byte of data for 8086 and alsocarries S7RD line: =0 when a read cycle is in progressWR line: =0 when a write cyle is in progressDEN line: (Data enable) Enables the external devices to supply data to the processor.Ready line: can be used to insert wait states into the bus cycle so that it is extended by anumber of clock periods



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Interrupt signals:INTR (Interrupt request) :=1 shows there is a service request, sampled at the finalclock cycle of each instruction acquisition cycle.

INTA : Processor responds with two pulses going to 0 when it services the interrupt andwaits for the interrupt service number after the second pulse.TEST: Processor suspends operation when =1. Resumes operation when=0. Used tosyncronize the processor to external events.NMI (Nonmaskable interrupt) : A leading edge transition causes the processor go tothe interrupt routine after the current instruction is executed.RESET : =0 Starts the reset sequence.

Maximum Mode Interface For multiprocessor environment 8288 Bus Controller is used for bus control WR,IO/M,DT/R,DEN,ALE, INTA signals are not available.

o MRDC(memory read command)o MWRT(memory write command)o AMWC(advanced memory write command)o IORC(I/O read command)o IOWC(I/O write command)o AIOWC(Advanced I/O write command)o INTA(interrupt acknowledge)



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Addressing ModesA] Data Category B] Branch Category

Data Category:1)Immediate Addressing 2) Direct Addressing ( Segment Override prefix) 3) Registeraddressing 4) Register Indirect Addressing . 5)Register relative addressing.6)Base Indexaddressing 7)Relative base index addressing.

Branch Category:1) IntrasegmentDirect 2) IntersegmentIndirect.

Instruction SetWe only cover the smallsubset of the 8088 instruction set that is essential. In particular, we willnot mention various registers, addressing modes and instructions that could often provide fasterways of doing things.A summary of the 80x86 protected-mode instruction set is available on thecourse Web page and should be printed out if you dont have another reference.

Data Transfer



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The MOV instruction is used to transfer 8 and 16-bit data to and from registers. Either the sourceor destination has to be a register. The other operand can come from another register, frommemory, from immediate data (a value included in the instruction) or from a memory location

pointed at by register BX.

For example, if COUNT is the label of a memory location the following are possible assembly-language instructions :

; register: move contents of BX to AXMOV AX,BX

; direct: move contents of AX to memoryMOV COUNT,AX

; immediate: load CX with the value 240

MOV CX,0F0H

; memory: load CX with the value at; address 240MOV CX,[0F0H]

; register indirect: move contents of AL; to memory location in BXMOV [BX],AL

Most 80x86 assemblers keep track of the type of each symbol and require a type override whenthe symbol is used in a different way. The OFFSET operator to convert a memory reference to a

16-bit value.

For example:MOV BX,COUNT ; load the value at location COUNTMOV BX,OFFSET COUNT ; load the offset of COUNT16-bit registers can be pushed (the SP is first decremented by two and then the value stored at SP)or popped (the value is restored from the memory at SP and then SP is incremented by 2).

For example:PUSH AX ; push contents of AXPOP BX ; restore into BX

There are some things to note about Intel assembly language syntax: the order of the operands is destination,source the reverse of that used on the 68000!

semicolons begin a comment

the suffix H is used to indicate a hexadecimal

constant, if the constant begins with a letter it

must be prefixed with a zero to distinguish it

from a label the suffix B indicates a binary constant

square brackets indicate accesses to memory

the size of the transfer (byte or word) is determined



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by the size of the destination

I/O Operations

The 8086 has separate I/O and memory address spaces. Values in the I/O space are accessed withIN and OUT instructions. The port address is loaded into DX and the data is read/written to/fromAL or AX:MOV DX,372H ; load DX with port addressOUT DX,AL ; output byte in AL to port ; 372 (hex)IN AX,DX ; input word to AX

Arithmetic/LogicArithmetic and logic instructions can be performed on byte and 16-bit values. The first operandhas to be a register and the result is stored in that register.; increment BX by 4ADD BX,4

; subtract 1 from ALSUB AL,1; increment BXINC BX; compare (subtract and set flags ; but without storing result)CMP AX,[MAX]; mask in LS 4 bits of ALAND AL,0FH; divide AX by twoSHR AX; set MS bit of CXOR CX,8000H

; clear AXXOR AX,AX

Control TransferConditional jumps transfer control to another address depending on the values of the flags in theflag register. Conditional jumps are restricted to a range of -128 to +127 bytes from the nextinstruction while unconditional jumps can be to any point.; jump if last result was zero (two values equal)JZ skip; jump if carry set (below)JC neg; jump on carry not set

JNC smaller; unconditional jump:JMP loopThe assembly-language equivalent of an if statement in a high-level language is a CoMPareoperation followed by a conditional jump.

The CALL and RET instructions call and return from subroutines. The processor pushes IP on thestack during a CALL instruction and the contents of IP are popped by the RET instructions.For example:



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CALL readchar...readchar:

...RET

Segment/Offset AddressingSince address registers and address operands are only 16 bits they can only address 64k bytes. Inorder to address the 20-bit address range of the 8086, physical addresses (those that are put on theaddress bus) are always formed by adding the values of one of the segment registers to the 16-bitaddress to form a 20- bit address. The segment registers themselves only contain themost-significant 16 bits of the 20-bit value that is contributed by the segment registers. The leastsignificant four bits of the segment address are always zero.

By default, the DS (data segment) is used for data transfer instructions (e.g. MOV), CS (codesegment) is used with control transfer instructions (e.g. JMP or CALL), and SS is used with thestack pointer (e.g. PUSH or to save/restore addresses during CALL/RET or INT instructions).

The use of segment registers reduces the size of pointers to 16 bits. This reduces the code size butalso restricts the addressing range of a pointer to 64k bytes. Performing address arithmetic withindata structures larger than 64k is awkward. This is the biggest drawback of the 8086 architecture.We will restrict ourselves to short programs where all of the code, data and stack are placed intothe same 64k segment (i.e. CS=DS=SS).

Interrupts and ExceptionsIn addition to interrupts caused by external events (such as an IRQ signal), certain instructions

such as a dividing by zero or the INT instruction generate exceptions.The 8086 reserves the lower 1024 bytes of memory for an interrupt vector table. There is one4-byte vector for each of the 256 possible interrupt/exception numbers. When an interrupt orexception occurs, the processor: (1) clears the interrupt flag in the flags register, (2) pushes theflags register, CS, and IP (in that order), (3) loads IP and CS (in that order) from the appropriateinterrupt vector location, and (4) transfers control to that location. For external interrupts (IRQ orNMI) the interrupt number is read from the data bus during an interrupt acknowledge bus cycle.For internal interrupts (e.g. INT instruction) the interrupt number is determined from theinstruction.The INT instruction allows a program to generate any of the 256 interrupts. Thissoftware interrupt is typically used to access operating system services.

Pseudo-Ops

A number of assembler directives (pseudo-ops) are also required to write assembly languageprograms.ORG specifies the location of code or data within the segment, DB and DW assemblebytes and words of constant data respectively.

Assembler Directives :

ASSUME DB - Defined Byte.



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DD - Defined Double Word DQ - Defined Quad Word DT - Define Ten Bytes

DW - Define Word

ASSUME Directive - The ASSUME directive is used to tell the assembler that the name of thelogical segment should be used for a specified segment. The 8086 works directly with only 4physical segments: a Code segment, a data segment, a stack segment, and an extra segment.

Example:ASUME CS:CODE ;This tells the assembler that the logical segment named CODE contains theinstruction statements for the program and should be treated as a code segment.ASUME DS:DATA ;This tells the assembler that for any instruction which refers to a data in thedata segment, data will found in the logical segment DATA.

DB - DB directive is used to declare a bytetype variable or to store a byte in memory location.Example:1. PRICE DB 49h, 98h, 29h ;Declare an array of 3 bytes, named as PRICE and initialize.2. NAME DB ABCDEF ;Declare an array of 6 bytes and initialize with ASCII code for letters3. TEMP DB 100 DUP(?) ;Set 100 bytes of storage in memory and give it the name as TEMP,but leave the 100 bytes uninitialized. Program instructions will load values into these locations.

DW - The DW directive is used to define a variable of type word or to reserve storage location oftype word in memory.Example:MULTIPLIER DW 437Ah ; this declares a variable of type word and named it asMULTIPLIER. This variable is initialized with the value 437Ah when it is loaded

into memory to run.EXP1 DW 1234h, 3456h, 5678h ; this declares an array of 3 words and initialized with specifiedvalues.STOR1 DW 100 DUP(0); Reserve an array of 100 words of memory and initialize all wordswith 0000.Array is named as STOR1.

END - END directive is placed after the last statement of a program to tell the assembler that thisis the end of the program module. The assembler will ignore any statement after an ENDdirective. Carriage return is required after the END directive.

ENDP - ENDP directive is used along with the name of the procedure to indicate the end of aprocedure to the assembler.

Example:SQUARE_NUM PROCE ; It start the procedure ;Some steps to find the square root of a numberSQUARE_NUM ENDP ;Hear it is the End for the procedure.

END - End ProgramENDP - End ProcedureENDS - End SegmentEQU - EquateEVEN - Align on Even Memory Address



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EXTRN

ENDS - This ENDS directive is used with name of the segment to indicate the end of that logic

segment.Example:CODE SEGMENT ;Hear it Start the logic segment containing code Some instructionsstatements to perform the logical operation.CODE ENDS ;End of segment named as CODE

EQU - This EQU directive is used to give a name to some value or to a symbol. Each time theassembler finds the name in the program, it will replace the name with the value or symbol yougiven to that name.Example:FACTOR EQU 03H ; you has to write this statement at the starting of your program and later inthe program you can use this as follows

ADD AL, FACTOR; When it codes this instruction the assembler will code it as ADDAL, 03HThe advantage of using EQU in this manner is, if FACTOR is used many no of times in aprogram and you want to change the value, all you had to do is change the EQU statement atbeginning, it will changes the rest of all.

EVEN - This EVEN directive instructs the assembler to increment the location of the counter tothe next even address if it is not already in the even address. If the word is at even address 8086can read a memory in 1 bus cycle.If the word starts at an odd address, the 8086 will take 2 buscycles to get the data. A series of words can be read much more quickly if they are at evenaddress. When EVEN is used the location counter will simply incremented to next address andNOP instruction is inserted in that incremented location.

Example:DATA1 SEGMENT ; Location counter will point to 0009 after assembler reads next statementSALES DB 9 DUP(?) ;declare an array of 9 bytesEVEN ; increment location counter to 000AHRECORD DW 100 DUP( 0 ) ;Array of 100 words will start from an even address for quickerread

DATA1 ENDSGROUP - Group Related SegmentsLABLENAMEOFFSET

ORG Originate

GROUP - The GROUP directive is used to group the logical segments named after the directiveinto one logical group segment.INCLUDE - This INCLUDE directive is used to insert a block of source code from the namedfile into the current source module.

PROC - ProcedurePTR- Pointer



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PUBLCSEGMENTSHORT

TYPE

PROC - The PROC directive is used to identify the start of a procedure. The term near or far isused to specify the type of the procedure.Example:SMART PROC FAR; This identifies that the start of a procedure named as SMART andinstructs the assembler that the procedure is far .SMART ENDP This PROC is used with ENDP to indicate the break of the procedure.

PTR- This PTRoperator is used to assign a specific type of a variable or to a label.Example:INC [BX] ; This instruction will not know whether to increment the byte pointed to by BX or a

word pointed to by BX.INC BYTE PTR [BX] ;increment the byte pointed to by BX This PTR operator can also be usedto override the declared type of variable . If we want to access the a byte in an arrayWORDS DW 437Ah, 0B97h,MOV AL, BYTE PTR WORDS

PUBLIC - The PUBLIC directive is used to instruct the assembler that a specified name or labelwill be accessed from other modules.Example:PUBLIC DIVISOR, DIVIDEND ;these two variables are public so these are available to allmodules.If an instruction in a module refers to a variable in another assembly module, we canaccess that module by declaring as EXTRN directive.

TYPE - TYPE operator instructs the assembler to determine the type of a variable anddetermines the number of bytes specified to that variable.Example:Byte type variable assembler will give a value 1Word type variable assembler will give a value 2Double word type variable assembler will give a value 4ADD BX, TYPE WORD_ ARRAY ; hear we want to increment BX to point to next word in anarray of words.

MACROS:Macros are just like procedures, but not really. Macros =ook like procedures, but they exist only

until your code is compiled, after = compilation all macros are replaced with real instructions. Ifyou = declared a macro and never used it in your code, compiler will =imply ignore it.emu8086.inc is a good example of how macros can be used, this file contains =everal macros tomake coding easier for you.

Macro definition:

name MACRO [parameters,...]



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ENDM

Unlike procedures, macros should be defined above the code that uses it, for example: =

MyMacro MACRO p1, p2, p3

MOV AX, p1MOV BX, p2MOV CX, p3

ENDM

ORG 100h

MyMacro 1, 2, 3

MyMacro 4, 5, DX

RET

The above code is expanded into:

MOV AX, 00001hMOV =X, 00002hMOV CX, 00003hMOV AX, 00004hMOV BX, =0005hMOV CX, DX

Some important facts about macros and procedures:

When you want to use a procedure you should use =B>CALL instruction, for example:

CALL MyProc =/FONT>

When you want to use a macro, you can just type its =ame. For example:

MyMacro =/FONT>

Procedure is located at some specific address in memory, and if you use the sameprocedure 100 times, the CPU will transfer control to this part of the memory. The



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control will be returned back to the program by RET instruction. The =B>stack is used tokeep the return address. The CALL instruction takes about 3 bytes, so the size of the

output executable file =rows very insignificantly, no matter how many time the procedureis used.

Macro is expanded directly in program's code. So if =ou use the same macro 100 times,the compiler expands the macro =00 times, making the output executable file larger andlarger, each time all instructions of a macro are inserted.

You should use stackor any general purpose registers to pass parameters to procedure.

To pass parameters to macro, you can just type them after the macro name. For example:

MyMacro 1, 2, 3

To mark the end of the macro ENDM directive is enough.

To mark the end of the procedure, you should type the same of the procedure before theENDP directive.

Macros are expanded directly in code, therefore if there are labels inside the macro definition youmay get "Duplicate declaration" error when macro is used for twice or more. To avoid suchproblem, use LOCAL directive followed by names of variables, labels or procedure names. Forexample:

MyMacro2 MACROLOCAL label1, label2

CMP AX, 2JE label1CMP AX, 3JE label2label1:

INC AX

label2:ADD AX, 2

ENDM

ORG 100h

MyMacro2



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MyMacro2

RET

AN INTRODUCTION TO INTERRUPTS

INTERRUPTS

There are two main types of interrupt in the 8086 microprocessor, internal and external hardwareinterrupts. Hardware interrupts occur when a peripheral device asserts an interrupt input pin of

the microprocessor. Whereas internal interrupts are initiated by the state of the CPU (e.g. divideby zero error) or by an instruction.

Provided the interrupt is permitted, it will be acknowledged by the processor at the end of thecurrent memory cycle. The processor then services the interrupt by branching to a special serviceroutine written to handle that particular interrupt. Upon servicing the device, the processor is theninstructed to continue with what is was doing previously by use of the "return from interrupt"instruction.

The status of the programme being executed must first be saved. The processors registers will besaved on the stack, or, at very least, the programme counter will be saved. Preserving thoseregisters which are not saved will be the responsibility of the interrupt service routine. Once the

programme counter has been saved, the processor will branch to the address of the serviceroutine.

Edge or Level sensitive Interrupts

Edge level interrupts are recognised on the falling or rising edge of the input signal. They aregenerally used for high priority interrupts and are latched internally inside the processor. If thislatching was not done, the processor could easily miss the falling edge (due to its short duration)and thus not respond to the interrupt request.

Level sensitive interrupts overcome the problem of latching, in that the requesting device holdsthe interrupt line at a specified logic state (normally logic zero) till the processor acknowledges

the interrupt. This type of interrupt can be shared by other devices in a wired 'OR' configuration,which is commonly used to support daisy chaining and other techniques.

Maskable Interrupts

The processor can inhibit certain types of interrupts by use of a special interrupt mask bit. Thismask bit is part of the flags/condition code register, or a special interrupt register. In the 8086



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microprocessor if this bit is clear, and an interrupt request occurs on the Interrupt Request input, itis ignored.

Non-Maskable Interrupts

There are some interrupts which cannot be masked out or ignored by the processor. These areassociated with high priority tasks which cannot be ignored (like memory parity or bus faults). Ingeneral, most processors support the Non-Maskable Interrupt (NMI). This interrupt has absolutepriority, and when it occurs, the processor will finish the current memory cycle, then branch to aspecial routine written to handle the interrupt request.

Advantages of Interrupts

Interrupts are used to ensure adequate service response times by the processing. Sometimes, withsoftware polling routines, service times by the processor cannot be guaranteed, and data may be

lost. The use of interrupts guarantees that the processor will service the request within a specifiedtime period, reducing the likelihood of lost data.

Interrupt Latency

The time interval from when the interrupt is first asserted to the time the CPU recognises it. Thiswill depend much upon whether interrupts are disabled, prioritized and what the processor iscurrently executing. At times, a processor might ignore requests whilst executing some indivisibleinstruction stream (read-write-modify cycle). The figure that matters most is the longest possibleinterrupt latency time.

Interrupt Response Time

The time interval between the CPU recognising the interrupt to the time when the first instructionof the interrupt service routine is executed. This is determined by the processor architecture andclock speed.

The Operation of an Interrupt sequence on the 8086 Microprocessor:

1. External interface sends an interrupt signal, to the Interrupt Request (INTR) pin, or an internalinterrupt occurs.

2. The CPU finishes the present instruction (for a hardware interrupt) and sends Interrupt

Acknowledge (INTA) to hardware interface.

3. The interrupt type N is sent to the Central Processor Unit (CPU) via the Data bus from thehardware interface.

4. The contents of the flag registers are pushed onto the stack.

5. Both the interrupt (IF) and (TF) flags are cleared. This disables the INTR pin and the trap orsingle-step feature.



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6. The contents of the code segment register (CS) are pushed onto the Stack.

7. The contents of the instruction pointer (IP) are pushed onto the Stack.

8. The interrupt vector contents are fetched, from (4 x N) and then placed into the IP and from (4x N +2) into the CS so that the next instruction executes at the interrupt service procedureaddressed by the interrupt vector.

9. While returning from the interrupt-service routine by the Interrupt Return (IRET) instruction,the IP, CS and Flag registers are popped from the Stack and return to their state prior to theinterrupt.

Multiple Interrupts

If more than one device is connected to the interrupt line, the processor needs to know to which

device service routine it should branch to. The identification of the device requesting service canbe done in either hardware or software, or a combination of both. The three main methods are:

1. Software Polling,2. Hardware Polling, (Daisy Chain),3. Hardware Identification (Vectored Interrupts).

Software Polling Determination of the Requesting Device

A software routine is used to identify the device requesting service. A simple polling technique isused, each device is checked to see if it was the one needing service.



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Having identified the device, the processor then branches to the appropriate interrupt-handling-routine address for the given device. The order in which the devices appear in the polling

sequence determines their priority.

DOS Function Calls



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AH 00H : Terminate a ProgramAH 01H : Read the Keyboard

AH 02H : Write to a Standard Output Device

AH 08H : Read a Standard Input without Echo

AH 09H : Display a Character StringAH 0AH : Buffered keyboard Input

INT 21H : Call DOS Function



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UNIT-III

MULTIPROCESSOR CONFIGURATIONS 9

Coprocessor ConfigurationClosely Coupled ConfigurationLoosely CoupledConfiguration8087 Numeric DataProcessorData TypesArchitecture8089 I/OProcessorArchitectureCommunication between CPU and IOP.

Each processor in the 80x86 family has a corresponding coprocessor with which it is

compatible.Math Coprocessor is known as NPX,NDP,FUP.

Numeric processor extension (NPX),Numeric data processor (NDP),

Floating point unit (FUP).

Compatible Processor and Coprocessor

Processors

1. 8086 & 80882. 80286

3. 80386DX

4. 80386SX5. 80486DX6. 80486SX

Coprocessors

1. 80872. 80287,80287XL3. 80287,80387DX

4. 80387SX5. It is Inbuilt

6. 80487SX



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8087 Numeric Data Processor:

Architecture of 8087

Control UnitExecution Unit



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Control UnitControl unit: To synchronize the operation of the coprocessor and the processor.

This unit has a Control word and Status word and Data Buffer

If instruction is an ESCape (coprocessor) instruction, the coprocessor executes it, if not



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the microprocessor executes.Status register reflects the over all operation of the coprocessor.

C3-C0 Condition code bits TOP Top-of-stack (ST)

ES Error summary

PE Precision error UE Under flow error OE Overflow error ZE Zero error

DE Denormalized error IE Invalid error

B Busy bit

B-Busy bit indicates that coprocessor is busy executing a task. Busy can be tested by

examining the status or by using the FWAIT instruction. Newer coprocessor

automatically synchronize with the microprocessor, so busy flag need not be testedbefore performing additional coprocessor tasks.

C3-C0 Condition code bits indicates conditions about the coprocessor.

TOP- Top of the stack (ST) bit indicates the current register address as the top of thestack.

ES-Error summary bit is set if any unmasked error bit (PE, UE, OE, ZE, DE, or IE) is

set. In the 8087 the error summary is also caused a coprocessor interrupt.

PE- Precision error indicates that the result or operand executes selected precision.

UE-Under flow error indicates the result is too large to be represent with the current

precision selected by the control word.

OE-Over flow error indicates a result that is too large to be represented. If this error ismasked, the coprocessor generates infinity for an overflow error.

ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or

non-zero number.

DE-Denormalized error indicates at least one of the operand is denormalized.



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IE-Invalid error indicates a stack overflow or underflow, indeterminate from (0/0,0,-0,etc) or the use of a NAN as an operand. This flag indicates error such as those produced

by taking the square root of a negative number.

CONTROL REGISTER

Control register selects precision, rounding control, infinity control.It also masks an unmasks the exception bits that correspond to the rightmost Six bits of

status register.

Instruction FLDCW is used to load the value into the control register.

IC Infinity control

RC Rounding control

PC Precision control

PM Precision control

UM Underflow mask

OM Overflow mask

ZM Division by zero maskDM Denormalized operand mask

IM Invalid operand mask

IC Infinity control selects either affine or projective infinity. Affine

allows positive

and negative infinity, while projective assumes infinity is unsigned.

INFINITY CONTROL

0 = Projective

1 = Affine

RC Rounding control determines the type of rounding.

ROUNDING CONTROL

00=Round to nearest or even

01=Round down towards minus infinity

10=Round up towards plus infinity

11=Chop or truncate towards zero

PC- Precision control sets the precision of he result as define in table



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PRECISION CONTROL

00=Single precision (short)

01=Reserved

10=Double precision (long)

11=Extended precision (temporary)

Exception Masks It Determines whether the error indicated by the exception

affects

the error bit in the status register. If a logic1 is placed in one of the

exception control bits,

corresponding status register bit is masked off.

Numeric Execution Unit

This performs all operations that access and manipulate the numeric data in

the

coprocessors registers.

Numeric registers in NUE are 80 bits wide.

NUE is able to perform arithmetic, logical and transcendental operations as

well as

supply a small number of mathematical constants from its on-chip ROM.

Numeric data is routed into two parts ways a 64 bit mantissa bus and

a 16 bit sign/exponent bus.

Data Types

Internally, all data operands are converted to the 80-bit temporary real

format.

We have 3 types.

Integer data type

Packed BCD data type

Real data type

Coprocessor data types

Integer Data Type

Packed BCD

Real data type

Converting a decimal number into a Floating-point number.

1) Converting the decimal number into binary form.

2) Normalize the binary number

3) Calculate the biased exponent.

4) Store the number in the floating-point format.



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Step Result

1) 100.25

2) 1100100.01 = 1.10010001 * 26

3) 110+01111111=10000101

4 ) Sign = 0

Exponent =10000101

Significand = 10010001000000000000000

In step 3 the biased exponent is the exponent a 26 or 110,plus a bias of

01111111(7FH)

,single precision no use 7F and double precision no use 3FFFH.

IN step 4 the information found in prior step is combined to form the

floating point no.

INSTRUCTION SET

The 8087 instruction mnemonics begins with the letter F which stands for

Floating

point and distinguishes from 8086.

These are grouped into Four functional groups.

The 8087 detects an error condition usually called an exception when it

executing an

instruction it will set the bit in its Status register.

TypesI. DATA TRANSFER INSTRUCTIONS.

II. ARITHMETIC INSTRUCTIONS.

III. COMPARE INSTRUCTIONS.

IV. TRANSCENDENTAL INSTRUCTIONS.

(Trigonometric and Exponential)

Data Transfers Instructions

REAL TRANSFER

FLD Load real

FST Store real

FSTP Store real and pop

FXCH Exchange registers

INTEGER TRANSFER

FILD Load integer

FIST Store integer

FISTP Store integer and pop

PACKED DECIMAL TRANSFER(BCD)



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FBLD Load BCD

FBSTP Store BCD and pop

Example

FLD Source- Decrements the stack pointer by one and copies a real number

from a

stack element or memory location to the new ST.

FLD ST(3) ;Copies ST(3) to ST.

FLD LONG_REAL[BX] ;Number from memory

;copied to ST.

FLD Destination- Copies ST to a specified stack position or to a specified

memory

location .FST ST(2) ;Copies ST to ST(2),and

;increment stack pointer.

FST SHORT_REAL[BX] ;Copy ST to a memory at a

;SHORT_REAL[BX]

FXCH Destination Exchange the contents of ST with the contents of a

specified

stack element.

FXCH ST(5) ;Swap ST and ST(5)

FILD Source Integer load. Convert integer number from memory to temporary-real

format and push on 8087 stack.

FILD DWORD PTR[BX] ;Short integer from memory at [BX].

FIST Destination- Integer store. Convert number from ST to integer and copy to

memory.

FIST LONG_INT ;ST to memory locations named LONG_INT.

FISTP Destination-Integer store and pop. Identical to FIST except that stack

pointer is

incremented after copy.

FBLD Source- Convert BCD number from memory to temporary- real format and

push on top of 8087 stack.

Arithmetic Instructions.

Four basic arithmetic functions:



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Addition, Subtraction, Multiplication, and

Division.

Addition

FADD Add real

FADDP Add real and pop

FIADD Add integer

Subtraction

FSUB Subtract real

FSUBP Subtract real and pop

FISUB Subtract integer

FSUBRSubtract real reversed

FSUBRP Subtract real and pop

FISUBRSubtract integer reversed

Multiplication

FMUL Multiply real

FMULP Multiply real and pop

FIMUL Multiply integer

Advanced

FABS Absolute value

FCHS Change sign

FPREM Partial remainder

FPRNDINT Round to integer

FSCALE Scale

FSQRT Square root

FXTRACT Extract exponent and mantissa.

Example

FADD Add real from specified source to specified destination Source can

be a stack

or memory location. Destination must be a stack element. If no source or

destination is

specified, then ST is added to ST(1) and stack pointer is incremented so that

the result ofaddition is at ST.

FADD ST(3), ST ;Add ST to ST(3), result in ST(3)

FADD ST,ST(4) ;Add ST(4) to ST, result in ST.

FADD ;ST + ST(1), pop stack result at ST

FADDP ST(1) ;Add ST(1) to ST. Increment stack

;pointer so ST(1) become ST.

FIADD Car_Sold ;Integer number from memory + ST



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FSUB - Subtract the real number at the specified source from the real number

at the

specified destination and put the result in the specified destination.

FSUB ST(2), ST ;ST(2)=ST(2) ST.

FSUB Rate ;ST=ST real no from memory.

FSUB ;ST=( ST(1) ST)

FSUBP - Subtract ST from specified stack element and put result in specified

stack

element .Then increment the pointer by one.

FSUBP ST(1) ;ST(1)-ST. ST(1) becomes new ST

FISUB Integer from memory subtracted from ST, result in ST.

FISUB Cars_Sold ;ST becomes ST integer from memory

Compare Instructions.

Comparison

FCOM Compare real

FCOMP Compare real and pop

FCOMPP Compare real and pop twice

FICOM Compare integer

FICOMP Compare integer and pop

FTST Test ST against +0.0

FXAM Examine ST

Transcendental Instruction.Transcendental

FPTAN Partial tangent

FPATAN Partial arctangent

F2XM1 2x - 1

FYL2X Y log2X

FYL2XP1 Y log2(X+1)

Example

FPTAN Compute the values for a ratio of Y/X for an angle in ST. The angle

must be

in radians, and the angle must be in the range of 0 < angle < /4. F2XM1

ComputeY=2x-1 for an X value in ST. The result Y replaces X in ST. X must be in the

range

0X0.5.

FYL2X - Calculate Y(LOG2X).X must be in the range of 0 < X < any Y

must be in the range -

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Unit no: 3

to FYL2X except that it gives more accurate results when compute log of a

number very

close to one.

Constant Instructions.

Load Constant Instruction

FLDZ Load +0.0

FLDI Load+1.0

FLDPI Load

FLDL2T Load log210

FLDL2E Load log2e

FLDLG2 Load log102

FLDLN2 Load loge2

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The communication between CPU and IOP may take different forms depending on theparticular computer considered. The sequence of operations during CPU and IOP

communication is shown in figure.



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The CPU sends a test I/O instruction to IOP to test the IOP path.

The responds by inserting a status word in memory location.

The CPU refers to the status word in memory. If everything is in order, the CPU

sends the start I/O instruction to start the I/O transfer.

The IOP accesses memory for IOP program.

The CPU can now continue with another program while the IOP is busy with theprogram. Both programs refer to memory by means of DMA transfer.



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When the IOP terminates the execution of its program, it sends an interrupt

request to the CPU.

The CPU then issues a read I/O instruction to read the status from the IOP.

The IOP transfers the status word to memory location.

The status word indicates whether the transfer has been completed satisfactorily

or if any error has occurred during the transfer.



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Unit no: 4UNIT-IV

I/O INTERFACING 9Memory interfacing and I/O interfacing with 8085parallel communication interfaceserial communication

interfacetimer-keyboard/display controllerinterrupt controllerDMA controller (8237)applicationssteppermotortemperature control..

Memory InterfacingThe memory is made up of semiconductor material used to store the programs and data.

Three types of memory is,

Process memory

Primary or main memory

Secondary memory

Typical EPROM and Static RAM

A typical semiconductor memory IC will have n address pins, m data pins (or output

pins).Having two power supply pins (one for connecting required supply voltage (V and theother for connecting ground).The control signals needed for static RAM are chip select (chip enable), read control(output enable) and write control (write enable).

The control signals needed for read operation in EPROM are chip select (chip enable)and read control (output enable).

Decoder

It is used to select the memory chip of processor during the execution of a program. No

of IC's used for decoder is,

2-4 decoder (74LS139)

3-8 decoder (74LS138)



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Number of Address Pins and Data Pins in Memory ICs

Example for Memory Interfacing

Consider a system in which the full memory space 64kb is utilized for EPROM memory.Interface the EPROM with 8085 processor.The memory capacity is 64 Kbytes. i.e

2^n = 64 x 1000 bytes where n = address lines. So, n = 16.

In this system the entire 16 address lines of the processor are connected to address input

pins of memory IC in order to address the internal locations of memory.

The chip select (CS) pin of EPROM is permanently tied to logic low (i.e., tied to ground).

Since the processor is connected to EPROM, the active low RD pin is connected to active

low output enable pin of EPROM.

The range of address for EPROM is 0000H to FFFFH.



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Lecture planCode & name of subject: 141402 Microprocessors & MicrocontrollersUnit no: 4

Programmable peripheral interface(8255):

Architecture of 8255:The parallel input-output port chip 8255 is also called as programmable peripheral inputoutput

port. The Intels 8255 is designed for use with Intels 8-bit, 16-bit and higher capability

microprocessors. It has 24 input/output lines which may be individually programmed in two

groups of twelve lines each, or three groups of eight lines. The two groups of I/O pins are named

as Group A and Group B. Each of these two groups contains a subgroup of eight I/O lines called

as 8-bit port and another subgroup of four lines or a 4-bit port. Thus Group A contains an 8-bit

port A along with a 4-bit port. C upper.The port A lines are identified by symbols PA0-PA7

while the port C lines are identified as PC4-PC7. Similarly, GroupB contains an 8-bit port B,containing lines PB0-PB7 and a 4-bit port C with lower bits PC0- PC3. The port C upper and

port C lower can be used in combination as an 8-bit port C. Both the port C are assigned the

same address. Thus one may have either three 8-bit I/O ports or two 8-bit and two 4-bit ports

from 8255. All of these ports can function independently either as input or as output ports. This

can be achieved by programming the bits of an internal register of 8255 called as control word

register ( CWR ). This buffer receives or transmits data upon the execution of input or outputinstructions by the microprocessor. The control words or status information is also transferred

through the buffer.



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The signal description of 8255 are briefly presented as follows :

PA7-PA0: These are eight port A lines that acts as either latched output or buffered input lines

depending upon the control word loaded into the control word register.

PC7-PC4 : Upper nibble of port C lines. They may act as either output latches or input buffers

lines.This port also can be used for generation of handshake lines in mode 1 or mode 2.



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PC3-PC0 : These are the lower port C lines, other details are the same as PC7-PC4 lines.

PB0-PB7 : These are the eight port B lines which are used as latched output lines or buffered

input lines in the same way as port A.

RD : This is the input line driven by the microprocessor and should be low to indicate read

operation to 8255.

WR: This is an input line driven by the microprocessor. A low on this line indicates write

operation.

CS : This is a chip select line. If this line goes low, it enables the 8255 to respond to RD and WR

signals, otherwise RD and WR signal are neglected.

A1-A0 : These are the address input lines and are driven by the microprocessor. These lines

A1-A0 with RD, WR and CS from the following operations for 8255. These addresslines are used for addressing any one of the four registers,i.e. three ports and a control word

register as given in table below.

In case of 8086 systems, if the 8255 is to be interfaced with lower order data bus, the A0 and

A1 pins of 8255 are connected with A1 and A2 respectively.

D0-D7 : These are the data bus lines those carry data or control word to/from the

microprocessor.

RESET : A logic high on this line clears the control word register of 8255. All ports are set as

input ports by default after reset.

Operational Modes of 8255There are two main operational modes of 8255:

1. Input/output mode 2. Bit set/reset mode

Input/Output ModeThere are three types of the input/output mode. They are as follows:

Mode 0

In this mode, the ports can be used for simple input/output operations without handshaking. If

both port A and B are initialized in mode 0, the two halves of port C can be either used together

as an additional 8-bit port, or they can be used as individual 4-bit ports. Since the two halves ofport C are independent, they may be used such that one-half is initialized as an input port while

the other half is initialized as an output port. The input output features in mode 0 are as follows:

1. O/p are latched. 2. I/p are buffered not latched. 3. Port do not have handshake or interrupt

capability.

Mode 1

When we wish to use port A or port B for handshake (strobed) input or output operation, we

initialise that port in mode 1 (port A and port B can be initilalised to operate in different

modes,ie, for eg, port A can operate in mode 0 and port B in mode 1). Some of the pins of port C

function as handshake lines.



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Lecture planCode & name of subject: 141402 Microprocessors & MicrocontrollersUnit no: 4For port B in this mode (irrespective of whether is acting as an input port or output port), PC0,

PC1 and PC2 pins function as handshake lines.

If port A is initialised as mode 1 input port, then, PC3, PC4 and PC5 function as handshake

signals. Pins PC6 and PC7 are available for use as input/output lines.

The mode 1 which supports handshaking has following features: 1. Two ports i.e. port A and Bcan be use as 8-bit i/o port. 2. Each port uses three lines of port c as handshake signal and

remaining two signals can be function as i/o port. 3. interrupt logic is supported. 4. Input and

Output data are latched.

Mode 2

Only group A can be initialised in this mode. Port A can be used for bidirectional handshake data

transfer. This means that data can be input or output on the same eight lines (PA0 - PA7). Pins

PC3 - PC7 are used as handshake lines for port A. The remaining pins of port C (PC0 - PC2) can

be used as input/output lines if group B is initialised in mode 0. In this mode, the 8255 may be

used to extend the system bus to a slave microprocessor or to transfer data bytes to and from a

floppy disk controller.

Bit Set/Reset (BSR) mode

In this mode only port b can be used (as an output port). Each line of port C (PC0 - PC7) can be

set/reset by suitably loading the command word register.no effect occurs in input-output mode.

The individual bits of port c can be set or reset by sending the signal OUT instruction to the

control register.

Control Word Format

Input/output mode format

Control Word format in input/output mode

The figure shows the control word format in the input/output mode. This mode is selected

by making D7 = '1' .

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