mixed mode entry and simulation tutorial

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Mixed Mode Entry and Simulation Tutorial

Table Of Contents Mixed Mode Entry and Simulation Tutorial...................................................................................... 1

Introduction .................................................................................................................................. 1 Creating New Design ................................................................................................................... 1 Creating New VHDL File.............................................................................................................. 2 Modifying Source Code................................................................................................................ 4 Adding Block Diagram Schematic................................................................................................ 5 Compiling Schematic ................................................................................................................. 13 Creating Hierarchical Schematic................................................................................................ 14 Generating Test Bench .............................................................................................................. 22 Simulating Design ...................................................................................................................... 25

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Introduction

This tutorial will teach you how to create designs with the Block Diagram Editor. We assume that you are familiar with the Active-HDL application. In this tutorial we will use the VHDL model description of a one bit adder to create a 3-bit adder with the Block Diagram Editor.

Creating New Design

1. The Active-HDL starts with the following window, that allows you to open an existing workspace or create a new one.

Select Create new workspace and click OK. The New Workspace wizard dialog will appear.

The wizard consists of one dialog in which you should provide a name and location for the new workspace.

Make sure that the Add New Design to Workspace checkbox is selected and click the OK button. As a result, the New Design Wizard will be invoked.

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2. In the first wizard dialog, select the Create an empty design option, and then click Next.

3. In the next wizard dialog, specify the desired synthesis and implementation tools for the current design. Choose the default family, block diagram configuration and VHDL as the default HDL language. Then click Next.

4. In the next wizard dialog, specify the name of the new design, and choose its destination folder as shown below:

Click Next.

5. The summary widow will appear. Click the Finish button to complete creation of the design.

Creating New VHDL File

1. As was mentioned before, the design will contain a 1-bit adder, whose interface will be generated in the next few steps. In the Design Browser window, double-click the icon labeled Add New File. The Add New File dialog will open. Go to the Wizards tab, and then select the VHDL Source Code Wizard icon.

2. The New Source File Wizard will start. When the first dialog appears, leave the default settings and click Next.

3. In the next dialog, type the name of the source file you are going to create (adder1) as shown in the figure below, and then click Next.

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4. In the next dialog, specify ports of the entity implementing a 1-bit adder. Click the New button and type the port name in the Name filed. Choose the port type from available Port direction options.

Create the following ports of the type: A in B in Cin in Sum out Cout out

Click the Finish button to complete creation of the source file.

The Design Browser window will contain the adder1.vhd file.

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This file contains the interface description of the model but no behavior specification is entered yet.

Modifying Source Code

1. Double-click the adder1.vhd file to open its contents, and type the following lines below the -- enter your statements here -- line:

Sum


Adding Block Diagram Schematic

Next you will create the 3-bit adder.

1. Double click the Add New File icon in the Design Browser to open the following window:

2. Type the adder3 name in the Name edit box, and choose the Block Diagram icon in the window. Click the OK button. The empty Block Diagram Editor window will appear.

Placing Symbols on Schematic

3. Click the button to open Symbols Toolbox where the previously compiled adder is represented by the appropriate symbol.

Click adder in the toolbox to display its symbol.

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4. Drag the symbol to the Block Diagram Editor window using the drag-and-drop method.

5. The symbol placed in the Block Diagram Editor window is shown above. Using the method described above, place two additional adder symbols as shown in the picture below.

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6. Draw nets between the Cout output and Cin input ports of the symbols. To do this, click the Cout port, and while holding the mouse button down, move the cursor to the Cin port. Release the button. Complete the schematic as shown below:

Creating Buses and Terminals

7. Clicking the small triangle next to the icon to expand the button. Choose the bus input terminal by clicking the appropriate icon.

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8. The cursor shape will change. Click the empty space of the editor window and place two output bus terminals as shown in the picture below. Press the Esc key to switch to the Select mode.

9. Assign terminal names. Click the terminal with the right mouse button and select Properties from the context menu.

10. Type the terminal name and the width of the bus connected with the terminal.

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11. In the Name edit box, type A and set the bus width 2 downto 0 in Index range edit boxes.

Specify the name B for the second bus terminal.

12. Place another input terminal (for wires) and name it as Cin. Look at the following picture:

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13. Draw a connection (wire) between the terminal and symbol as shown below:

14. Place the output bus terminal on the diagram as shown in the picture below. Name it as Sum and set its width to 2 downto 0 (see picture below):

Creating Connections

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In this part of the tutorial, we will connect the previously added terminals with unconnected pins of the symbols U1-U3.

15. By pressing the W key, draw the wires connected to the A, B ports of the adder symbols as it is shown in the following picture.

16. Double-click the wire to name its segment: for the U1 symbol, the wire connecting the A input pin should be named A(0), the wire

connecting the B input - B(0), for the U2 symbol, the wire connecting the A input pin should be named A(1), the wire

connecting the B input - B(1), for the U3 symbol, the wire connecting the A input pin should be named A(2), the wire

connecting the B input - B(2),

17. Place the output terminal and name it as Cout. Connect the terminal as shown below:

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18. The Sum pins of the adder symbols should be connected to the Sum bus. Connect the wires to the Sum pins and change their names appropriately:

Sum(0) for the U1 unit, Sum(1) for the U2 unit, Sum(2) for the U3 unit.

The following picture shows the complete diagram:

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Compiling Schematic

1. You can compile the entire schematic (3-bit adder). Right-click the adder3.bde file in the Design Browser window, and choose the Compile option.

After compilation, the Design Browser window should contain the following structure.

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As you can see above, the schematic created in the Block Diagram Editor has also a structural representation.

Creating Hierarchical Schematic

In the next step we will create a schematic where you will place the 3-bit adder symbol along with the digital display decoder.

1. Double-click the Add New File option in the Design Browser window to add a new BDE file.

2. Select the Block Diagram, type the Top name in the Name field, and click OK. A new, empty Block Diagram Editor window will open.

3. Click the icon to open Symbol Toolbox. The toolbox now contains two symbols: 3-bit and 1-bit adders.

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4. Click the 3-bit adder symbol (adder3), and drag it to the Block Diagram Editor window.

Creating Fubs

5. Click the icon representing a FUB. The cursor changes its shape to a . Move the mouse pointer to the point where you want to anchor the first corner of the fub, and then hold down the mouse button. While holding, move the mouse pointer to the point where you want to place the opposite corner of the fub (the one located on the opposite end of the diagonal). When you move the mouse pointer, a temporary fub outline is stretched between the fixed corner and the current location of the mouse pointer. Release the mouse button to anchor the other corner. Press the Esc key.

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6. Right-click the fub and select the Properties menu option to open the Fub Properties dialog box..

7. Change the Fub name from Fub1 to hex2led and click OK.

8. Click the button and draw a bus as follows:

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9. Double-click the bus to open the Bus Properties dialog.

10. Type the Hex name in the Segment edit box, and set the bus width 3 downto 0 in the Index range edit box.

Click OK to close the dialog.

Note, the bus and fub pin names have changed.

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11. In the next step, connect the Cout pin of the 3-bit adder with the bus, dragging the wire from the Cout pin to the bus line.

12. Name appropriate nets (wires and buses), and complete the diagram as shown in the picture below.

13. We need to connect the 7-bit output of the hex2led decoder. Click the icon representing bus output terminal, place it on the diagram, and press Esc when finished. Click the terminal symbol with the right mouse button, and choose the Properties option to change the terminal name and set the bus width. Type the Led name, and set the bus width: 6 downto 0. Click OK to close the dialog.

Draw the bus from the hex2led symbol to the LED bus terminal. The result is shown on the picture below.

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Specifying Source Code for Fubs

14. In the next step we will specify the architecture for the decoder. Click the fub with the right mouse button and choose Push from the context menu.

15. When the Create New Implementation dialog appears, choose the architecture type describing the decoder by selecting the VHDL Source Code icon, and click OK.

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16. The HDL Editor window will appear with the previously defined interface of the decoder. Complete the decoder description with appropriate instructions (see the next section of this document).

Using Language Assistant Templates

17. Click the icon to open the Language Assistant window. Switch to the HDL Editor and place the cursor between -- enter your statements here and end Hex2Led lines. In the Language Assistant window expand the Synthesis templates branch, and select the HEX2LED Converter template. Click it with the right mouse button, and choose the Use option from the context menu.

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The decoder code is inserted into the HDL Editor window. Compile the file and close the Language Assistant.

18. Open the top.bde file and specify input ports for the 3-bit adder. Place the following input terminals:

A(2:0), Bus terminal B(2:0), Bus terminal Cin, Input terminal

Next, connect terminals with the appropriate symbol pins (see below).

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19. Compile the entire design. Right-click the top.vhd file in the Design Browser window and select the Compile All command.

20. When the compilation passes successfully, the following structure in the Design Browser window should appear.

Generating Test Bench

1. Before simulation, you can create a test bench file. Right-click the top(top) unit and choose the Generate Test Bench option from the context menu.

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Using Test Bench Wizard

2. Choose the Single Process Testbench Type and click OK.

3. Since we are not reading any test vectors from file click the Next button.

4. In the next window accept the default names for the entity, architecture and folders.

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Click the Next button.

5. Finish Test Bench Generation by clicking the Finish button.

The file hierarchy should be as follows:

Modifying Test Bench Code

6. Complete the Test Bench with the stimulators. Double click the top_tb.vhd file and type the following lines:

Cin


7. After completing the test bench file you can compile it. In the test bench folder there is also a created simulation macro command file named TOP_TB_runtest.do. Its purpose is to automate design compilation and simulation processes. Open the file and type the following line at the end of the file:

run 600 ns

8. Save the file using the Save command from the File menu.

Simulating Design

Now you can perform the simulation of the design. In the Design Browser window right click the TOP_TB_runtest.do file and choose the Execute command from the context menu.

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Simulation results displayed in the Waveform Viewer window should be as follows:

Thank you for using Active-HDL.

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Mixed Mode Entry and Simulation Tutorial Introduction Creating New Design Creating New VHDL File Modifying Source Code Adding Block Diagram Schematic Compiling Schematic Creating Hierarchical Schematic Generating Test Bench Simulating Design

mixed mode entry and simulation tutorial

Documents

new design wizard

new file dialog

new workspace wizard

new vhdl file

new source file wizard

current design

simulating design

design option