mixed-mode bist based on column matching

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Mixed-Mode BIST Mixed-Mode BIST Based on Column Based on Column

MatchingMatching Petr FišerPetr Fišer

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OutlineOutline Introduction to BISTIntroduction to BIST State-of-the-art Methods State-of-the-art Methods Mixed-Mode BISTMixed-Mode BIST Column-Matching MethodColumn-Matching Method Experimental ResultsExperimental Results A Summary of That EverythingA Summary of That Everything ConclusionsConclusions What Could Be Done YetWhat Could Be Done Yet

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Introduction to BISTIntroduction to BISTThe BIST StructureThe BIST Structure

Generate test patternsGenerate test patterns

Apply the patterns to Apply the patterns to the circuitthe circuit

Evaluate the responseEvaluate the response

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Present BIST MethodPresent BIST Method

Mixed-Mode BISTMixed-Mode BIST Combination of pseudo-random and Combination of pseudo-random and

deterministic BISTdeterministic BIST The easy-to-detect faults are detected by The easy-to-detect faults are detected by

pseudo-random patternspseudo-random patterns Some patterns are generated Some patterns are generated

deterministically, to detect the hard-to-detect deterministically, to detect the hard-to-detect faultsfaults

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State-of-the-art MethodsState-of-the-art Methods ReseedingReseeding

The pseudo-random test patterns are generated The pseudo-random test patterns are generated by LFSR, more LFSR seeds are appliedby LFSR, more LFSR seeds are applied

Weighted Pattern BISTWeighted Pattern BISTChange the probability of occurrence of 1s and 0s Change the probability of occurrence of 1s and 0s

in the PR sequencein the PR sequence Bit-Fixing, Bit-Flipping, Row-matchingBit-Fixing, Bit-Flipping, Row-matching

Modify the PR patterns by additional logicModify the PR patterns by additional logic

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Mixed-Mode BISTMixed-Mode BIST Combination of Combination of

pseudo-random and pseudo-random and deterministic BISTdeterministic BIST

Two disjoint phasesTwo disjoint phases Simple control logicSimple control logic Simple design Simple design

processprocess

LFSR

Decoder

Switch

CUT

MISR

TPG

mode

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Column-MatchingColumn-Matching LFSR produces code wordsLFSR produces code words These have to be transformed into These have to be transformed into

deterministic patternsdeterministic patterns(computed by ATPG)(computed by ATPG)

=> => Output DecoderOutput Decoder

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Column-MatchingColumn-MatchingBasic PrincipleBasic Principle

Try to reorder test patterns, so that most of Try to reorder test patterns, so that most of the Decoder outputs will be implemented as the Decoder outputs will be implemented as wires – wires – A Column MatchA Column Match

This will be accomplished when the particular This will be accomplished when the particular columns of the LFSR and test matrix will be columns of the LFSR and test matrix will be equalequal

Direct matchDirect match – even the Switch logic is – even the Switch logic is eliminatedeliminated

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Column-MatchingColumn-MatchingExampleExample

10001001101011100101111111000010011110111100110010

0100110010011111110011001

1000100110001011000011001

0100110010011111110011001

C-Matrix

T-Matrix Pruned C-Matrix

PRPG Patterns

Test Patterns Output Decoder PLA

s

n

r

p

1 0 0 0 10 0 1 1 00 0 1 0 11 0 0 0 01 1 0 0 1

0 1 0 0 11 0 0 1 00 1 1 1 11 1 1 0 01 1 0 0 1

Output Decoder PLA

x - x y - y40 0 4

y0 = x4’ + x1y1 = x3’y2 = x2 x3’ + x2’ x4’y3 = x0’y4 = x4

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Mixed-Mode Column-Mixed-Mode Column-MatchingMatching

1.1. Simulate first Simulate first n n LFSR patternsLFSR patterns2.2. Determine undetected faultsDetermine undetected faults3.3. Compute a test for them (ATPG)Compute a test for them (ATPG)4.4. Design the Decoder producing test from Design the Decoder producing test from

LFSR patterns > LFSR patterns > nn

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10100010100010110110010111000111100011100011110111

Pseudo-randomsequence }Simulate Non-covered

faultsATPG Test

Vectors

1X0001010X110110001X

101001101101011 0000110000

(non-det)Deterministicsequence

} }x-x0 4 y-y0 4

LFSR

10100010100010110110010111010011011010110000110000

Final test sequence

ExampleExample

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LFSR

CUT

1

x0 x1 x2 x3 x4

y0 y1 y2 y3 y4

Deterministicmode

y = x0 0

’

’

y = xy = xy = xy = x +x

1 1

2 2

3 1

4 0 1+

ExampleExample

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Experimental ResultsExperimental ResultsColumn-Column-matchingmatching

Bit-fixingBit-fixing Row-matchingRow-matching

BenchBench TLTL GEsGEs TLTL GEsGEs TLTL GEsGEsc880c880 1 K1 K 10.510.5 1 K1 K 2727 1 K1 K 2121c1355c1355 2 K2 K 1515 3 K3 K 1111 2 K2 K 00c1908c1908 3 K3 K 7.57.5 4 K4 K 1212 4.5 K4.5 K 88c2670c2670 5 K5 K 172172 5 K5 K 121121 5 K5 K 119119c3540c3540 3 K3 K 7.57.5 4.5 K4.5 K 1313 4.5 K4.5 K 44c7552c7552 8 K8 K 586586 10 K10 K 186186 8 K8 K 297297s420s420 1 K1 K 24.524.5 1 K1 K 2828 -- --s641s641 4 K4 K 1515 10 K10 K 1212 10 K10 K 66s713s713 5 K5 K 16.516.5 -- -- 5 K5 K 44s838s838 6 K6 K 130130 10 K10 K 3737 -- --s1196s1196 10 K10 K 66 -- -- 10 K10 K 3636

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Experimental ResultsExperimental ResultsBench inps 100% FC TL (PR + Det.) M DM Overhead Time [s]

c2670 233 2.4 M 1 K + 1 K 193 173 19 % 166

c7552 207 > 100 M 7 K + 1 K 131 33 19 % 500

s420 34 165 K 3 K + 1 K 35 21 11 % 0.41

s641 54 200 K 3 K + 1 K 54 44 6 % 0.21

s713 54 300 K 3 K + 1 K 54 42 5 % 0.32

s838 67 > 100 M 1 K + 1 K 37 13 32 % 26.20

s1196 32 200 K 9 K + 1 K 32 28 1 % 0.04

s5378 214 80 K 20 K + 1 K 214 205 1 % 0.98

s9234 247 10 M 50 K + 1 K 208 138 8 % 350

s13207.1 700 100 K 10 K + 1 K 696 500 6 % 137

s15850.1 611 > 10 M 10 K + 1 K 478 346 9 % 812

s38417 1664 > 10 M 100 K + 2 K 1503 834 11 % 17 K

s38584.1 1464 > 1 G 100 K + 1 K 1464 1354 1 % 34

b07 50 200 K 10 K + 1 K 50 34 6 % 0.5

b12 126 5 M 10 K + 1 K 118 104 7 % 25

b14 277 > 100 M 100 M / 1 K 90 58 56 % 100 K

b15 485 > 100 M 1 M / 2 K 263 158 44 % 65 K

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What Has Not Been Said What Has Not Been Said Here YetHere Yet

Well, there were more problems that had to be Well, there were more problems that had to be solved:solved:

How to choose the lengths of the phasesHow to choose the lengths of the phases How to improve the fault coverage in the How to improve the fault coverage in the

pseudo-random phasepseudo-random phase How to generate test vectors. Or better - what How to generate test vectors. Or better - what

vectors to generatevectors to generate How to choose the columns to be matchedHow to choose the columns to be matched How to find out if a particular column match is How to find out if a particular column match is

possible to be donepossible to be done How to synthesize the Decoder logicHow to synthesize the Decoder logic

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How to choose the lengths How to choose the lengths of the phasesof the phases

Some trade-off has to be foundSome trade-off has to be found The PR-phase length influences fault coverage The PR-phase length influences fault coverage

achieved achieved number of undetected faults number of undetected faults number number of deterministic vectors to be generatedof deterministic vectors to be generated

The Deterministic phase length influences the The Deterministic phase length influences the design time and BIST area overheaddesign time and BIST area overhead

Fišer, P. - Kubátová, H.: Influence of the Test Lengths Fišer, P. - Kubátová, H.: Influence of the Test Lengths on Area Overhead in Mixed-Mode BIST, Proc. 9th on Area Overhead in Mixed-Mode BIST, Proc. 9th Biennial Baltic Electronics Conference (BEC'04), Biennial Baltic Electronics Conference (BEC'04), Tallinn (Estonia), 3.-6.10.2004, pp. 201-204Tallinn (Estonia), 3.-6.10.2004, pp. 201-204

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How to improve the fault How to improve the fault coverage in the pseudo-coverage in the pseudo-

random phaserandom phase What LFSR polynomial and seed to choose?What LFSR polynomial and seed to choose? Or a CA?Or a CA? Or to modify the patterns somehow?Or to modify the patterns somehow?

Fišer, P. - Kubátová, H.: Pseudorandom Testability - Study of the Fišer, P. - Kubátová, H.: Pseudorandom Testability - Study of the Effect of the Generator Type, ECI'04, Herľany, SR, 22.-Effect of the Generator Type, ECI'04, Herľany, SR, 22.-24.9.04, pp. 200-20524.9.04, pp. 200-205

Fišer, P. - Kubátová, H.: Improvement of the Fault Coverage of Fišer, P. - Kubátová, H.: Improvement of the Fault Coverage of the Pseudo-Random Phase in Column Matching BIST, Proc. the Pseudo-Random Phase in Column Matching BIST, Proc. 31th Euromicro Symposium on Digital Systems Design 31th Euromicro Symposium on Digital Systems Design (DSD'05), Porto, (Portugal), 30.8. - 3.9.05, pp. 56-63(DSD'05), Porto, (Portugal), 30.8. - 3.9.05, pp. 56-63

Fišer, P. - Kubátová, H.: Pseudorandom Testability - Study of the Fišer, P. - Kubátová, H.: Pseudorandom Testability - Study of the Effect of the Generator Type, Acta Polytechnica, Vol. 2, Effect of the Generator Type, Acta Polytechnica, Vol. 2, August 2005, CVUT, ISSN 1210-2709, pp. 47-54August 2005, CVUT, ISSN 1210-2709, pp. 47-54

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How to generate test How to generate test vectors.vectors.

Or better - what vectors to Or better - what vectors to generategenerate

It’s better to generate deterministic vectors It’s better to generate deterministic vectors having many don’t careshaving many don’t cares

And moreover – we can improve the result by And moreover – we can improve the result by generating more vectors per one fault. It costs generating more vectors per one fault. It costs time, but the area overhead is smallertime, but the area overhead is smaller

Well, it’s already done, there are positive Well, it’s already done, there are positive results, but no publication yet.results, but no publication yet.

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How to choose the columns How to choose the columns to be matchedto be matched

NP-hardNP-hard Heuristic methods have to be usedHeuristic methods have to be used Fast-search and Thorough-search methods proposedFast-search and Thorough-search methods proposed

Fišer, P. - Kubátová, H.: Survey of the Algorithms in the Fišer, P. - Kubátová, H.: Survey of the Algorithms in the Column-Matching BIST Method, Proc. 10th Column-Matching BIST Method, Proc. 10th International On-Line Testing Symposium 2004 International On-Line Testing Symposium 2004 (IOLTS'04), Madeira, Portugal, 12.-14.7.2004, pp. 181(IOLTS'04), Madeira, Portugal, 12.-14.7.2004, pp. 181

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How to find out if a How to find out if a particular column match is particular column match is

possible to be donepossible to be done NP-C, if don’t cares are present in the testNP-C, if don’t cares are present in the test B-Matrix based approachB-Matrix based approach

Fišer, P. - Hlavička, J. - Kubátová, H.: Fišer, P. - Hlavička, J. - Kubátová, H.: Column-Matching BIST Exploiting Test Column-Matching BIST Exploiting Test Don't-Cares. Proc. 8th IEEE Europian Test Don't-Cares. Proc. 8th IEEE Europian Test Workshop (ETW'03), Maastricht (The Workshop (ETW'03), Maastricht (The Netherlands), 25.-28.5.2003, pp. 215-216Netherlands), 25.-28.5.2003, pp. 215-216

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How to synthesize the How to synthesize the Decoder logicDecoder logic

Two-level Boolean minimizer requiredTwo-level Boolean minimizer required BOOM, FC-Min, BOOM-II developedBOOM, FC-Min, BOOM-II developed

Hlavička, J. - Fišer, P.: BOOM - a Heuristic Boolean Minimizer. Proc. Hlavička, J. - Fišer, P.: BOOM - a Heuristic Boolean Minimizer. Proc. International Conference on Computer-Aided Design ICCAD 2001, San International Conference on Computer-Aided Design ICCAD 2001, San Jose, California (USA), 4.-8.11.2001, pp. 439-442 Jose, California (USA), 4.-8.11.2001, pp. 439-442

Fišer, P. - Hlavička, J. - Kubátová, H.: FC-Min: A Fast Multi-Output Boolean Fišer, P. - Hlavička, J. - Kubátová, H.: FC-Min: A Fast Multi-Output Boolean Minimizer, Proc. 29th Euromicro Symposium on Digital Systems Design Minimizer, Proc. 29th Euromicro Symposium on Digital Systems Design (DSD'03), Antalya (TR), 1.-6.9.2003, pp. 451-454(DSD'03), Antalya (TR), 1.-6.9.2003, pp. 451-454

Fišer, P. - Hlavička, J.: BOOM - A Heuristic Boolean Minimizer, Computers Fišer, P. - Hlavička, J.: BOOM - A Heuristic Boolean Minimizer, Computers and Informatics, Vol. 22, 2003, No. 1, pp. 19-51 and Informatics, Vol. 22, 2003, No. 1, pp. 19-51

Fišer, P. - Kubátová, H.: Two-Level Boolean Minimizer BOOM-II, Proc. 6th Fišer, P. - Kubátová, H.: Two-Level Boolean Minimizer BOOM-II, Proc. 6th Int. Workshop on Boolean Problems (IWSBP'04), Freiberg, Germany, Int. Workshop on Boolean Problems (IWSBP'04), Freiberg, Germany, 23.-24.9.2004, pp. 221-22823.-24.9.2004, pp. 221-228

… … and moreand more

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ConclusionsConclusions Column-matching-based mixed-mode BIST Column-matching-based mixed-mode BIST

method has been presentedmethod has been presented Pseudo-random LFSR patterns are being Pseudo-random LFSR patterns are being

transformed into deterministic vectors generated transformed into deterministic vectors generated by ATPG by the Decoderby ATPG by the Decoder

We try to match as many of the Decoder outputs We try to match as many of the Decoder outputs as possible with its inputs, which yields no logic as possible with its inputs, which yields no logic necessary to implement these outputsnecessary to implement these outputs

Mixed-mode – two disjoint BIST phases introducedMixed-mode – two disjoint BIST phases introduced Many more “minor” problems involvedMany more “minor” problems involved

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What Could Be Done YetWhat Could Be Done Yet Adjust the width of a PRPGAdjust the width of a PRPG More sophisticated methods should be More sophisticated methods should be

found, to find a proper PRPGfound, to find a proper PRPG Incorporate the ATPG into the design Incorporate the ATPG into the design

process – iterative test computationprocess – iterative test computation Test-per-scan supportTest-per-scan support Partitioning of the CUTPartitioning of the CUT Combine CM-BIST with other methodsCombine CM-BIST with other methods

mixed-mode bist based on column matching

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