MASTER'S THESIS

Mitigation of GX209HA Processor forUsage in Space

Martin Strömgren2016

Master of Science in Engineering TechnologySpace Engineering

Luleå University of TechnologyDepartment of Computer Science, Electrical and Space Engineering

Mitigation of GX209HA processor

for usage in space

Luleå University of Technology

Department of Computer Science, Electrical and Space Engineering

Author:

Martin Strömgren

Supervisor:

Daniel Skaborn

Examiner:

Anita Enmark

This thesis report is presented for the degree Master of Science in Space engineering,

specialization Spacecraft and instrumentation

December 22, 2015

Abstract

This thesis aim to create rtl hardware to control the boot up of the commercial AMD GX209HA SOCprocessor. During this thesis the decision was made to boot GX209HA from a fault tolerant externalmemory over the SPI and use the LPC bus to control that the processor booted correctly. The SPIwas created to emulate the PCT25VF032B SPI �ash memory and a FIFO register was attached tothe SPI to store the data before it is being transmitted. To communicate with the main system aninterface to the internal wishbone bus was created for this hardware. The last piece of hardwareto be created was the LPC interface and the FIFO that will store the test codes from the BIOS ofthe processor. The created hardware functioned properly during simulation and the SPI interfacework for a linear transfer. However, the GX209HA processor start executing the instructions whilethe boot image is being transferred and will jump between addresses. The LPC interface receivesone test code before it get stuck, which has not been solved. Thermal interface materials has beeninvestigated and a list of thermal interface materials that pass the ESA outgassing restrictions hasbeen constructed.

Acknowledgements

I would like to thank ÅAC Microtec AB and Mattias Örth for giving me the opportunity to do mymaster thesis at their company. I would also like to thank my supervisor Daniel Skaborn for helpingme plan and execute this thesis. Stefan Strålsjö has given me an enormous amount of help withdesigning rtl, as well as simulating and testing the hardware I created, for which I am really grateful.I would also like to thank Jonas Antoni at Hectronic AB for helping me understand how the processorbehaves and how to handle it. I would like to thank my examiner Anita Enmark for preparing mefor this thesis. Finally a big thank you to my family and friends for supporting and helping me onthis journey.

i

Contents

Abstract i

Acknowledgements i

List of Figures iii

List of Tables iv

Abbreviations v

1 Introduction 11.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2 Report outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Theoretical background 42.1 Vacuum e�ects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.2 Radiation e�ect on electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.3 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 System 73.1 Serial Periferal Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.2 System design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.3 GX209HA boot control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.3.1 SPI Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.3.2 FIFO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.3.3 Wishbone interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.3.4 LPC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4 Thermal interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 Testing and result 144.1 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144.2 Testing SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154.3 Testing LPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.4 Thermal interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5 Conclusion 19

6 Future work 20

Bibliography 21

A RTL code 24

B Logical schematics 44

C Testing software 47

ii

List of Figures

1.1 How deep into the atmosphere di�erent wavelengths can penetrate. [7] . . . . . . . . . 1

2.1 Outgassing: di�usion followed by desorption. [9] . . . . . . . . . . . . . . . . . . . . . . 42.2 The connection between two surfaces on a micro scale. [22] . . . . . . . . . . . . . . . 6

3.1 An illustration of how the SPI devices may be designed in an eight bit transfer cycle. [21] 73.2 An overview of the overall system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.3 Timing schedule of the SPI transfer when in read mode. [23] . . . . . . . . . . . . . . . 93.4 An overview of the GX209HA boot control, as it is designed. . . . . . . . . . . . . . . 93.5 The SPI Management block functionality. . . . . . . . . . . . . . . . . . . . . . . . . . 113.6 The functionality of the WB interface block. . . . . . . . . . . . . . . . . . . . . . . . . 123.7 The functionality of the LPC interface block. . . . . . . . . . . . . . . . . . . . . . . . 13

4.1 Simulation result of the SPI. The names of the signals are rd_data_o (which is theMISO signal), clk_spi, SPI_MOSI, SPI_CS0, Rd_En and rd_data. . . . . . . . . . . 14

4.2 Simulation result of the WB interface. The names of the signals are WB_clk, rst_i,wb_dat_i, wb_dat_o, wb_addr_i, wb_ack_o and int_o. . . . . . . . . . . . . . . . 15

4.3 Simulation result of the LPC interface. The names of the signals are lreset_n, lclk,lframe_n, lad_i, lad_o, lad_oe, lpc_wr, lpc_data_re and lpc_ack. . . . . . . . . . . 15

4.4 The connection schematic of the SPI test. . . . . . . . . . . . . . . . . . . . . . . . . . 164.5 The connection schematic of the LPC test. . . . . . . . . . . . . . . . . . . . . . . . . 17

B.1 Logical schematic of SPI Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44B.2 Logical schematic of the WB Interface. The yellow boxes represent the FIFO registers. 45B.3 Logical schematic of the LPC Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . 46

iii

List of Tables

1.1 Comparison between the GX209HA and Rad-Hard processors. . . . . . . . . . . . . . 3

3.1 A short description of the �les in the component. . . . . . . . . . . . . . . . . . . . . . 103.2 The CVCM restriction for di�erent masses of a material according to ESA. [30] . . . . 13

4.1 Some of characteristics of the OBC-lite. FM stands for Flight Model, which is faulttolerant and EM is Engineering Model, which is not. [28] . . . . . . . . . . . . . . . . . 16

4.2 Some thermal interface material and their properties. . . . . . . . . . . . . . . . . . . . 17

iv

Abbreviations

AVS American Vacuum Society

BIOS Basic Input/Output System

CMOS Complementary Metal Oxide Semiconductor

COTS Commercial-Of-The-Shelf

CS Chip Select

CVCM Collected Volatile Condensable Materials

EDAC Error Detection And Correction

ESA European Space Agency

FIFO First In First Out

FPGA Field Programmable Gate Array

Hi-Rel High Reliability

LPC Low Pin Count

MISO Master In Slave Out

MOSI Master Out Slave In

Rad-Hard Radiation Hardened

Rad-Tol Radiation Tolerant

RAM Random Access Memory

rtl Register transfer level

SEL Single Event Latchup

SEU Single Event Upset

SOC System On Chip

SPI Serial Peripheral Interface

TIM Thermal Interface Material

TML Total Mass Loss

UV Ultraviolet

VHDL Very high speed integrated circuit Hardware Descriptive Language

WB WishBone

v

1. Introduction

When designing a spacecraft and its subsystems a lot of consideration has to be paid to the envi-ronment it will encounter during operation. In space the environment will be almost vacuum and ascan be seen in Figure 1.1 electronics on a satellite will experience a larger dose of radiation since itis not protected by the atmosphere. Since almost all satellites have an orbit with an altitude above200 km [29] they are not even protected from the ultraviolet (UV) radiation which is absorbed verye�ciently by the atmosphere. To withstand such an environment the satellite components need toundergo severe analysis and testing before launch, since there will be no possibility to repair thesatellite once it is launched. [3]

Figure 1.1: How deep into the atmosphere di�erent wavelengths can penetrate. [7]

The trend in the satellite business is to reduce the mass, volume and power consumption alongwith increased processing capabilities. In an example given by the European Space Agency (ESA) themass of data handling unit has decreased considerably over the last few years. [1] One way to achievehigh processing power with small mass is to use commercial components. This thesis has the aim tocreate a working interface that can be used to boot up a Commercial-Of-The-Shelf (COTS) processorfrom a fault tolerant memory and has been conducted at ÅAC Microtec AB. Aside from the bootup interface this thesis will aim to create additional hardware to monitor the boot up and controlthat the processor has booted correctly. If time is available, commercial thermal interface materialswill also be investigated to see if there are commercial materials that could replace the space gradedmaterials.

1

1. Introduction

During the 1980s and 90s satellites with a mass between 10 and 100 kg, called micro-satellites, werebeing launched at an increased rate and several countries all over the world built micro-satellites tobe launched into orbit. The most common application for these satellites were communication. Thissparked an interest for the use of micro-satellites for scienti�c, commercial and military applications.[2] Nano-satellites, satellites with a mass of 1-10 kg, are a very popular choice to educate studentsand young engineers in designing a satellite. Another reason for the increased launch rate for micro-and nano-satellites is that they present a good opportunity to test and demonstrate new technologyfor space missions. This is why these small satellites are used to make it possible to reduce the costof larger satellites intended for longer missions. [2]

1.1 Background

To withstand such an environment as space, electronic components and systems have to be designedin a special way and they have to undergo severe testing to ensure that the components will workproperly in space. Since the market for such components is limited, there are not a lot of companiesdeveloping radiation hardened (Rad-Hard) or radiation tolerant (Rad-Tol) components. A smallproduction scale in combination with the amount of testing required makes Rad-hard componentsvery expensive and hard to a�ord for smaller satellite manufacturers. [6] The Rad-Tol components arenot as powerful as most of the similar components commercially available, due the protection againstradiation in their design. The systems on a satellite will have no possibility to have hardware errorsrepaired, so they have to be able to function for a long time without the need to be repaired. [5]

During sounding rocket experiments early on, some of the instruments were designed using someCOTS components and these experiments yielded the �rst time COTS components used in a spaceenvironment. [6] Since then COTS has always been used to some extent on satellites to raise theperformance or lower the cost and the use of COTS components are therefore increasing. [5] A reasonfor this increase of commercial components, aside from the better performance, is the fact that themarket of high reliability (Hi-Rel) components is decreasing. [5] A drawback of COTS is that it is hardto use the same components in several missions since the components of today are quickly replacedby newer and better components and soon becomes obsolete. This also makes commercial productsunsuitable for missions like Rosetta and JUICE that has the launch planned around 10 years fromthe announcement. [6] [19] [20] M. Day writes in a paper [6] that when using commercial componentsin space application it is important to plan were to put the commercial components to make themfunction as well as possible. In [5] M. Pignol states that "COTS components can never be usedcompletely as is in the space context". There are several reasons the full potential of COTS cannotbe used during space missions. The main restrictions for commercial components are that the memorybus on a satellite operates at a lower speed than what is typical for a commercial processor and thetypical power consumption of commercial components is too large for the restricted power budgetof a satellite. Around 2010 microprocessors started to appear with error detection and correction(EDAC) for the cache memory powerful enough to handle the space environment, making them moreattractive for space missions. [5]

COTS components have to be tested and quali�ed before they can be used on space missions sincethey are more sensitive to, for example, thermal cycling which may cause intermetallic growth thatend up short circuiting the component. Depending on the assurance requirements of the mission,the severity of the quali�cation testing varies. Once commercial components have been quali�ed touse for space missions they will remain quali�ed for seven years. Day and Pignol also states severalexamples of satellites that are in orbit with varying amounts of COTS components. [6] [5] M. Pignolalso presents suggestions on how to validate that the design can handle the space environment. [5]

ÅAC Microtec has decided to use a commercial processor for data processing to make smallsatellites more powerful. This processor will complement the onboard computer of satellites and beused solely for processing data and make processor heavy calculations. For this ÅAC Microtec haschosen the AMD Embedded GX209HA system on chip (SOC) processor. The GX209HA operates at1.0 GHz, which can be compared to the radiation hardened processors where most of them operateat frequencies of tens of MHz. GX209HA is also a 64 bit processor, while the Rad-Hard ones are32 bit processors, making the commercial processor even more powerful compared to the Rad-Hardones. In Table 1.1 a few characteristics of the GX209HA is compared to some Rad-Hard processors.Another reason the GX209HA was chosen is that it supports EDAC for its memories.

2

1. Introduction

Table 1.1: Comparison between the GX209HA and Rad-Hard processors.

processor CPU frequency Data widthGX209HA [13] 1.0 GHZ 64 bitAT679F [14] 100 MHz 32 bitTSC695F [15] 25 MHz 32 bitSCOC3 [16] 80 MHz 32 bitCOLE [17] 80 MHz 32 bit

1.2 Report outline

This report will start with short description of how the vacuum and radiation in space a�ect thespacecraft and its electronics. The theoretical section will also brie�y explain why electronics aresensitive to heat and why it is necessary to distribute the heat produced away from the electronics.After the theoretical chapter the full system will be presented along with decisions and assumptionsmade during the design process. Chapter 3 will also describe the design procedure of the �nalsystem and in which order the di�erent parts were created. Simulations along with the di�erent testprocedures performed on the design and the corresponding results will be described in Chapter 4.This report will end with a conclusion and discussion of the work performed and give some suggestionsof what can be done to make the system functional.

3

2. Theoretical background

Due to the environment satellites are exposed to in space it is important to know how that environmenta�ects satellites and their systems. This chapter will explain the e�ect that the vacuum and radiationin space has on the spacecraft and its electronics. It will also explain the e�ect that heat has onelectronics and how heat is distributed away from the electronics to protect it.

2.1 Vacuum e�ects

At about 150 km altitude the pressure is approximately 0.5 µPa, according to a table provided byAVS Science and Technology of Materials, Interfaces, and Processing. [25] This is about nine ordersof magnitude less than the pressure at sea level, according to the same table. Most satellites havean orbit with an altitude of 200 km or higher, [29] it is therefore justi�able to assume that theirenvironment is vacuum. Due to the lack of atmosphere a spacecraft has to rely solely on radiation torelease heat and lower the temperature. This means that the surface properties of the satellite arecrucial in order to keep the satellite in a suitable temperature range.

Figure 2.1: Outgassing: di�usion followed by desorption. [9]

Impurities exist in all materials [10] and these impurities can escape due to their lower bindingenergy, through a process called outgassing. These impurities are either initially present in thematerial or the product of decomposition from exposure to solar radiation. [32] Outgassing is mainlydriven by two di�erent processes in the material; namely desorption and di�usion, that result in acontamination of the spacecraft. Desorption is a process where a molecule at the surface acquireenough energy to break its bonds with the surrounding atoms and leave the surface. The othercontributor to outgassing is called di�usion. Di�usion is when impurities within the material, drivenby thermal movement, di�use across the material and have enough energy to evaporate at the surface.These two processes are illustrated in Figure 2.1 and although desorption requires less energy thandi�usion, [10] the main part of the contaminants are located within the material and di�usion istherefore the dominant contributor to the contamination of the satellite. Particles which are releasedmay stick to other parts of the spacecraft and create a thin coating. If this coating is formed onan optical sensor, a solar panel or thermal management surface it will degrade their performances.When testing the outgassing properties of a material its total mass loss (TML) and collected volatilecondensable materials (CVCM) values are determined. TML is determined by measuring the mass

4

2. Theoretical background

loss of a sample during 24 hours at 125◦C and a pressure below 7 mPa, while CVCM is measured bythe mass gained by a 25◦C plate during the same test.

2.2 Radiation e�ect on electronics

There are two di�erent kinds of radiation, one is the particle radiation which consist mainly of protons,neutrons, electrons and alpha particles. The other one is electro magnetic radiation, e.g. UV light,X-ray and gamma radiation. When these di�erent radiations pass through matter they interact withit in di�erent ways. The most common particles for a satellite in orbit are protons and electrons, [10]so these particle interactions will be further explained along with photon interaction. When protonsand electrons travel through matter they will mainly interact with the nucleus and electrons of theatoms by electrical forces. When a proton or electron enters the vicinity of the atomic electrons theforce exerted between them will depend on the distance according to Coulomb's law

F =Q1Q2

4πε0r2, (2.1)

where Q1, Q2 is the charge of each particle, ε0 = 8.854187817 · 10−12As/V m is the permittivity inempty space [11] and r the distance between the particles. If the kinetic energy of the incomingparticle is large enough, it wont be stopped by this force and may rip electrons from their orbits.This is called ionization and is the most common e�ect of radiation. [10] Photons whose energy islarger than the binding energy of the electron they hit will have the same e�ect. Due to the largermass of a proton compared to an electron, a proton that hit the nucleus could transfer enough energyto an atom in order to break its bond with the surrounding atoms and push it out of place.

When electronics are exposed to radiation, ionization of atoms in a component may produce smallcurrent spikes. These spikes may alter the value stored in a memory device by changing the value ofone or more bits, depending on how tightly packed they are, between 1 and 0. This is called a singleevent upset (SEU) and spacecraft systems has implemented error detection and correction (EDAC)codes to handle SEU, since they are guaranteed to happen in orbit. [10]

Another e�ect ionizing radiation can cause is called single event latchup (SEL) which can occurin semiconductor components such as CMOS devices. SEL occur when a particle manage to ionizeenough atoms in a speci�c area to induce a parasitic current in the component. This current willnot stop until the power is turned o� [10] so the system shall be able to detect a rise in currentconsumption in order to handle SEL.

When an atom is dislocated by a proton it will create a vacancy in the structure of the electroniccomponent. This is called displacement damage and the displaced atom may ionize or displace otheratoms in the electronic structure. Even though some of the displaced atoms may return to the vacantposition and recreate the original structure through thermal movement, a process called annealing,some dislocated atoms will remain displaced. [10] The remaining vacancies in the electronic structurewill reduce the conductivity of the component.

2.3 Thermal management

More compact electronic design increase the amount of heat generated due to the larger amount ofpower consumed by the electronics. Higher temperature can cause materials to degrade and wear outmore quickly than they would at a more optimal temperature and it will also reduce the reliability ofthe electronics. To be able to keep the electronics operational over a long period of time it is importantthat they operate at a low temperature to minimize the thermal stress on the system. [26] [27]

Distributing the heat from the electronics can be done by connecting it to a heat sink with goodthermal conductivity. However, just putting the heat sink in contact with the component will notsu�ce. This is because microscopic irregularities on the surface will create cavities between the twosurfaces, which can be seen in Figure 2.2. Heat will be transferred between the component and theheat sink through conduction only where the heat sink and component are in contact and throughradiation over the cavities. Since the cavities make up more than 98% [8] of the area that connectsthe component and heat sink they have to be �lled in order to ensure a good thermal connection.

5

2. Theoretical background

Several di�erent materials are available to be used for this purpose, which will be further investigatedin section 3.4. [4] These materials are called thermal interface materials (TIM) and increases theheat conduction between the electronics and heatsink. However TIM does not have as good thermalconductivity as the component to heat sink connection, so the thermal interface will still be a thermalbottleneck [4] and research is conducted to improve conductivity of TIM.

Figure 2.2: The connection between two surfaces on a micro scale. [22]

6

3. System

The main focus has been to design the gate logic hardware, also called register transfer level (rtl)hardware, that will handle the boot sequence of the GX209HA SOC processor. GX209HA is a chipthat contains a CPU, a graphic processor and an input/output controller on one die and operatesat a frequency of 1.0 GHz. The GX209HA is a dual core 64 bit processor and is operational withina temperature range of -40◦C to 105◦C. [18] [13] The rtl created is to be implemented onto a �eldprogrammable gate array (FPGA), which is a component consisting of programmable logical gates andmemory elements. This chapter will start with a brief introduction to the serial peripheral interface(SPI) bus and explain why the GX209HA will be booted over the SPI. The chapter will continuewith explaining the choices made when designing the system and in which order the di�erent partswere created, followed by a description of the �nal system and its parts in the same order. Finally,the process of choosing a thermal interface material for the processor will be presented.

3.1 Serial Periferal Interface

SPI is a serial interface consisting of four signals; the serial clock, chip select (CS), master in slaveout (MISO) and master out slave in (MOSI), where the master device drives the clock, chip selectand MOSI signals, while the MISO signal is driven by the slave device. When a transfer is to beginthe master activates the chip select, sometimes referred to as slave select, and start transferring withthe most signi�cant bit �rst. Figure 3.1 illustrates an example of what the SPI connection may looklike in a system that transfers eight bits every transfer cycle. [21] The slave and master both transmitat the same time, so they have to be able to handle the received data in accordance with the SPIprotocol being used. SPI can be used as a bus with the CS signals deciding which slave that shall beactive, the SPI bus will use more signals depending on how many slaves that are connected.

During startup, the BIOS of the GX209HA processor will set up the system and interfaces basedon the available software. By default the BIOS will execute the software from a local �ash memory.The GX209HA is equipped with a boot disable signal that, if active, will make the processor bootover the SPI. Booting the processor over the SPI will allow the boot image to be stored in a memorythat has hamming coding implemented and therefore is fault tolerant.

Figure 3.1: An illustration of how the SPI devices may be designed in an eight bit transfer cycle. [21]

7

3. System

3.2 System design

In Figure 3.2 the over all system of the platform is shown, the part designed in this thesis is the SPIBoot control block. The OpenRISC is a fault tolerant processor and the main CPU of the system, allthe other blocks in Figure 3.2 are a part of the rtl of the FPGA. The Memory controller adds EDACon all incoming data that is written towards the external chip. Memory controller then performs ascrubbing of the data from least signi�cant bit address to the most signi�cant bit address. The Flashcontroller will handle the write, read and erase actions of the NAND �ash memory of the board. Inthe �ash memory is the boot image for the GX209HA processor stored along with the boot sequenceof the main board. The DMA control controls the access to these memories.

Figure 3.2: An overview of the overall system.

The Debug unit allow external access to the processor and control of the wishbone bus so thatthe system functions can be tested and debugged. The Debug unit is connected to circuitry that willmake it possible to connect a computer to the board via a debugger. The Error manager monitorserror events in critical components and store them in error counters. Each error counter indicates itserror in the Error Manager Status Register and the counters are cleared on Power-On-Reset, unlessthe reset is issued by the Error manager. This feature allows the software to perform actions based onprevious reset events. The Watchdog is a timer implemented to counter software freeze. This blockwill also reset the system if the boot up sequence takes to long.

The SCET is the timer of the spacecraft and consist of a counter that increases its value by 1 forevery 275 clock cycle. This give the timer a resolution of approximately 15.3 µs and a turnaroundtime of 136 years. The GPIO is connected to the GPIO pins of the FPGA and they are de�ned ascombined input and output, where their direction is managed by software.

Since the boot image of the GX209HA is stored on an external �ash memory the processor will bebooted over the SPI. The GX209HA processor is compliant to the PCT25VF032B SPI �ash memory,so the rtl will be designed to function as this memory in read mode. This part will henceforth becalled SPI emulator. It is assumed that the SPI transfer is linear, i.e. the transfer will go from the�rst address to last. Figure 3.3 shows the behaviour of the SPI �ash memory when in read modeand is taken from the product data sheet. [23] The master will start each transfer cycle by sending

8

3. System

an eight bit instruction, so called OpCode, containing which kind of operation is to take place. Inread mode the next 24 bits contain the address where the data is to be sent from. During these bitsthe MISO signal is ignored by the master and the �rst bit of data is read on the trailing edge of the32nd clock cycle by the master. Since the main system should be able to continue working during theboot up of the GX209HA, a �rst in �rst out (FIFO) register will be connected to the SPI emulator.The SPI emulator is the �rst part that is designed and tested, followed by the implementation of theFIFO register.

Figure 3.3: Timing schedule of the SPI transfer when in read mode. [23]

Communication with the main system will be done over the internal WishBone (WB) bus, devel-oped by ÅAC Microtec. The WB interface has to be modi�ed to suit the need of this component. Thisinterface was designed after the SPI emulator and FIFO register. In order to ensure that GX209HAhas booted correctly the hardware need a way to supervise the boot up sequence. A few di�erentmethods were considered and after discussing it with Jonas Antoni at Hectronic AB it was decidedto use the low pin count (LPC) bus where the GX209HA will send out test codes during startup.These test codes are sent over the LPC bus with the hexadecimal address 80, which is why they arecalled PORT80 codes. PORT80 codes are a speci�c set of codes that the BIOS send out as a startuptest in a particular order. If these codes are not received in that order, something has gone wrongduring startup. The LPC interface was the last piece of the rtl to be created and it was designed tobe compliant with the Intel LPC bus. [24]

3.3 GX209HA boot control

Figure 3.4: An overview of the GX209HA boot control, as it is designed.

Figure 3.4 shows an overview of the system designed in this thesis and how the di�erent parts areconnected to each other. Each block will be described in this section. The GX209HA boot control is

9

3. System

designed using the hardware descriptive language VHDL with the software ModelSim. The hardwarecode is divided into six �les and in Table 3.1 the �les of the project are summarized with a shortdescription. For full code of the �les see Appendix A, the code of the FIFO registers are not includedin the Appendix.

Table 3.1: A short description of the �les in the component.

File DescriptionFIFO A 256 element register of 32 bit words. Stores the data that is to be sent in a

�rst in �rst out mannerlpc_byte The LPC interface, forwards the data received over the LPC bus to PORT80_-

FIFO registerPORT80_FIFO The second part of the LPC Interface block. Stores the values received over

the LPC bus and informs the system that new values are ready to be readSPI_WB The wishbone interface. The PORT80_FIFO and FIFO �les are embedded in

this �leSPI_Management An SPI slave. Also serializes the output of the FIFO register so it can be sent

over the SPI busQ7_boot_control The top entity, connects SPI_WB, lpc_byte and SPI_Management compo-

nents together and creates the component layout

3.3.1 SPI Management

The SPI Management block will emulate an SPI slave device in accordance with the PCT25VF032BSPI �ash memory. Figure 3.5 illustrates the functionality of the SPI Management block, which isactivated by the CS signal of the SPI. The blocks MOSI handler and Data serialization are driven bythe SPI clock, while the SPI clock check is driven by the main system clock. The data serializationblock will serialise the 32 bit output of the FIFO register so that the data can be sent bit by bitover the MISO signal of the SPI bus. When the last bit is being sent the data serialization block willretrieve the next 32 bit from the FIFO by activating the read enabled signal. The SPI Managementblock is activated by the chip select signal of the SPI.

There are two processes that are used to control that the SPI is working correctly. One process isrepresented by the MOSI handler block, which controls that the incoming OpCode is the hexadecimalnumber 03, which is the code for a read sequence, if this code is not received the SPI data has probablybeen corrupted by radiation. If the wrong OpCode is received this block will activate the irq signalto send an interrupt request to the WB interface. The MOSI handler block also activates the SPIManagement so that it starts sending data at the right time. The SPI clock may freeze due toradiation so the SPI clock check block is implemented to monitor the SPI clock. SPI clock check isa simple counter which is driven by the internal clock and checks a counter driven by the SPI clock.The SPI clock counter is located in the MOSI handler block and is triggered by the SPI clock signalwhen the CS signal is active. This process will alert the system, by activating the irq signal, if the SPIclock counter hasn't changed value during a certain time while the chip select signal is active. Boththe MOSI handler and the SPI clock check can activate the irq signal which the WB interface will useto alert the main system that there is a problem with the SPI. The code for this block can be foundin the �le SPI_Management in Appendix A and the logical schematic can be found in Appendix B.

3.3.2 FIFO register

The FIFO register block is a 256 element long array consisting of elements with the size of 32-bits.The FIFO register is connected to the main system through the WB Interface, which makes it possiblefor the main system to �ll the register with parts of the boot image and attend other matters whilethat part is being transmitted. When the SPI Management block has sent the last bit it will activatethe read enable signal and the FIFO will transfer the element that is �rst in line. The FIFO registerreceives and transmits 32-bit words.

In the connection to the WB Interface �ve interrupt �ags can be generated by the FIFO register,empty, almost_empty, almost_full, full and overrun. The empty and full �ags indicate that the

10

3. System

Figure 3.5: The SPI Management block functionality.

register is empty and full respectively. Almost_empty �ag indicates that there are only two elementsleft in the FIFO and the almost_full �ag indicates that only two more elements can be written tothe register. An overrun �ag will occur if the register is written to, even though it is full. The codefor the FIFO register is created by Jakob Viketoft and Stefan Strålsjö for ÅAC Microtec.

3.3.3 Wishbone interface

Figure 3.6 shows the structure of the wishbone interface. The WB interface is driven by the systemclock and will connect the boot control to the wishbone bus. The part of the wishbone interfacethat is connected to the WB bus is illustrated by the blocks irq handler and WB command handler.In the irq handler block all the interrupt request signals from the boot controller are collected andstored in an interrupt register accessible by the WB bus. In this register one bit is used to indicateif the SPI is functioning, �ve bits to tell the state of the FIFO register and one bit to indicate thatthere are PORT80 codes to be read. Irq handler uses the empty signal of the PORT80 FIFO registerto detect if any codes have been received, if the empty signal is not active the WB interface willalert the main system that there are codes to be read. The main system can write to the interruptregister in order to deactivate active bits after handling those interrupts. Along with the interruptregister, the irq handler also contains a register that allows the main system to control which interruptrequests that should alert the main system. In this register each interrupt request signal correspondto an enable/disable bit, if a bit is disabled an interrupt will not be generated by the correspondinginterrupt request.

The WB command handler block represents the part of the WB interface that carries out the

11

3. System

Figure 3.6: The functionality of the WB interface block.

commands aimed for the boot controller and ignores the other requests. Each part of the system thatis accessible by the WB bus is represented by an address, so if data is to be sent to the FIFO registerthe system sends a write command along with the address that represents the FIFO register and thedata that is about to be written. Data that is about to be written to the FIFO is passed along fromthe bus to the FIFO write, which handles the connection to the FIFO register. The PORT80 readblock handles the connection to the PORT80 FIFO and retrieves codes which are passed onto theWB bus by the command handler. Information and commands regarding the interrupt registers arealso handled by this block, the only direct connection the irq handler has with the WB bus is theinterrupt request signal.

The WB Interface is designed speci�cally for the GX209HA boot control, due to the speci�ccommands and connections to this component. However, the interface uses the same structure andcommand handling as all wishbone interfaces at ÅAC Microtec. Those interfaces were developed byStefan Strålsjö. A few other registers are implemented for debugging purposes and are not relevantto the �nal function of the interface. The code of the WB Interface can be found in Appendix A andthe logical schematics in Appendix B.

3.3.4 LPC interface

The LPC interface consists of two �les, the lpc_byte �le describes the actual LPC interface while thePORT80_FIFO is a FIFO register that stores the PORT80 codes and handles the connection to theWB interface. Figure 3.7 shows the structure of the LPC interface where the LPC mode decoder,Data handler and LPC data transfer blocks represents the interface. The LPC interface is a modi�edversion of OpenCores LPC bus, designed as an Intel LPC peripheral during I/O write mode, i.e theprocessor will write to the peripheral. [24] The LPC mode decoder block handles the communicationwith the bus and ignores all activities that are not a write instruction to the hexadecimal address 80.Data is sent over the LPC bus four bits at a time and a PORT80 code is composed of eight bits sothe Data handler block is responsible for combining the data into PORT80 codes and writing themto the FIFO. Since the same signals of the LPC bus are used to both transmit and receive data, theLPC data transfer block controls when the mode controller should receive or transmit data. Whendata has been sent to the FIFO, LPC data transfer will set the LPC mode decoder into sending modeto con�rm that data has been received.

The PORT80 FIFO register contains eight bit elements but is otherwise the same as the FIFOconnected to the SPI. The empty signal of the FIFO is connected to the WB interface to be used toalert that there are codes to be read. The FIFO integrated in the handling of the PORT80 codeswasn't originally implemented, but was added due to reasons explained in chapter 4. The code of the

12

3. System

Figure 3.7: The functionality of the LPC interface block.

LPC interface can be found in Appendix A and the logical schematics in Appendix B.

3.4 Thermal interface

The thermal interface will connect the CPU to the heat sink, so that heat can be transferred fromthe processor and the heat sink can radiate the heat to lower the temperature. When investigatingmaterial to be used as thermal interface, the material has to be space quali�ed. This means thatcertain criteria, such as outgassing, has to be ful�lled. A decision was made to only investigatecommercial materials in order to determine if there are commercial materials that can be of interestfor space missions. Therefore the �rst parameter used to �lter out material was their outgassingcharacteristics. Material whose TML was above 1 % [10] and CVCM was above the values suppliedby ESA, which are summarized in Table 3.2, are not suitable for space and therefore excluded fromthe process.

Table 3.2: The CVCM restriction for di�erent masses of a material according to ESA. [30]

Weight (g) CVCM (%)>1000 <0.01

100 - 1000 <0.0110 - 100 <0.011 - 10 <0.03<1 <0.1

When the products that did not have the suitable outgassing properties had been ruled out theirthermal characteristics, such as thermal conductance and thermal impedance, were examined. Thethermal interface should not be attached using mechanical attachment since neither the board northe heat sink are designed for that kind of strain. A value of thermal conductance as high as possibleis desirable for the TIM as well as a low thermal impedance.

13

4. Testing and result

During the design process of the system, several simulations have been made to test if the systembehaves as desired. This chapter will start by describing the simulations and their results and thenmove on to how the system was tested on hardware along with the results from those tests. Thelast part of the chapter will display some of the TIM that has been evaluated along with theircharacteristics.

4.1 Simulation

When the rtl design was done it was simulated in the same tool used to design it. This was madeby creating a so called test bench, where signals are sent into the component and its outputs areanalysed. Firstly the SPI emulator was simulated by creating a test bench that acts as an SPI masterand then control that the SPI start transferring when it is supposed to and that it transfer the correctdata. In Figure 4.1 the simulation of the SPI can be seen during one transfer cycle. The rd_datasignal is the 32 bit output of the FIFO register that is to be sent on the SPI. During the �rst 31 clockcycles, clk_spi is the clock signal, the rd_data_o signal remains unchanged since the instruction andaddress are being sent from the master during these bits. The SPI start sending on clock cycle 32due to the fact that the processor will start to read at the trailing edge of cycle 32. rd_data_o sendsa clock signal pattern which is reversed after 16 cycles, which is the same as the value of rd_data. Atthe end of the transfer cycle the Rd_En signal is activated and retrieves the next word to be sent.Even though Figure 4.1 does not show the next transfer, the next word is being transferred.

Figure 4.1: Simulation result of the SPI. The names of the signals are rd_data_o (which is the MISOsignal), clk_spi, SPI_MOSI, SPI_CS0, Rd_En and rd_data.

After the FIFO register and WB interface were implemented a WB test bench, developed byStefan Strålsjö, was used to simulate the WB interface. The size of the FIFO was reduced duringthis simulation in order to be able to check the FIFO full and overrun �ags. Figure 4.2 show theactivity on the wishbone bus during several di�erent commands, where most commands writes datato the FIFO register. During these commands the wishbone bus will send an address and data on thewb_adr_i and wb_data_i signals respectively when the wb bus writes to the system. The wb_dat_osignal sends data onto the wb bus during read commands and its value only change in the simulationwhen a register is read. At the end of each wb instruction cycle the wb_ack_o signal is activated tolet the bus know that the instruction has been completed. The signal int_o is the interrupt signalthat will alert the main system that an interrupt �ag is active. This signal is not active during the�rst clock cycles of the �gure even though some �ags are active, the value of wb_dat_o would bezero when address 078 is read if no �ags were active. This is due to the fact that all the interrupts

14

4. Testing and result

Figure 4.2: Simulation result of the WB interface. The names of the signals are WB_clk, rst_i,wb_dat_i, wb_dat_o, wb_addr_i, wb_ack_o and int_o.

are disabled during that period. The �ags are enabled by writing 32 ones to the address 080 andwhen this is done the int_o becomes active, as expected. When the reset signal (rst_i) is activated,the system resets to the default mode and this part is not included in Figure 4.2. All interrupt �agsfunction as expected, the empty and almost_empty �ags are deactivated during the period of the�gure and the other react the way they should during the simulation. In order to determine thatthe connection between the FIFO and SPI was working properly the SPI was also tested, which isexplained in the beginning of this section.

Figure 4.3: Simulation result of the LPC interface. The names of the signals are lreset_n, lclk,lframe_n, lad_i, lad_o, lad_oe, lpc_wr, lpc_data_re and lpc_ack.

After connecting the LPC interface to the WB interface, signals were generated in accordance withthe LPC speci�cation [24] and the PORT80_FIFO was examined to make sure that the codes senthad been stored. Simulation results from the LPC simulation during three write cycles can be seenin Figure 4.3. The lframe_n signal goes low to start an LPC sequence where the lad_i signal willcarry information about the type of transfer that will be done along with which address that shall beaccessed. lad_o will transfer data to acknowledge that the data has been handled when the lad_oeis active since lad_i and lad_o will have the same lines on the hardware. When lpc_wr is activateddata is sent to the PORT80 FIFO over the lpc_data_reg signal. The lpc_ack signal is activated tolet the LPC interface know that the data has been received by the FIFO. If other transfer modes oraddresses are sent, the simulation show that they will be ignored. The content of the PORT80 FIFOwas controlled to ensure that the codes has been stored correctly.

4.2 Testing SPI

When the rtl has passed simulation, it has to be tested using real hardware. This was done byincluding this rtl code in a project for an OBC lite board to get all connections of the FPGA right.The OBC lite is a micro processor board with an FPGA that is developed by ÅAC Microtec andTable 4.1 lists some of its characteristics. [28] The output pins of the FPGA was modi�ed so thatsuitable pins on the OBC lite board could be associated with the SPI and LPC signals. A memoryboard that can act as an SPI master was connected to the SPI pins on the OBC as shown in Figure4.4. A program was created to �ll the FIFO with a clock signal pattern, this was a modi�ed version

15

4. Testing and result

Figure 4.4: The connection schematic of the SPI test.

of the code in Appendix C. The memory board activated the SPI bus and the data on the MISOsignal was analysed to con�rm the clock signal pattern. After some problem with the connectors, theclock pattern was �nally seen.

Table 4.1: Some of characteristics of the OBC-lite. FM stands for Flight Model, which is fault tolerantand EM is Engineering Model, which is not. [28]

Processor 32 bit processorProcessor clock 18 MHz

SDRAM 64 MB (EM) 32 MB (FM)Instruction cache 8 kB

Data cache 8 kBMass storage 1 GB NAND parallel Flash

When the function of the SPI had been veri�ed, the OBC was connected to a carrier board for theGX209HA processor in the same manner. This setup was then used to try to boot the processor bysending the standard boot image for the processor over the SPI. The processor did not start and thisturned out to be because the processor begins to execute the instructions read during the transfer andwill therefore jump between di�erent addresses in the memory. The software used during this test isa further development of the software used with the memory board and can be found in Appendix C.

4.3 Testing LPC

The �rst tests of the LPC interface was done on an early version of this hardware where the PORT80_-FIFO was not a FIFO register but just an interface that stored the latest PORT80 code and handledthe communication with the WB bus. In these tests the OBC Lite was connected to a carrier boardthat had a connector for the LPC pins. The Carrier board was connected to the OBC according toFigure 4.5, the lreset_n signal was deemed unnecessary for the test, and the processor was booted.A modi�ed version of the software used in section 4.2 was used to read the interrupt register of theWB bus to see if any PORT80 codes had been received. However, during the �rst test no codes werereceived.

To determine why no codes were received, the LPC connection was examined. With the OBCboard powered the voltage of the LPC pins were measured. Since these pins should be in tri-state bydefault to be able to receive data the voltage level should be between 1 and 2 V. The voltage levelof the LPC pins turned out to be at a level which represents a logical high. The reason turned outto be that the declaration of tri-state in the code was not correct. When this was solved the systemwas once again connected according to Figure 4.5 and the LPC interface was tested. During the

16

4. Testing and result

Figure 4.5: The connection schematic of the LPC test.

second round of testing only one code was received and it was discovered that the LPC clock had afrequency roughly two times larger than that of the OBC clock, so a FIFO was designed to handle thecommunication between the two clock domains. With the FIFO register implemented, the interfacewas tested once again and still only one code was received. By examining the debugging registersimplemented on the WB it was discovered that the hardware got stuck in the mode when it shouldreturn and wait for the next LPC interaction after the �rst code. When pulling the lreset_n signalhigh during the startup, more codes were received. Two small displays on the carrier board show thePORT80 code that are being sent, which makes it possible to see the last code that is to be sent.However, the last PORT80 code that should be transmitted could not be found. If the lreset_n waspulled high after the startup was complete, nothing happened.

4.4 Thermal interface

Several materials have been studied to �nd commercial thermal interface materials that passes theoutgassing criteria for usage in space. One of the materials that was investigated, the 1671, has beenused in aerospace and defence applications. Table 4.2 shows some of the most relevant products withtheir characteristics and their manufacturer. The values of the thermal impedance are given as theywere by the manufacturer and some values are given for di�erent pressures, depending on how thevalue was obtained. Some of the materials lack a thermal impedance value and this is because thatthe value could not be found, so they would need further investigation. CVCM for the GR-ae is givenas <0,01 since 0,01 is the smallest value measurable by that test.

Table 4.2: Some thermal interface material and their properties.

MaterialTML(%)

CVCM(%)

Thermal conductance(W/m−K)

Thermal impedance(◦Ccm2/W )

Manufacturer

GEL30 0,15 0,05 3,5 - Therm-a-gap1671 0,76 0,07 2,6 1,48 Cho-therm

T�ex 600 0,13 0,05 3,00 2,97 LairdT�ex HR600 0,19 0,07 3,00 2,26 LairdTPLI 200 0,07 0,02 6,00 - LairdTPLI 210 0,08 0,03 6,00 1,03 LairdTPLI 220 0,07 0,02 6,00 1,35 LairdTPLI 240 0,07 0,02 6,00 2,45 LairdGR-ae 0,04 <0,01 1,5 - Fujipoly

When analysing the materials in Table 4.2 there are four materials, TPLI 200 - 240, which have athermal conductance more than two times that of the 1671. Thermally conductive materials providedby the ESA database [31] has a thermal conductance ranging from 0.146 to 0.39 W/m−◦ C, so these

17

4. Testing and result

materials provide a valid alternative. However, there are more characteristics that has to be consideredand due to time constraints these characteristics could not be investigated. In order to determine ifany of these materials can be used they need to be investigated further and the materials have to betested before they can be used.

18

5. Conclusion

The main goal with this thesis was to create a working SPI interface toward the AMD EmbeddedGX209HA processor and the SPI interface did work. However since the GX209HA starts executingthe instructions it receives over the SPI before the entire transfer is complete, the processor cannotbe booted using this hardware. The GX209HA has a hold signal for the SPI implemented that willallow the slave to paus the transfer and resume it when ready. This hardware could be modi�edto use that signal to boot even if it would be much slower. The WB interface is working properlywhich is demonstrated in the �rst testing of the SPI as the test software managed to write to theFIFO register. It is also shown during the testing of the LPC interface since all the WB registers areaccessible by the debugger.

In simulation the entire component function the way it is supposed to. The LPC bus does,however, not work when constructed onto the OBC board where the hardware gets stuck in a statewhere it is only supposed to be in during one clock cycle the �rst time that state is reached. Whythe LPC hardware got stuck in that state has not been determined. It is possible that during themodi�cation of the Open Cores code some of the changes made could in fact be preventing the LPCto function the way that it should. During testing, the LPC received more codes if the lreset_n signalwas pulled high during the startup of the processor, nothing will happen if the startup is complete,indicating that it is the PORT80 codes that were being received. However the last code that is sentcould not be found so it is not certain what kind of codes are being received.

Thermal interface material are crucial in order to prevent that the processor overheats and thereare several commercial materials that meet the outgassing criteria of ESA. The thermal properties ofthese materials varies and the materials TPLI 200 - 240 from Laird technologies have higher thermalconductance than space graded materials. These materials need to be investigated further if they areto be used in space.

19

6. Future work

Since the rtl does not function the way it is supposed to more work have to be done in order for theboot control to work. The main focus is to make the interface able to boot the processor. To do sothe interface has to be modi�ed so that it reads the address sent by the processor and retrieve datafrom that address. One way to make the hardware work is to map a random access memory (RAM)to the SPI and modify the SPI to send the data from that memory. The GX209HA has a hold pinconnected to the SPI that can be used to pause the transfer while data is being retrieved, in case oftiming problems.

The behaviour of the LPC interface is another thing that needs to be investigated. Severaldebugging registers has been implemented to make it possible to determine how the LPC works andsome more are probably needed to be able to �gure it out. One thing to test could be to implementthe LPC code unmodi�ed to see if that will make it work. The function of the OpenCores LPC couldalso be further investigated in order to �gure out if there is something in the implementation that iswrong.

Thermal interface material has only been examined brie�y in this thesis and a more thoroughcomparison of TIMs have to be done in order to be able to choose a suitable material. For example,more space proven materials could be investigated to determine if it is justi�ed to use commercialmaterials for thermal management. The expected lifetime of the materials needs to be investigated,and whether thermal pads or greases is the optimum solution for the processor. Prices, batch sizesand availability also needs to be investigated further.

20

Bibliography

[1] Furano G., Issues in (very) rad hard systems. ESA-ESTEC Data Systems Di-vision, 2011.

[2] Yong Xue, Yingjie Li, Jie Guang, Xiaoye Zhang, Jianping Guo, Small satelliteremote sensing and applications - history, current and future. InternationalJournal of Remote Sensing, 2008.

[3] Berlin P., Satellite Platform Design. 5th Edition, Department of Space Science,University of Luleå2007.

[4] Schultz M., Allen S.T., Pohl W., The Crucial In�uence of Thermal InterfaceMaterial in Power Electronic Design. In�neon, 2013.

[5] Pignol M., COTS-based Applicastions in Space Avionics. CNES, 2010.

[6] Day M., 30 Years of Commercial Components In Space: Selection TechniquesWithout Formal Quali�cation. Surrey Space Centre, 1999.

[7] Fälthammar C-G., Space Physics. 2nd Edition, 3rd printing, Royal Institute ofTechnology (KTH), 2001.

[8] Bejan A., Kraus A. D., Heat transfer Handbook. John Wiley & sons, Volume 12003.

[9] Roussel J-F., Faye D., Van Eesbeek M., Tondu T., Migliore R., Rampini R.,Paulmier T., A new frontier for contamination: Reaching the molecules. 2009.

[10] Tribble A. C., The Space Environment. 2nd Edition, Princeton paperbacks,2003.

[11] Nordling C., Österman J., Physics Handbook for Science and engineering. 8thEdition, Studentlitteratur, 2006.

[12] Bloschock K. P., Bar-Cohen A., Advanced thermal management technologiesfor defence electronics. 2012.

[13] CPU world, AMD G-Series GX-209HA speci�cations. http://www.cpu-world.com/CPUs/Jaguar/AMD-G-Series%20GX-209HA.html.(Accessed: November 2015).

[14] Atmel products, AT697F. http://www.atmel.com/devices/AT697F.aspx. (Accessed: November 2015).

[15] Atmel datasheet, Rad-Hard 32-bit SPARC Embedded Processor. http://www.atmel.com/Images/doc4118.pdf. (Accessed: November 2015).

[16] Airbus defence & space (2012), SCOC3-Your computer core on a sin-gle chip. http://www.space-airbusds.com/en/equipment/scoc3.html. (Accessed: November 2015).

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BIBLIOGRAPHY

[17] Ruag, Panther processor board. https://www.ruag.com/fileadmin/ruag/Divisions/Space/Products/Digital_Electronics_for_Satellites___Launchers/Data_Handling_Systems/PDF/Processor_Board.pdf. (Accessed: November 2015).

[18] AMD, AMD Embedded G-Series System-on-Chip (SOC). https://www.amd.com/Documents/AMDGSeriesSOCProductBrief.pdf. (Accessed:November 2015).

[19] ESA Science and Technology (2015), Rosetta Summary. http://sci.esa.int/rosetta/2279-summary/. (Accessed: June 2015).

[20] ESA Science and Technology (2012), Announcement of oppor-tunity for the JUICE payload. http://sci.esa.int/juice/50494-announcement-of-opportunity-for-the-juice-payload/.(Accessed: June 2015).

[21] University of Washington, Communication. https://courses.cs.washington.edu/courses/cse466/11au/calendar/07-comms-posted2.pdf. (Accessed: June 2015).

[22] bit-tech Guide, How TIM works. http://www.bit-tech.net/hardware/2009/02/16/all-about-tim/1. (Accessed: June 2015).

[23] Professional computer technology limited (2010), PCT25VF032B Data sheet.

[24] Intel (2002), Intel Low Pin Count Interface Speci�cation. http://www.intel.com/design/chipsets/industry/25128901.pdf. (Accessed:August 2015).

[25] AVS Science and Technology, Atmospheric Pressure at Dif-ferent Altitudes. https://www.avs.org/AVS/files/c7/c7edaedb-95b2-438f-adfb-36de54f87b9e.pdf. (Accessed: Septem-ber 2015).

[26] Thermal Interface Wet Dispensed - Dow Corning, Thermal Interface Ma-terials Tutorial. http://www.dowcorning.com/content/etronics/etronicswet/newtim_tutorial1.asp?DCWS=Electronics&DCWSS=Thermal%20Interface%20-%20Wet%20Dispensed. (Accessed: June2015).

[27] Thermal Interface Wet Dispensed - Dow Corning, Why is Heat Bad for Elec-tronic Devices. http://www.dowcorning.com/content/etronics/etronicswet/newtim_tutorial3.asp?DCWS=Electronics&DCWSS=Thermal%20Interface%20-%20Wet%20Dispensed. (Accessed: June2015).

[28] ÅAC Microtec data sheet, OBC Lite 500. http://www.aacmicrotec.com/images/Products/Components/RIA/AAC_OBC_www.pdf. (Ac-cessed: September 2015).

[29] ITC's database of Satellites Sensors, list of all satellites. http://www.itc.nl/research/products/sensordb/AllSatellites.aspx. (Accessed:September 2015).

[30] ESA ESMAT, Outgassing database. http://esmat.esa.int/services/outgassing_data/outgassing_data.html. (Accessed: September2015).

[31] ESA ESMAT, Adhesives, Coatings, Varnishes. http://esmat.esa.int/Services/Preferred_Lists/Materials_Lists/materials_lists_9.html. (Accessed: November 2015).

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BIBLIOGRAPHY

[32] Spenvis, Help: Outgassing. https://www.spenvis.oma.be/help/background/contam/outgassing.html. (Accessed: September 2015).

23

Appendix A. RTL code

Some of the �les used to create the rtl hardware for this thesis are presented in this appendix.lpc_byte

-------------------------------------------------------------------- Universal dongle board source code---- Copyright (C) 2006 Artec Design <jyrit@artecdesign.ee>---- This source code is free hardware; you can redistribute it and/or-- modify it under the terms of the GNU Lesser General Public-- License as published by the Free Software Foundation; either-- version 2.1 of the License, or (at your option) any later version.---- This source code is distributed in the hope that it will be useful,-- but WITHOUT ANY WARRANTY; without even the implied warranty of-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU-- Lesser General Public License for more details.---- You should have received a copy of the GNU Lesser General Public-- License along with this library; if not, write to the Free Software-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301USA------ The complete text of the GNU Lesser General Public License can be found in-- the file ’lesser.txt’.

library ieee;use ieee.std_logic_1164.all;use IEEE.std_logic_unsigned.all;use IEEE.std_logic_arith.all;

entity lpc_iow isport (

--system signalslreset_n : in std_logic;lclk : in std_logic;lad_i : in std_logic_vector(3 downto 0);lad_o : out std_logic_vector(3 downto 0);lad_oe : out std_logic;lframe_n : in std_logic;

--memory interfacelpc_wr : out std_logic; --shared write not readlpc_data_o : out std_logic_vector(7 downto 0);lpc_val : out std_logic;

24

A. RTL code

lpc_ack : in std_logic;

-- Signals for debugginglpc_mode : out std_logic_vector(2 downto 0);data_count : out std_logic_vector(31 downto 0);addr_count : out std_logic_vector(31 downto 0);addr_debug : out std_logic_vector(31 downto 0);frame_count: out std_logic_vector(31 downto 0);start_count: out std_logic_vector(31 downto 0));

end lpc_iow;

architecture rtl of lpc_iow istype state is (RESETs,STARTs,ADDRs,TARs,SYNCs,DATAs,LOCAL_TARs); -- simple LCP states

signal CS : state;signal r_lad : std_logic_vector(3 downto 0);signal r_addr : std_logic_vector(31 downto 0); --should consider saving max

--adress 23 bits on flashsignal r_data : std_logic_vector(7 downto 0);signal r_cnt : std_logic_vector(2 downto 0);signal addr_count_i : std_logic_vector(31 downto 0);signal addr_debug_i : std_logic_vector(31 downto 0);signal data_count_i : std_logic_vector(31 downto 0);signal start_count_i: std_logic_vector(31 downto 0);signal frame_count_i: std_logic_vector(31 downto 0);

signal lad_rising_o : std_logic_vector(3 downto 0);signal lad_rising_oe : std_logic;

constant START_FW_READ : std_logic_vector(3 downto 0):="1101";constant START_LPC : std_logic_vector(3 downto 0):="0000";constant IDSEL_FW_BOOT : std_logic_vector(3 downto 0):="0000"; --0000 is boot device on ThinCanconstant MSIZE_FW_1B : std_logic_vector(3 downto 0):="0000"; --0000 is 1 byte readconstant SYNC_OK : std_logic_vector(3 downto 0):="0000"; --sync doneconstant SYNC_WAIT : std_logic_vector(3 downto 0):="0101"; --sync wait device holds the busconstant SYNC_LWAIT : std_logic_vector(3 downto 0):="0110"; --sync long wait expected device holds the busconstant TAR_OK : std_logic_vector(3 downto 0):="1111"; --accepted tar constant for master and slave

begin

lad_o <= lad_rising_o;lad_oe <= lad_rising_oe;

frame_count <= frame_count_i;start_count <= start_count_i;data_count <= data_count_i;addr_count <= addr_count_i;addr_debug <= addr_debug_i;--Pass the whole LPC address to the systemlpc_data_o <= r_data;

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A. RTL code

-- purpose: LPC IO write/LPC MEM read/LPC FW read handler-- type : sequential-- inputs : lclk, lreset_n-- outputs:LPC: process (lclk, lreset_n)begin -- process LPCif lreset_n = ’0’ then -- asynchronous reset (active low)CS <= RESETs;lad_rising_oe <=’0’;lad_rising_o <="0000";lpc_val <=’0’;lpc_wr <=’0’;r_lad <= (others=>’0’);r_addr <= (others=>’0’);r_data <= (others=>’0’);r_cnt <= (others=>’0’);lpc_mode <= (others=>’0’);data_count_i <= (others=>’0’);addr_count_i <= (others=>’0’);addr_debug_i <= (others=>’0’);frame_count_i <= (others=>’0’);start_count_i <= (others=>’0’);

elsif lclk’event and lclk = ’1’ then -- rising clock edgecase CS iswhen RESETs => ----------------------------------------------------------lpc_mode <= "001"; --1lpc_wr <=’0’;lpc_val <=’0’;if lframe_n=’0’ thenframe_count_i <= frame_count_i + 1;CS <= STARTs;r_lad <= lad_i;

elseCS <= RESETs;

end if;when STARTs => ----------------------------------------------------------lpc_mode <= "010"; --2if lframe_n = ’0’ thenr_lad <= lad_i; -- latch lad state for next cycleCS <= STARTs;

elsif r_lad = START_LPC then--must identify CYCTYPEstart_count_i <= start_count_i +1;if lad_i(3 downto 1)="001" then --IO WRITE WILL HAPPEN--next 4 states must be address statesCS <=ADDRs;r_cnt <= "000";

elseCS<= RESETs;

end if;elseCS<= RESETs;

end if;

when ADDRs => -----------------------------------------------------------

26

A. RTL code

lpc_mode <= "011"; --3--IO write cycleif r_cnt ="011" thenif r_addr(11 downto 0)=x"008" and lad_i(3 downto 2)="00" thenr_addr <= r_addr(27 downto 0)&lad_i;r_cnt <= "000";addr_count_i <= addr_count_i +1;CS <=DATAs;

elsif r_addr(11 downto 0)=x"008" and lad_i(3 downto 0)=x"8" then--for debug switch

r_addr <= r_addr(27 downto 0)&lad_i;r_cnt <= "000";addr_debug_i <= addr_debug_i +1;CS <=DATAs;

else--not for this deviceCS <=RESETs;

end if;elser_addr <= r_addr(27 downto 0)&lad_i;r_cnt <=r_cnt + 1;CS <=ADDRs;

end if;

when DATAs => -----------------------------------------------------------lpc_mode <= "100"; --4--IO write cycleif r_cnt ="001" thenr_data <= lad_i&r_data(7 downto 4); --LSB first from io cycler_cnt <= "000";lpc_wr <=’1’; --IO write must accurelpc_val <=’1’;CS <= TARs;data_count_i <= data_count_i +1;

elser_data <= lad_i&r_data(7 downto 4); --LSB first from io cycler_cnt <=r_cnt + 1;CS <= DATAs;

end if;when TARs => ------------------------------------------------------------lpc_mode <= "101"; --5if r_cnt ="001" thenif lpc_ack=’0’ thenlad_rising_o <= SYNC_LWAIT; --added to avoid trouble

elsif lpc_ack = ’1’ thenlad_rising_o <=SYNC_OK;CS <= SYNCs;

end if;lad_rising_oe <=’1’;

elsif lad_i = TAR_OK thenlpc_wr <=’0’;r_cnt <=r_cnt + 1;lad_rising_o <= TAR_OK; --drive to F on the busCS <= TARs;

elselpc_wr <=’0’;CS <= RESETs; --some error in protocol master must drive lad to "1111" on 1st TAR

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A. RTL code

end if;when SYNCs => -----------------------------------------------------------

lpc_mode <= "110"; --6--IO write cycle-- just passing r_lad on bus againlad_rising_o <= TAR_OK;CS <= LOCAL_TARs;

when LOCAL_TARs => ------------------------------------------------------lpc_mode <= "111"; --7

--IO write cyclelpc_wr <=’0’;lpc_val <= ’0’;lad_rising_oe <=’0’;CS <= RESETs;

end case;end if;

end process LPC;end rtl;

28

A. RTL code

SPI_Management

------------------------------------------------------------------------------------ Filename: SPI_Management.vhd-- Module name: Q7_boot_control---- Author(s): Martin Strömgren <martin.stromgren@aacmicrotec.com>---- Description: Manages the SPI interface, and control that the SPI doesn’t hang-- Requirements:----------------------------------------------------------------------------------

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SPI_Management is

Port (clk_spi : in std_logic;WB_clk : in std_logic;rst_i : in std_logic;SPI_MOSI : in std_logic;SPI_CS0 : in std_logic;rd_data : in std_logic_vector(31 downto 0);irq_spi : out std_logic;Rd_En : out std_logic;SPI_MISO : out std_logic);

end entity;

architecture rtl of SPI_Management is

type state is (STARTUP,TRANSFER,NEW_TRANSFER);

constant CHECK : std_logic_vector(31 downto 0) := X"03FFFFC0";constant OP_CODE : std_logic_vector(7 downto 0) := X"03";constant SPI_PAUS_MAX : std_logic_vector(7 downto 0) := X"0F";

signal mode : state;signal irq_spi_clk : std_logic;signal irq_mosi : std_logic;signal count_rst : std_logic; -- count_rst is pulled high when CS0 goes high so that MOSI_proc resets when activated.signal count_start : std_logic;signal Rd_En_SPI : std_logic;signal Rd_En_CS : std_logic;signal start : std_logic;signal Rd_ptr : std_logic_vector(4 downto 0);signal clk_cycle : std_logic_vector(6 downto 0);signal clk_previous : std_logic_vector(6 downto 0);signal received : std_logic_vector(31 downto 0);

begin-- Check if the clock is not working properlyProcess(WB_clk,rst_i)

variable counter : std_logic_vector(7 downto 0):= (others => ’0’);

begin

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A. RTL code

if rst_i = ’1’ thencounter := (others => ’0’);clk_previous <= (others => ’0’);irq_spi_clk <= ’0’;

elsif rising_edge(WB_clk) thenif SPI_CS0 = ’0’ thenif counter < SPI_PAUS_MAX and clk_cycle /= clk_previous thencounter := (others => ’0’);clk_previous <= clk_cycle;

elsif counter = 15 thenirq_spi_clk <= ’1’;counter := (others => ’0’);

elsecounter := counter + 1;

end if;end if;

end if;end process;

-- Process to handle the transmission over the SPI bus.MOSI_proc : Process(clk_spi,rst_i)

beginif rst_i = ’1’ thencount_start <= ’0’;irq_mosi <= ’0’;Rd_En_SPI <= ’0’;start <= ’1’;SPI_MISO <= ’0’;clk_cycle <= (others => ’0’);received <= (others => ’0’);Rd_ptr <= (others => ’1’);mode <= STARTUP;

elsif rising_edge(clk_spi) thenif SPI_CS0 = ’0’ then-- Start cycle after CS0 is pulled highif count_rst = ’1’ thenRd_En_SPI <= ’0’;received(31) <= SPI_MOSI;count_start <= ’1’;clk_cycle <= (0 => ’1’, others => ’0’);mode <= STARTUP;

end if;case mode iswhen STARTUP =>

if clk_cycle <= 31 thenreceived(31 - conv_integer(clk_cycle)) <= SPI_MOSI;count_start <= ’0’;

if clk_cycle = 30 thenmode <= TRANSFER;clk_cycle <= (others => ’0’);

elsif start = ’0’ and clk_cycle = 8 and received(31 downto 24) /= OP_CODE thenirq_mosi <= ’1’;

end if;

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A. RTL code

clk_cycle <= clk_cycle + 1;end if;

when TRANSFER =>SPI_MISO <= rd_data(conv_integer(Rd_ptr));

if Rd_ptr = 31 thenreceived(0) <= SPI_MOSI;Rd_ptr <= Rd_ptr - 1;if start = ’1’ thenstart <= ’0’;

end if;elsif Rd_ptr = 30 and received /= CHECK then

irq_mosi <= ’1’;Rd_ptr <= rd_ptr - 1;

elsif Rd_ptr = 1 thenRd_ptr <= Rd_ptr - 1;Rd_En_SPI <= ’1’;

elsif Rd_ptr = 0 thenmode <= STARTUP;Rd_En_SPI <= ’0’;Rd_ptr <= (others => ’1’);clk_cycle <= (others => ’0’);

elseRd_ptr <= Rd_ptr - 1;clk_cycle <= clk_cycle + 1;

end if;

when others =>null;

end case;end if;

end if;end process;

-- Process to deal with the situattion when CS0 goes high.Process(SPI_CS0, count_start)beginif SPI_CS0 = ’1’ thenRd_En_CS <= ’0’;count_rst <= ’1’;

elsif count_start = ’1’ thencount_rst <= ’0’;

elseRd_En_CS <= ’1’;

end if;end process;

irq_spi <= irq_mosi or irq_spi_clk;Rd_En <= Rd_En_CS and Rd_En_SPI;

end architecture;

31

A. RTL code

SPI_WB

--------------------------------------------------------------------------------- Filename : SPI_WB.vhd-- Module name : SPI_WB---- Author(s) : Martin Strömgren <martin.stromgren@aacmicrotec.com>---- Description : Wishbone interface to the Q7 boot controler.-- Requirements : As stated in the Å?AC CCSDS IP Requirement Specification,-- Doc nr: 204634 rev A (or highest)-- Design document: ÅAC CCSDS IP Detailed Design Document-- Doc nr: 204635-------------------------------------------------------------------------------

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;

library work;

entity SPI_WB isgeneric (ADDR_WIDTH : natural := 12;DATA_WIDTH : natural := 32);

port(-- WB interface common signalsclk_i : in std_logic;rst_i : in std_logic;

-- WB slave part signalswb_dat_i : in std_logic_vector(DATA_WIDTH-1 downto 0);wb_dat_o : out std_logic_vector(DATA_WIDTH-1 downto 0);wb_adr_i : in std_logic_vector(ADDR_WIDTH-1 downto 0);wb_we_i : in std_logic;wb_cyc_i : in std_logic;wb_stb_i : in std_logic;wb_ack_o : out std_logic;

-- Interruptint_o : out std_logic; -- Interrupt out

-- SPI Signalsrd_clk : in std_logic;Rd_EN : in std_logic;irq_spi : in std_logic;rd_data : out std_logic_vector(DATA_WIDTH - 1 downto 0);

-- LPC signalslpc_wr : in std_logic;lreset_n : in std_logic;lpc_val : in std_logic;lclk : in std_logic;lpc_ack : out std_logic;lpc_data : in std_logic_vector(7 downto 0);

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A. RTL code

-- Debugg signalslpc_mode : in std_logic_vector(2 downto 0);data_count : in std_logic_vector(31 downto 0);frame_count : in std_logic_vector(31 downto 0);start_count : in std_logic_vector(31 downto 0);addr_debug : in std_logic_vector(31 downto 0);addr_count : in std_logic_vector(31 downto 0));

end entity SPI_WB;

architecture rtl of SPI_WB is

constant FIFO_ADDR_BITS : natural := 8; -- 8 standard. Use 4 during testing.-- Interruptsconstant WR_FIFO : std_logic_vector(11 downto 0) := x"070";constant RD_PORT80 : std_logic_vector(11 downto 0) := x"074";constant RD_INTERRUPT : std_logic_vector(11 downto 0) := x"078";constant INTERRUPT_ENABLE : std_logic_vector(11 downto 0) := x"080";

-- Debugging addressesconstant LPC_DATA_COUNT : std_logic_vector(11 downto 0) := x"084";constant LPC_ADDR : std_logic_vector(11 downto 0) := x"088";constant LPC_ADDR_DEBUG : std_logic_vector(11 downto 0) := x"08C";constant LPC_START : std_logic_vector(11 downto 0) := x"090";constant LPC_FRAME : std_logic_vector(11 downto 0) := x"094";constant PORT80_FIFO_IRQ : std_logic_vector(11 downto 0) := x"098";constant LPC_MODE_ADDR : std_logic_vector(11 downto 0) := x"09C";

-- Component interrupt signalssignal irq_almost_empty : std_logic;signal irq_almost_full : std_logic;signal irq_empty : std_logic;signal irq_full : std_logic;signal irq_overflow : std_logic;signal irq_PORT80 : std_logic;signal irq_P80_time_out : std_logic;signal irq_P80_not_read : std_logic;signal underrun : std_logic;

-- FIFO signalssignal rd_count : std_logic_vector(FIFO_ADDR_BITS downto 0);signal wr_en : std_logic;signal wr_data : std_logic_vector(DATA_WIDTH - 1 downto 0);signal wr_count : std_logic_vector(FIFO_ADDR_BITS downto 0);

signal addr_count_i : std_logic_vector(31 downto 0);signal data_count_i : std_logic_vector(31 downto 0);

-- Component PORT80 signalssignal P80_register : std_logic_vector(7 downto 0);signal Rd_En_port80 : std_logic;signal rd_count_port80 : std_logic_vector(FIFO_ADDR_BITS downto 0);signal almost_empty_port80 : std_logic;signal underrun_port80 : std_logic;

signal wr_count_port80 : std_logic_vector(FIFO_ADDR_BITS downto 0);signal full_port80 : std_logic;signal almost_full_port80 : std_logic;

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A. RTL code

signal overflow_port80 : std_logic;

-- Interruptssignal irq_almost_empty_i : std_logic;signal irq_almost_full_i : std_logic;signal irq_empty_i : std_logic;signal irq_full_i : std_logic;signal irq_overflow_i : std_logic;signal irq_PORT80_i : std_logic;signal irq_P80_time_out_i : std_logic;signal irq_P80_not_read_i : std_logic;signal irq_spi_i : std_logic;

signal irq_almost_empty_en : std_logic;signal irq_almost_full_en : std_logic;signal irq_empty_en : std_logic;signal irq_full_en : std_logic;signal irq_overflow_en : std_logic;signal irq_PORT80_en : std_logic;signal irq_P80_time_out_en : std_logic;signal irq_spi_en : std_logic;

signal rst_P80_interrup : std_logic; -- Signal to reset the PORT80 interrupt

-- Wishbone relatedsignal wb_ack : std_logic; -- Ack out (internally)signal wb_dat : std_logic_vector(31 downto 0); -- Data out

begin--------------------------------------------------------------------------------- Registers for SPI-------------------------------------------------------------------------------wb_regs : process(clk_i, rst_i)beginif (rst_i = ’1’) then-- IRQsirq_almost_empty_i <= ’0’;irq_almost_full_i <= ’0’;irq_empty_i <= ’0’;irq_full_i <= ’0’;irq_overflow_i <= ’0’;irq_PORT80_i <= ’0’;irq_P80_time_out_i <= ’0’;irq_P80_not_read_i <= ’0’;irq_spi_i <= ’0’;

irq_almost_empty_en <= ’1’;irq_almost_full_en <= ’1’;irq_empty_en <= ’1’;irq_full_en <= ’1’;irq_overflow_en <= ’1’;irq_PORT80_en <= ’1’;irq_P80_time_out_en <= ’1’;irq_spi_en <= ’1’;

rst_P80_interrup <= ’0’;

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A. RTL code

wr_en <= ’0’;wr_data <= (others => ’0’);

-- WBwb_ack <= ’0’;wb_dat <= (others => ’0’);

elsif ((clk_i = ’1’) and clk_i’event) then

-- Interrupt handling (edge triggered)if (irq_almost_empty_i = ’0’ and irq_almost_empty = ’1’) thenirq_almost_empty_i <= ’1’;

end if;

if irq_almost_full_i = ’0’ and irq_almost_full = ’1’ thenirq_almost_full_i <= ’1’;

end if;

if (irq_empty_i = ’0’ and irq_empty = ’1’) thenirq_empty_i <= ’1’;

end if;

if irq_full_i = ’0’ and irq_full = ’1’ thenirq_full_i <= ’1’;

end if;

if irq_overflow_i = ’0’ and irq_overflow = ’1’ thenirq_overflow_i <= ’1’;

end if;

if irq_PORT80_i = ’0’ and irq_PORT80 = ’0’ thenirq_PORT80_i <= ’1’;

end if;

if irq_P80_time_out_i = ’0’ and irq_P80_time_out = ’1’ thenirq_P80_time_out_i <= ’1’;

end if;

if irq_P80_not_read_i = ’0’ and irq_P80_not_read = ’1’ thenirq_P80_not_read_i <= ’1’;

end if;

if irq_spi_i = ’0’ and irq_spi = ’1’ thenirq_spi_i <= ’1’;

end if;

----------------------------------------------------------------------------- wb write---------------------------------------------------------------------------if (wb_cyc_i = ’1’ and wb_stb_i = ’1’ and wb_we_i = ’1’) thenwb_ack <= ’1’;

------------------------------------------------------------------------- Address 0x70 Wright to FIFO (CHANGE THE CODE)-----------------------------------------------------------------------

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A. RTL code

if (wb_adr_i(ADDR_WIDTH -1 downto 2) = WR_FIFO(ADDR_WIDTH -1 downto 2)) thenwr_en <= ’1’;wr_data <= wb_dat_i;

end if;

------------------------------------------------------------------------- Address 0x78 SPI interrupts-----------------------------------------------------------------------if (wb_adr_i(ADDR_WIDTH -1 downto 2) = RD_INTERRUPT(ADDR_WIDTH -1 downto 2)) then-- Reset the regs by write ’1’ to clearif wb_dat_i(31) = ’1’ thenirq_overflow_i <= ’0’;

end if;

if wb_dat_i(27) = ’1’ thenirq_full_i <= ’0’;

end if;

if wb_dat_i(23) = ’1’ thenirq_empty_i <= ’0’;

end if;

if wb_dat_i(19) = ’1’ thenirq_almost_full_i <= ’0’;

end if;

if wb_dat_i(15) = ’1’ thenirq_almost_empty_i <= ’0’;

end if;

if wb_dat_i(11) = ’1’ thenirq_P80_time_out_i <= ’0’;

end if;

if wb_dat_i(8) = ’1’ thenirq_P80_not_read_i <= ’0’;

end if;

if wb_dat_i(7) = ’1’ thenirq_PORT80_i <= ’0’;rst_P80_interrup <= ’1’;

end if;

if wb_dat_i(3) = ’1’ thenirq_spi_i <= ’0’;

end if;end if;

------------------------------------------------------------------------- Address 0x80 Interrupts Enable-----------------------------------------------------------------------if (wb_adr_i(ADDR_WIDTH -1 downto 2) = INTERRUPT_ENABLE(ADDR_WIDTH -1 downto 2)) thenirq_overflow_en <= wb_dat_i(31);irq_full_en <= wb_dat_i(27);irq_empty_en <= wb_dat_i(23);irq_almost_full_en <= wb_dat_i(19);irq_almost_empty_en <= wb_dat_i(15);

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A. RTL code

irq_P80_time_out_en <= wb_dat_i(11);irq_PORT80_en <= wb_dat_i(7);irq_spi_en <= wb_dat_i(3);

end if;

--------------------------------------------------------------------------- Interrupt signal rst-------------------------------------------------------------------------

if rst_P80_interrup = ’1’ thenrst_P80_interrup <= ’0’;

end if;

if (wr_en = ’1’) thenwr_en <= ’0’;

end if;end if;

---------------------------------------------------------------------------------- wb read--------------------------------------------------------------------------------if (wb_cyc_i = ’1’ and wb_stb_i = ’1’ and wb_we_i = ’0’) thenwb_ack <= ’1’;wb_dat <= (others => ’0’);

------------------------------------------------------------------------- Address 0x74 Read PORT80 register (LPC BUS NOT YET IMPLEMENTED)-----------------------------------------------------------------------if (wb_adr_i(ADDR_WIDTH -1 downto 2) = RD_PORT80(ADDR_WIDTH -1 downto 2)) thenwb_dat(31 downto 8) <= (others => ’0’);wb_dat(7 downto 0) <= P80_register;Rd_En_port80 <= ’1’;

end if;

------------------------------------------------------------------------- Address 0x78 SPI interrupts-----------------------------------------------------------------------if (wb_adr_i(ADDR_WIDTH -1 downto 2) = RD_INTERRUPT(ADDR_WIDTH -1 downto 2)) thenwb_dat(31) <= irq_overflow_i;wb_dat(30 downto 28) <= (others => ’0’);wb_dat(27) <= irq_full_i;wb_dat(26 downto 24) <= (others => ’0’);wb_dat(23) <= irq_empty_i;wb_dat(22 downto 20) <= (others => ’0’);wb_dat(19) <= irq_almost_full_i;wb_dat(18 downto 16) <= (others => ’0’);wb_dat(15) <= irq_almost_empty_i;wb_dat(14 downto 12) <= (others => ’0’);wb_dat(11) <= irq_P80_time_out_i;wb_dat(10 downto 9) <= (others => ’0’);wb_dat(8) <= irq_P80_not_read_i;wb_dat(7) <= irq_PORT80_i;wb_dat(6 downto 4) <= (others => ’0’);wb_dat(3) <= irq_spi_i;wb_dat(2 downto 0) <= (others => ’0’);

end if;

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A. RTL code

------------------------------------------------------------------------- Address 0x80 Interrupts Enable-----------------------------------------------------------------------if (wb_adr_i(ADDR_WIDTH -1 downto 2) = INTERRUPT_ENABLE(ADDR_WIDTH -1 downto 2)) thenwb_dat(31) <= irq_overflow_en;wb_dat(30 downto 28) <= (others => ’0’);wb_dat(27) <= irq_full_en;wb_dat(26 downto 24) <= (others => ’0’);wb_dat(23) <= irq_empty_en;wb_dat(22 downto 20) <= (others => ’0’);wb_dat(19) <= irq_almost_full_en;wb_dat(18 downto 16) <= (others => ’0’);wb_dat(15) <= irq_almost_empty_en;wb_dat(14 downto 12) <= (others => ’0’);wb_dat(11) <= irq_P80_time_out_en;wb_dat(10 downto 8) <= (others => ’0’);wb_dat(7) <= irq_PORT80_en;wb_dat(6 downto 4) <= (others => ’0’);wb_dat(3) <= irq_spi_en;wb_dat(2 downto 0) <= (others => ’0’);

end if;

------------------------------------------------------------------------- Address 0x84 LPC_data-----------------------------------------------------------------------if (wb_adr_i(ADDR_WIDTH -1 downto 2) = LPC_DATA_COUNT(ADDR_WIDTH -1 downto 2)) thenwb_dat(31 downto 0) <= data_count;

end if;

------------------------------------------------------------------------- Address 0x88 LPC_addr-----------------------------------------------------------------------if (wb_adr_i(ADDR_WIDTH -1 downto 2) = LPC_ADDR(ADDR_WIDTH -1 downto 2)) thenwb_dat(31 downto 0) <= addr_count;

end if;

------------------------------------------------------------------------- Address 0x8C LPC_addr-----------------------------------------------------------------------if (wb_adr_i(ADDR_WIDTH -1 downto 2) = LPC_ADDR_DEBUG(ADDR_WIDTH -1 downto 2)) thenwb_dat(31 downto 0) <= addr_debug;

end if;

------------------------------------------------------------------------- Address 0x90 LPC_start-----------------------------------------------------------------------if (wb_adr_i(ADDR_WIDTH -1 downto 2) = LPC_START(ADDR_WIDTH -1 downto 2)) thenwb_dat(31 downto 0) <= start_count;

end if;

------------------------------------------------------------------------- Address 0x94 LPC_frame-----------------------------------------------------------------------if (wb_adr_i(ADDR_WIDTH -1 downto 2) = LPC_FRAME(ADDR_WIDTH -1 downto 2)) thenwb_dat(31 downto 0) <= frame_count;

end if;

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A. RTL code

------------------------------------------------------------------------- Address 0x98 PORT80_FIFO flags-----------------------------------------------------------------------if (wb_adr_i(ADDR_WIDTH -1 downto 2) = PORT80_FIFO_IRQ(ADDR_WIDTH -1 downto 2)) thenwb_dat(31 downto 29) <= (others => ’0’);wb_dat(28 downto 20) <= wr_count_port80;wb_dat(19 downto 17) <= (others => ’0’);wb_dat(16 downto 8) <= rd_count_port80;wb_dat(7 downto 6) <= (others => ’0’);wb_dat(5) <= underrun_port80;wb_dat(4) <= overflow_port80;wb_dat(3) <= almost_full_port80;wb_dat(2) <= almost_empty_port80;wb_dat(1) <= full_port80;wb_dat(0) <= irq_PORT80;

end if;

------------------------------------------------------------------------- Address 0x9C LPC_frame-----------------------------------------------------------------------if (wb_adr_i(ADDR_WIDTH -1 downto 2) = LPC_MODE_ADDR(ADDR_WIDTH -1 downto 2)) thenwb_dat(2 downto 0) <= lpc_mode;

end if;end if;

--------------------------------------------------------------------------- Bus acknowledge rst-------------------------------------------------------------------------if (wr_en = ’1’) thenwr_en <= ’0’;

end if;

if (Rd_En_port80 = ’1’) thenRd_En_port80 <= ’0’;

end if;

if (wb_ack = ’1’) thenwb_ack <= ’0’;

end if;end if;

end process wb_regs;

--------------------------------------------------------------------------------- Interrupts always enabled until fixed.-------------------------------------------------------------------------------int_o <= ((irq_almost_empty_i and irq_almost_empty_en) or

(irq_almost_full_i and irq_almost_full_en) or(irq_empty_i and irq_empty_en) or(irq_full_i and irq_full_en) or(irq_overflow_i and irq_overflow_en) or(irq_PORT80_i and irq_PORT80_en) or(irq_P80_time_out_i and irq_P80_time_out_en) or(irq_spi_i and irq_spi_en));

--------------------------------------------------------------------------------- Internal signals for output-------------------------------------------------------------------------------

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A. RTL code

wb_ack_o <= wb_ack;wb_dat_o <= wb_dat;

PORT80_FIFO: entity work.port80_fifoport map(rd_reset => rst_i,wr_reset => lreset_n,rd_clk => clk_i,wr_clk => lclk,

rd_en => Rd_En_port80,rd_data => P80_register,rd_count => rd_count_port80,empty => irq_PORT80,almost_empty => almost_empty_port80,underrun => underrun_port80,

wr_en => lpc_wr,wr_data => lpc_data,lpc_val => lpc_val,lpc_ack => lpc_ack,wr_count => wr_count_port80,full => full_port80,almost_full => almost_full_port80,overflow => overflow_port80);

FIFO: entity work.fifogeneric map(ADDR_BITS => FIFO_ADDR_BITS,DATA_BITS => DATA_WIDTH)

port map(rd_reset => rst_i,wr_reset => rst_i,rd_clk => rd_clk,wr_clk => clk_i,rd_en => Rd_En,rd_data => rd_data,rd_count => rd_count,empty => irq_empty,almost_empty => irq_almost_empty,underrun => underrun,wr_en => wr_en,wr_data => wr_data,wr_count => wr_count,full => irq_full,almost_full => irq_almost_full,overflow => irq_overflow);

end architecture rtl;

40

A. RTL code

Q7_boot_control

--------------------------------------------------------------------------------- Filename: Q7_boot_control.vhd-- Module name: Q7_boot_control_top---- Author(s): Martin Strömgren <martin.stromgren@aacmicrotec.com>---- Description: Connects the SPI_Management and SPI_WB components to connect-- them to their common signals.-- Requirements:-------------------------------------------------------------------------------

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;

library work;

entity Q7_boot_control isgeneric (ADDR_WIDTH : natural := 12;DATA_WIDTH : natural := 32);

port(-- WB interface common signalsWB_clk : in std_logic;rst_i : in std_logic;

-- WB slave part signalswb_dat_i : in std_logic_vector(DATA_WIDTH-1 downto 0);wb_dat_o : out std_logic_vector(DATA_WIDTH-1 downto 0);wb_adr_i : in std_logic_vector(ADDR_WIDTH-1 downto 0);wb_we_i : in std_logic;wb_cyc_i : in std_logic;wb_stb_i : in std_logic;wb_ack_o : out std_logic;

-- Interruptint_o : out std_logic; -- Interrupt out

-- SPI Signalsrd_data_o : out std_logic;clk_spi : in std_logic;SPI_MOSI : in std_logic;SPI_CS0 : in std_logic;

-- LPC signalslreset_n : in std_logic;lclk : in std_logic;lad_i : in std_logic_vector(3 downto 0);lad_o : out std_logic_vector(3 downto 0);lad_oe : out std_logic;lframe_n : in std_logic);

end entity Q7_boot_control;

architecture rtl of Q7_boot_control is

41

A. RTL code

-- SPI to WB signalssignal Rd_EN : std_logic;signal irq_spi : std_logic;

-- WB to SPI signalsignal rd_data : std_logic_vector(DATA_WIDTH - 1 downto 0);

-- LPC to WBsignal lpc_wr : std_logic;signal lpc_val : std_logic;signal lpc_data_reg : std_logic_vector(7 downto 0);

-- Debuging signalssignal lpc_mode : std_logic_vector(2 downto 0);signal addr_count : std_logic_vector(31 downto 0);signal addr_debug : std_logic_vector(31 downto 0);signal data_count : std_logic_vector(31 downto 0);signal start_count : std_logic_vector(31 downto 0);signal frame_count : std_logic_vector(31 downto 0);

-- WB to LPCsignal lpc_ack : std_logic;

begin

SPI_Management: entity work.spi_managementport map(clk_spi => clk_spi,WB_clk => WB_clk,rst_i => rst_i,SPI_MOSI => SPI_MOSI,SPI_CS0 => SPI_CS0,rd_data => rd_data,irq_spi => irq_spi,Rd_En => Rd_En,SPI_MISO => rd_data_o);

SPI_WB: entity work.spi_wbgeneric map(ADDR_WIDTH => 12,DATA_WIDTH => 32)

port map(clk_i => WB_clk,rst_i => rst_i,

-- WB slave part signalswb_dat_i => wb_dat_i,wb_dat_o => wb_dat_o,wb_adr_i => wb_adr_i,wb_we_i => wb_we_i,wb_cyc_i => wb_cyc_i,wb_stb_i => wb_stb_i,wb_ack_o => wb_ack_o,int_o => int_o,

42

A. RTL code

-- LPC interface signalslclk => lclk,lreset_n => lreset_n,lpc_wr => lpc_wr,lpc_val => lpc_val,lpc_ack => lpc_ack,lpc_data => lpc_data_reg,

-- Debugg signalslpc_mode => lpc_mode,addr_count => addr_count,addr_debug => addr_debug,data_count => data_count,frame_count => frame_count,start_count => start_count,

-- SPI signalsrd_clk => clk_spi,Rd_En => Rd_En,irq_spi => irq_spi,rd_data => rd_data);

lpc_iow: entity work.lpc_iowport map(

--LPC system signalslreset_n => lreset_n,lclk => lclk,lad_i => lad_i,lad_o => lad_o,lad_oe => lad_oe,lframe_n => lframe_n,

--memory interfacelpc_wr => lpc_wr,lpc_data_o => lpc_data_reg,lpc_val => lpc_val,lpc_ack => lpc_ack,

-- Debugg signalslpc_mode => lpc_mode,addr_count => addr_count,addr_debug => addr_debug,data_count => data_count,frame_count => frame_count,start_count => start_count);

end architecture rtl;

43

Appendix B. Logical schematics

SPI Management

Figure

B.1:

Logical

schematic

ofSP

IManager

44

B. Logical schematics

WB Interface

Figure

B.2:

Logical

schematic

ofthe

WBInterface.

The

yellowboxes

representthe

FIFOregisters.

45

B. Logical schematics

LPC Interface

Figure

B.3:

Logical

schematic

ofthe

LPCInterface.

46

Appendix C. Testing software

The software from which the test software was modi�ed is presented in this appendix.qstfb.c

1 // Qseven Faul t t o l e r a n t boo t s t r ap2 //3 // Copyright ÅAC Microtec AB 20154 // Author Danie l Skaborn5 // Edi ted by Martin Strömgren67 #include <s td i n t . h>8 #include <s td i o . h>9 #include <or1k−support . h>10 #include " q s f tb . h"11 #include "bootimage . h"1213 uint32_t regread ( uint32_t addr ) {14 return REG32( addr ) ;15 }16 void r egwr i t e ( uint32_t addr , uint32_t value ) {17 REG32( addr )=value ;18 return ;19 }2021 int main (void ) {22 uint32_t adre s s =0;23 uint32_t i , temp ;24 int32_t notdone=1;25 int32_t k =0;2627 // read the boot image to the data r e g i s t e r28 FILE * fp ;29 fp = fopen ( "H6069_000_005_189 . rom" , " rb" ) ;303132 f r ead ( data , 4 , 1048576 , fp ) ;333435 // enab l e FIFO low warning and New Port8036 r egwr i t e (QSFTB_INTENABREG, QSFTB_FIFILOW | QSFTB_NEWPE) ;37 p r i n t f ( "\n\ r " ) ;3839 p r i n t f ( "%d \n\ r " , s izeof ( data ) ) ;40 i f (IMAGE_SIZE > FIFO_SIZE) {41 for ( i =0; i<FIFO_SIZE ; i++) {42 r egwr i t e (QSFTB_SPIBUFF, data [ adre s s ] ) ;43 adre s s++;44 }

47

C. Testing software

45 p r i n t f ( "Image>FIFO \n\ r " ) ;46 } else i f (IMAGE_SIZE < FIFO_SIZE) {47 for ( i =0; i<IMAGE_SIZE; i++) {48 r egwr i t e (QSFTB_SPIBUFF, data [ adre s s ] ) ;49 adre s s++;50 }51 notdone = 0 ;52 p r i n t f ( "Image<FIFO \n\ r " ) ;53 }54 r egwr i t e (QSFTB_INTSTATUSREG,QSFTB_FIFILOW) ;55 r egwr i t e (QSFTB_INTSTATUSREG,QSFTB_FIFOEMPTY) ;5657 p r i n t f ( "Prepared f o r BOOT. . . \ n\ r " ) ;58 adre s s = 0 ;59 while ( notdone ) {60 temp = regread (QSFTB_INTSTATUSREG) ;61 p r i n t f ( "notdone loop \n\ r " ) ;62 i f ( temp & QSFTB_FIFILOW) { // push more data to b u f f e r63 i f ( (IMAGE_SIZE − adre s s ) < FIFO_SIZE) {64 for ( i=0 ; i <(IMAGE_SIZE−FIFO_LOWLEVEL) ; i++ ) {65 r egwr i t e (QSFTB_SPIBUFF, data [ adre s s ] ) ;66 adre s s++;67 i f ( adre s s > IMAGE_SIZE )68 notdone=0;6970 r egwr i t e (QSFTB_INTSTATUSREG,QSFTB_FIFILOW|QSFTB_FIFOEMPTY) ;71 }72 } else i f ( (IMAGE_SIZE − adre s s ) > FIFO_SIZE) {73 for ( i=0 ; i <(FIFO_SIZE−FIFO_LOWLEVEL) ; i++ ) {74 r egwr i t e (QSFTB_SPIBUFF, data [ adre s s ] ) ;75 adre s s++;76 i f ( adre s s > IMAGE_SIZE )77 notdone=0;7879 r egwr i t e (QSFTB_INTSTATUSREG,QSFTB_FIFILOW|QSFTB_FIFOEMPTY) ;80 }81 }82 } else i f ( temp & QSFTB_NEWPE) { // p r i n t the r e c e i v ed por t 80 code83 p r i n t f ( "%02X \n\ r " , regread (QSFTB_PORTEIGHTY) ) ;84 r egwr i t e (QSFTB_INTSTATUSREG, QSFTB_NEWPE) ;85 } else i f ( temp) { // unhangled f l a g , shou ld not occur86 p r i n t f ( " [%08X] \n\ r " , temp) ;87 }88 }8990 p r i n t f ( " Fu l l image booted \n\ r " ) ;9192 while (1 ) { // proceed d i s p l a y port80 codes93 temp = regread (QSFTB_INTSTATUSREG) ;94 i f ( temp & QSFTB_NEWPE) { // p r i n t the r e c e i v ed por t 80 code95 p r i n t f ( "%02X " , regread (QSFTB_PORTEIGHTY) ) ;96 r egwr i t e (QSFTB_INTSTATUSREG, QSFTB_NEWPE) ;97 }98 }99100 p r i n t f ( "This shouldn ' t have been pr in ted \n\ r " ) ;101 // never reached code

48

C. Testing software

102 return ;103 }

49

C. Testing software

qsftb.h

1 #ifndef QSFTB2 #define QSFTB_H34 #define QSFTB_INTSTATUSREG 0xb30000785 #define QSFTB_INTENABREG 0xb30000806 #define QSFTB_PORTEIGHTY 0xb30000747 #define QSFTB_SPIBUFF 0xb300007089 #define QSFTB_SPIERR 0x0000000810 #define QSFTB_NEWPE 0x0000008011 #define QSFTB_PETIMEOUT 0x0000080012 #define QSFTB_FIFILOW 0x0000800013 #define QSFTB_FIFOALMOSTFULL 0x0008000014 #define QSFTB_FIFOEMPTY 0x0080000015 #define QSFTB_FIFOFULL 0x0800000016 #define QSFTB_FIFOOVERRUN 0x800000001718 #define FIFO_SIZE 0x10019 #define FIFO_LOWLEVEL 0x022021 #endif

50

C. Testing software

bootimage.h

1 #ifndef BOOTIMAGE_H2 #include <s td i n t . h>3 #define BOOTIMAGE_H4 #define IMAGE_SIZE 104857656 uint32_t data [1048576 ]={} ;78 #endif

51