Minimum Implant Area-Aware Gate Sizing and Placement

Andrew B. Kahng and Hyein Lee

UC San Diego VLSI CAD Laboratory

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• Minimum Implant Area Constraint• Motivation• Prior Work• Minimum Implant Area-Aware Placement and Sizing• Experimental Results• Conclusions and Future Work

Outline

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• Implant (active) layers• Regions for ion implantation (= Vt)• Same as the entire cell region

in most cases

• Limitation of optical lithography (at λ=193nm) • Cannot make small patterns• Minimum implant area constraint ⇒ A small island of implant layer

is not allowed ⇒ Challenge for physical design in sub-22nm nodes

Minimum Implant Area (MinIA) Constraint

HL L

Minimum implant

width constraint

Violation

<Standard cell layout>

Implant area for P, NMOS

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• MUST consider neighbor cells’ size and Vt type• New physical design problems: placement and

sizing

Motivation: MinIA Constraint in Sub-22nm Nodes

H

MinIA constraint

WAS: OKIn previous nodes

L L

Minimum cell size> MinIA constraint

NOW: ViolationIn sub-22nm nodes

L LH

Minimum cell size < MinIA constraint

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• Traditional placement and sizing are separate problems• Placement problem: Place each cell without overlap• Gate sizing problem: Select size and Vt of each cell to minimize

power under timing/design constraints• MinIA-aware placement and sizing No longer ⇒

independent of each other in sub-22nm nodes• Sizing needs to understand placement• Example: Changing Vt can create MinIA violations depending on

the placement

• Placement, sizing and MinIA constraints MUST be considered together

Motivation: MinIA-Aware Placement and Sizing

LL L HL L

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• Redefine the traditional placement and gate sizing problems to capture new placement, sizing and MinIA rule interaction

• Propose placement and sizing heuristics to optimize power under the MinIA constraint

• Our proposed methods are implemented in C++ and incorporated into a standard P&R flow

• Our placement heuristic fixes almost all of violations while commercial tools cannot fix up to 64% of violations

• Our sizing and placement heuristic achieves comparable power reduction to the conventional sizing approach without creating MinIA violations

Our Work

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• Gate sizing, and co-optimization with placement• Method to minimize power and ECO cost• Sequential optimization of placement and sizing

• Linear (1-D) placement• Graph model-based approach• Dynamic programming

• Layout effect-aware placement• STI stress-aware placement

• No work considers the MinIA rules in placement and/or sizing

Prior Work: Literature

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• Case study of P&R tools• Technology: 45nm technology with modified MinIA rules • Commercial P&R tools fix MinIA violations by inserting filler cells • Result of two commercial tools

• Commercial tools cannot fix all of MinIA violations

Prior Work: Commercial P&R Tools

aes dma0%

10%20%30%40%50%60%70%

P&R1 P&R2

Rem

aini

ng M

inIA

vi

olati

ons (

%)

50% remaining violations

9

• Minimum Implant Area Constraint• Motivation• Prior Work• Minimum Implant Area-Aware Placement and Sizing• Experimental Results• Conclusions and Future Work

Outline

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• Problem: MinIA-aware sizing and placement• Minimize power • Subject to:

• Minimum implant area constraints• Timing constraints (slack, transition time)• No overlap in placement

• Sizing and placement are performed sequentially

Problem Formulation

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• We perform sizing and placement sequentially in our optimization

• Three combinations of sizing and placement problems• Free sizing and MinIA-aware placement

• Allow MinIA violations and fix the violations later• Strict MinIA-aware sizing

• Do not allow any MinIA violations during sizing• Relaxed MinIA-aware sizing and MinIA-aware

placement• Allow fixable MinIA violations• Used for our optimizer

Sequential Optimization

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• Levers to solve MinIA violationsHow to Fix MinIA Violations?

HL L HL L

HL L LL L

<Move neighbor cells> <Downsize neighbor cells>

<Change Vt of cells>

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ViolationWe must make the blue area larger than MinIA constraint (dashed red box)

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Our Heuristic Flow: Placement

Insert same Vt filler cells around violating cells

Vt swap the violating cell/its neighbor cells

to match Vt

Calculate whitespacefor violating cells Move neighbor cells

to obtain spacing

Insert filler cells

Downsize neighbor cells to obtain spacing

#Vio = 0?N

finish

#Vio = 0?NY

finish

#Vio = 0?N

Yfinish

Insert filler cells

finish

Y

timing check is needed

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Our Heuristic Flow: Sizing and Placement

Add the cell to the candidate list

Calculate sensitivity

Pick the most promising cellAnd commit

Fix MinIA violations

Fixable?Y

discard

Timing feasible?N

Y

N

Revert

Sensitivity function = ∆leakage/∆TNS

•TNS = total negative slack

•∆TNS is calculated considering sizing and MinIA costs

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Our OptimizerP&R Design (DEF)/LEF

MinIA-Aware Placement/Sizing

min implant layer rulesgeometry infodef/lef2oa

Timer Tool/P&R Tool

(DB update, ECO sizing/placement/

routing)

MinIA Violation Check

Tcl socket

OADB

Final P&R Design

Timing updateApply solutions

save P&R Design

MinIAOpt

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• Minimum Implant Area Constraint• Motivation• Prior Work• Minimum Implant Area-Aware Placement and Sizing• Experimental Results• Conclusions and Future Work

Outline

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• Technology: 45nm technology with modified MinIA rules• Testcases

• dma, mpeg, aes and jpeg from OpenCore

• High utilization (75~82%) is used• Many small cells are used

(% of minimum size cells : 59~84%)• Additional testcases (aes_var*)

with different Vt cell distributions• Various minimum implant width constraints

Experimental Setup

Testcase #inst. Orig. #Vio.dma 1168 193

mpeg 7121 693aes 9611 1146jpeg 44911 7864

aes_var1 9611 2955aes_var2 9611 2558aes_var3 9611 1816

Const. Min. width (# sites) % of violating lib. cells (in a lib.)

Const1 4 3%

Const2 6 12%

Const3 7 28%

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• How much MinIA violations can be fixed by our placement heuristic?

• Placement results with Const3

• Our approach fixes almost all of violations while commercial tools cannot fix up to 64% of violations

Experimental Results: Placement

dmampeg aes

jpeg

aes_var1

aes_var2

aes_var3

0%10%20%30%40%50%60%70%

Commercial Ours

Rem

aini

ng M

inIA

vio

-la

tions

(%)

64% vs. 3%

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• Which sizing heuristics show good results w.r.t. both power reduction and MinIA constraints?

• Comparison results between the three heuristics

• Our sizing heuristic (3) does not increase MinIA violations while maintaining low leakage power

dma mpeg2 aes jpeg0%

10%20%30%40%

(1) free sizing and MinIA place (2) Strict sizing and MinIA place(3) Relaxed sizing and MinIA placement

Leak

age

Redu

ction

(%)

Experimental Results: Sizing and Placement

dma mpeg2 aes jpeg0%

50%100%150%200%

∆ M

inIA

Vio

. (%

)

F

(1) Best leakage reduction(1) Many MinIA violations(2) Some MinIA violations (2) Worst leakage reduction(3) Small MinIA violations (3) Good leakage reduction

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• We address new gate sizing and placement problems arising in sub-22nm VLSI due to MinIA constraint

• We propose a heuristic sizing and placement method considering MinIA

• Our placement heuristic fixes almost all of violations while commercial tools cannot fix up to 64% of violations

• Our sizing and placement heuristic achieves comparable power reduction without creating MinIA violations

Conclusion

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• Single-row placement with MinIA fixing by using dynamic programming

• Unified placement, sizing and Vt-swap heuristics• Multi-row placement consideration

Future Work

MinIA violations

HL L

HL L

HStandard cell row1

Standard cell row2

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THANK YOU!