mikroprocesori-predavanje

Harvard architecture is a newer concept than von-Neumann's. It rose out of the need to speed up the work of a microcontroller. In Harvard architecture, data bus and address bus are separate. Thus a greater flow of data is possible through the central processing unit, and of course, a greater speed of work. Separating a program from data memory makes it further possible for instructions not to have to be 8-bit words. It is also typical for Harvard architecture to have fewer instructions than von-Neumann's, and to have instructions usually executed in one cycle. Microcontrollers with Harvard architecture are also called "RISC microcontrollers". RISC stands for Reduced Instruction Set Computer. Microcontrollers with von-Neumann's architecture are called 'CISC microcontrollers'. Title CISC stands for Complex Instruction Set Computer.

Mikrokontroler PIC16F876 je RISC arhitekture, kapaciteta programske FLASH memorije 8192 rei dok kapacitet RAM memorije iznosi 368 bajta. Komponenta poseduje i internu EEPROM memoriju podataka kapaciteta 256 bajta u koju se programski mogu skladititi odredjeni konstantni parametri. Maksimalna frekvencija taktovanja je 20 MHz. Sve instrukcije (35) izvravaju se u jednom ciklusu, osim instrukcija grananja za ije izvrenje su potrebna dva. Mikrokontroler je opremljen brzim 10-bitnim petokanalnim A/D konvertorom sa registrom sukcesivnih aproksimacija, serijskim komunikacionim interfejsom (USART), PWM modulom i standardnom opremom ovih komponenata brojaima/tajmerima. Radi zatite od eventualnih greaka u programu, usled industrijskih smetnji, ugradjen je tkzv. watchdog timer-broja snabdeven sopstvenim RC oscilatorom. Stek mikrokontrolera nije u sastavu interne RAM memorije ve predstavlja zasebnu celinu od osam nivoa.

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INSTRUKCIJSKI CIKLUS

PIPELINING (Protona obrada instrukcija)

BLOK DIJAGRAM PIC16F876

Postoje dva tajmera kojima se realizuje neophodno kanjenje pri uspostavljanju napajanja mikrokontrolera. Jedan od njih je Oscillator Start-up Timer (OST) koji dri mikrokontroler u stanju RESET dok se ne stabilie kristalni oscilator. Drugi je Power-up Timer (PWRT) koji obezbedjuje fiksno kanjenje od 72 ms (nominalno). Projektovan je da zadri ip u stanju RESET dok se ne stabilie napajanje mikrokontrolera. Zahvaljujui prisustvu ova dva tajmera u ipu najvei broj aplikacija nee imati potrebu za eksternim, specijalnim kolom za resetovanje mikrokontrolera.

4 tipa kristalnih oscilatora za taktovanje mikrokontrolera LP, XT, HS, RC.

RC oscilator je jeftino reenje kada striktni tajming nije od znaaja. LP oscilator je od znaaja za nisku potronju mikrokontrolera.

MEMORIJSKA MAPA

Svaki mikrokontroler PIC16F87X poseduje tri memorijska bloka. Programsku FLASH memoriju kapaciteta (8k x 14b), memoriju podataka (RAM) kapaciteta 368 bajta i memoriju podataka tipa EEPROM za trajno uvanje programskih konstanti i nepromenljivih parametara programa. Programska memorija i memorija podataka imaju odvojene magistrale (RISC arhitektura) tako da su konkurentni pristupi dozvoljeni. Programski broja PIC16F876/877 mikrokontrolera (broja instrukcija) je 13-bitni tako da moe adresirati 8k x 14 prostora programske memorije. RESET vektor je na adresi 0000h a interapt vektor na adresi 0004h.

ORGANIZACIJA PROGRAMSKE MEMORIJE

Organizacija Memorije podataka (RAM)

Memorija podataka je podeljena u 4 banke (stranice) koje sadre Registre Opte Namene (General Purpose Registers - GPR) i Registre Specijalne Namene (Special Function Registers - SFR). Bitovi RP1 (STATUS) i RP0 (STATUS) STASTUS-nog registra su bitovi za selekciju memorijskih banaka.

RP1 RP0 Bank 0 0 0 0 1 1 1 0 2 1 1 3

Kapacitet svake memorijske banke je 128 bajta. Nie lokacije svake banke rezervisane su za SFR registre dok su iznad ovih registara GPR registri implementirani kao SRAM (statiki RAM). Sve memorijske banke sadre SFR registre. Neki esto

korieni SFR registri kao na primer STATUS, INTCON, PCLATH, OPTION_REG itd. poseduju svoje kopije u drugim bankama to se ini u cilju redukcije koda i breg pristupa registrima.

GPR registri

Ovim registrima se moe pristupati direktno ili indirektno preko FSR (File Select Register).

SFR registri

To su registri koje koristi CPU mikrokontrolera i njegovi periferijski moduli. Koriste se za kontrolu zahtevane operacije uredjaja. Kao i GPR registri i ovi registri su implementirani kao SRAM. Mogu se podeliti na dve grupe: SFR registri CPU jezgra i SFR perigerala.

Organizacija DATA EEPROM memorije

EEADR adresni registar EEPROM-a EEDATA registar podataka EEPROM-a

Programski broja

The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC) are not readable, but are indirectly writable through the PCLATH register. On any RESET, the upper bits of the PC will be cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH PCH).

AKUMULATOR

W working register 8-bitni registar

Assembler Generating Absolute Code

Absolute code is the default output from the MPASM assembler. This process is shown below.

When a source file is assembled in this manner, all variables and routines used in the source file must be defined within that source file, or in files that have been explicitly included by that source file. If assembly proceeds without errors, a hex file will be generated, containing the executable machine code for the target device. This file can then be used with a debugger to test code execution or with a device programmer to program the microcontroller.

DIREKTIVE

Directives are assembler commands that appear in the source code but are not usually translated directly into opcodes. They are used to control the assembler: its input, output, and data allocation.

Many of the assembler directives have alternate names and formats. These may exist to provide backward compatibility with previous assemblers from Microchip and to be compatible with individual programming practices. If portable code is desired, it is recommended that programs be written using the specifications contained here.

Generalni format instrukcija

Tri kategorije instrukcija: bajt orijentisane, bit orijentisane i literalne i controlne instrukcije.

Bajt orijentisane registarske instrukcije 14-bitnog procesorskog jezgra

13 8 7 6 0 opcode d 7 bit file reg. address

d-0 W is destination reg d=1 F is destination reg.

Hex Mnemonic Description Function

07ff ADDWF f,d Add W and f W + f-> d 05ff ANDWF f,d AND W and f W .AND. f-> d 018f CLRF f Clear f 0->f 0100 CLRW Clear W 0->W 09ff COMF f,d Complement f .NOT. f->d 03ff DECF f,d Decrement f f - 1->d 0Bff DECFSZ f,d Decrement f, skip if zero f - 1->d, skip if 0 0Aff INCF f,d Increment f f + 1->d

0Fff INCFSZ f,d Increment f, skip if zero f + 1->d, skip if 0 04ff IORWF f,d Inclusive OR W and f W .OR. f->d 08ff MOVF f,d Move f f->d 008f MOVWF f Move W to f W->f 0000 NOP No operation 0Dff RLF f,d Rotate left f f(n)->dest(n+1), f(7)->C, C->dest(0) 0Cff RRF f,d Rotate right f f(n)->dest(n-1), f(0)->C, C->dest(7) 02ff SUBWF f,d Subtract W from f f - W->d 0Eff SWAPF f,d Swap halves f f(0:3)f(4:7)->d 06ff XORWF f,d Exclusive OR W and f W .XOR. f->d

Bit orijentisane registarske instrukcije 14-bitnog procesorskog jezgra

13 10 9 7 6 0 opcode b (bit) 7 bit file reg. address

b - 3 bit, bit address


1bff BCF f,b Bit clear f 0->f(b) 1bff BSF f,b Bit set f 1-> f(b) 1bff BTFSC f,b Bit test, skip if clear skip if f(b) = 0 1bff BTFSS f,b Bit test, skip if set skip if f(b) = 1

Literalne i kontrolne instrukcije 14-bitnog procesorskog jezgra

13 8 7 0 opcode K (literal)

13 11 10 0 opcode K (literal)

CALL and GOTO instructions only


3Ekk ADDLW k Add literal to W k + W->W 39kk ANDLW k AND literal and W k .AND. W->W 2kkk CALL k Call subroutine PC + 1->TOS, k->PC 0064 CLRWDT T Clear watchdog timer 0->WDT (and Prescaler if assigned) 2kkk GOTO k Goto address (k is nine bits) k->PC(9 bits) 38kk IORLW k Incl. OR literal and W k .OR. W->W 30kk MOVLW k Move Literal to W k->W 0062 OPTION Load OPTION register W->OPTION Register 0009 RETFIE Return from Interrupt TOS->PC, 1->GIE 34kk RETLW k Return with literal in W k->W, TOS->PC 0008 RETURN Return from subroutine TOS->PC 0063 SLEEP Go into Standby Mode 0->WDT, stop oscillator 3Ckk SUBLW k Subtract W from literal k - W->W 006f TRIS f Tristate port f W->I/O control reg f 3Akk XORLW k Exclusive OR literal and W k .XOR. W->W

TABELA SETA INSTRUKCIJA

MPASM asembler podrava sledee radix forme (brojne osnove): hexadecimal, decimal, octal, binary, i ASCII. Podrazumevani radix je hexadecimalni; ova forma radix-a odreuje formu dodeljenih konstanti u object fajlu kada radix nije eksplicitno specificiran asemblerskom direktivom. Tabela pokazuje razliite radix specifikacije.

Brojne osnove

Type Syntax Example

Decimal D'' D'100' . .100

Hexadecimal H'' H'9f' 0x 0x9f

Octal O'' O'777'

Binary B'' B'00111001'

ASCII A'' A'C' '' 'C'

Least Most Significant Character (3 bit) ---> Significant Character Hex 0 1 2 3 4 5 6 7 (4 bit) | 0 NUL DLE Space 0 @ P ` p | 1 SOH DC1 ! 1 A Q a q V 2 STX DC2 " 2 B R b r

3 ETX DC3 # 3 C S c s 4 EOT DC4 $ 4 D T d t 5 ENQ NAK % 5 E U e u 6 ACK SYN & 6 F V f v 7 Bell ETB ' 7 G W g w 8 BS CAN ( 8 H X h x 9 HT EM ) 9 I Y i y A LF SUB * : J Z j z B VT ESC + ; K [ k { C FF FS , < L \ l | D CR GS = M ] m } E SO RS . > N ^ n ~ F SI US / ? O _ o DEL

Tabela 7-bitnih ASCII karaktera.

ASEMBLERSKE DIREKTIVE

Vrste asemblerskih direktiva:

Kontrolne direktive (Control Directives) Uslovne asemblerske direktive (Conditional Assembly Directives) Direktive za podatke (Data Directives) Listing direktive (Listing Directives) Makro direktive (Macro Directives) Direktive za objektne datoteke (Object File Directives)

Kontrolne direktive

Directive Description Syntax

CONSTANT Declare Symbol Constant constant [= ,..., [= ] ] #DEFINE Define a Text Substitution Label #define [[(,...,)]] END End Program Block end EQU Define an Assembly Constant equ #INCLUDE Include Additional Source File include include "" ORG Set Program Origin org PROCESSOR Set Processor Type processor RADIX Specify Default Radix radix SET Define an Assembler Variable set #UNDEFINE Delete a Substitution Label #undefine VARIABLE Declare Symbol Variable variable [= ,, [= ] ]

Uslovne asemblerske direktive


ELSE Begin Alternative Assembly Block to IF else ENDIF End Conditional Assembly Block endif ENDW End a While Loop endw IF Begin Conditionally Assembled Code Block if IFDEF Execute If Symbol is Defined ifdef IFNDEF Execute If Symbol is Not Defined ifndef WHILE Perform Loop While Condition is True while

Direktive podataka


_ _BADRAM Specify invalid RAM locations _ _badram CBLOCK Define a Block of Constants cblock [] _ _CONFIG Set configuration fuses _ _config OR _ _config , DA Store Strings in Program Memory [] da [, , ..., ] DATA Create Numeric and Text Data data ,[,,...,]

data ""[,"",...] DB Declare Data of One Byte db [,,...,] DE Declare EEPROM Data de [,,...,] DT Define Table dt [,,...,] DW Declare Data of One Word dw [,,...,] ENDC End an Automatic Constant Block endc FILL Specify Memory Fill Value fill , _ _IDLOCS Set ID locations _ _idlocs _ _MAXRAM Specify maximum RAM address _ _maxram RES Reserve Memory res

Listing direktive


ERROR Issue an Error Message error "" ERRORLEVEL Set Messge Level errorlevel 0|1|2| LIST Listing Options list [[,...,]] MESSG Create User Defined Message messg "" NOLIST Turn off Listing Output nolist PAGE Insert Listing Page Eject page SPACE Insert Blank Listing Lines space [] SUBTITLE Specify Program Subtitle subtitl "" TITLE Specify Program Title title ""

Makro direktive


ENDM End a Macro Definition endm EXITM Exit from a Macro exitm EXPAND Expand Macro Listing expand LOCAL Declare Local Macro Variable local [,] MACRO Declare Macro Definition macro [,...,] NOEXPAND Turn off Macro Expansion noexpand

Direktive OBJECT fajla


BANKISEL Generate RAM bank selecting code for ind. addressing bankisel BANKSEL Generate RAM bank selecting code banksel CODE Begins executable code section [] code [] EXTERN Declares an external label extern [ ,] GLOBAL Exports a defined label extern [ .] IDATA Begins initialized data section [] idata [] PAGESEL Generate ROM page selecting code pagesel UDATA Begins uninitialized data section [] udata [] UDATA_ACS Begins access uninitialized data section [] udata_acs [] UDATA_OVR Begins overlayed uninitialized data section [] udata_ovr [] UDATA_SHR Begins shared uninitialized data section [] udata_shr []

Primeri kontrolnih direktiva

constant = [...,=] Description Creates symbols for use in MPASM assembler expressions. Constants may not be reset after having once been initialized, and the expression must be fully resolvable at the time of the assignment. This is the principal difference between symbols declared as constant and those declared as variable, or created by the set directive. Otherwise, constants and variables may be used interchangeably in expressions.

Example Variable RecLength=64 ; Set Default RecLength constant BufLength=512 ; Init BufLength RecLength may be reset later in RecLength=128 constant MaxMem=RecLength+BufLength ;CalcMaxMem

#define [] Description This directive defines a text substitution string. Wherever is encountered in the assembly code, will be substituted. Using the directive with no causes a definition of to be noted internally and may be tested for using the ifdef directive. This directive emulates the ANSI 'C' standard for #define. Symbols defined with this method are not available for viewing using MPLAB IDE.

Example #define length 20 #define control 0x19,7

#define position(X,Y,Z) (Y-(2 * Z +X)) : test_label dw position(1, length, 512) bsf control ; set bit 7 in f19

#undefine Description is an identifier previously defined with the #define directive. It must be a valid MPASM assembler label. The symbol named is removed from the symbol table. Example #define length 20 : #undefine length

end Description Indicates the end of the program. Example list p=17c42 : ; executable code : ; end ; end of instructions

equ Description The value of is assigned to . Example four equ 4 ; assigned the numeric value of 4 to label four

#include #include "" Description The specified file is read in as source code. The effect is the same as if the entire text of the included file were inserted into the file at the location of the include statement. Upon end-of-file, source code assembly will resume from the original source file. Up to six levels of nesting are permitted. Up to 256 include files are allowed. may be enclosed in quotes or angle brackets. If a fully qualified path is specified, only that path will be searched. Otherwise, the search order is: current working directory, source file directory, MPASM assembler executable directory.

Example #include "c:\sys\sysdefs.inc" ; system defs #include ; register defs

[] org Description Set the program origin for subsequent code at the address defined in . If is specified, it will be given the value of the . If no org is specified, code generation will begin at address zero. For PIC18CXXX devices, only even values are allowed. This directive may not be used when generating an object file. Example int_1 org 0x20 ; Vector 20 code goes here int_2 org int_1+0x10 ; Vector 30 code goes here

processor Description Sets the processor type to . Example processor 16C54

radix Description

Sets the default radix for data expressions. The default radix is hex. Valid radix values are: hex - hexadecimal (base 16) dec - decimal (base 10) oct - octal (base 8)

Example radix dec

set Description is assigned the value of the valid MPASM assembler expression specified by . The set directive is functionally equivalent to the equ directive except that set values may be subsequently altered by other set directives. Example area set 0 width set 0x12 length set 0x14 area set length * width length set length + 1

variable [=][,[=]...] Description Creates symbols for use in MPASM assembler expressions. Variables and constants may be used interchangeably in expressions. The variable directive creates a symbol that is functionally equivalent to those created by the set directive. The difference is that the variable directive does not require that symbols be initialized when they are declared. The variable values cannot be updated within an operand. You must place variable assignments, increments, and decrements on separate lines.

Example Variable RecLength=64 ; Set Default RecLength

Kontrolne direktive

#DEFINE Kada god se pojavi u programu menja se sa .

#define

#define ukljueno 1 #define iskljueno 0

#INCLUDE Ukljuivanje dodatne datoteke u program, koja se pie izmeu navodnika ili znakova .

#include #include "subprog.asm"

CONSTANT Zadavanje konstanog broja preko tekstualnog imena.

constant MAXIMUM=100 constant Length=30

VARIABLES Slino predhodnom, ali i posle zadavanja direktive moe se menjati vrednost.

variable level=20 variable time=13

SET Definie asemblersku promenljivu. Mogua ponovna definicija.

set

level set 0 length set 12

EQU definie asemblersku konstantu.

set

five equ 5 six equ 6 seven equ 7

ORG Odreuje poetnu adresu.

org

Start org 0x00

END Kraj programa

end

Uslovne asemblerske direktive

IF Ako se ispuni , onda se izvrava ona naredba to sledi, a ako ne onda ona to sledi ELSE ili ENDIF. Postoji i mogunost ugnedenog IF ispitivanja.

if

if nivo=100 goto PUNI else goto PRAZNI endif

WHILE Izvravanje dela programa sve dok je uslov zadovoljen. while ...

endw

while i

endw

IFDEF Izvravanje dela programa u sluaju da je simbol (asemblerska promenljiva) definisan.

#define test ...

ifdef test ...

endif

IFNDEF Izvrava deo programa i ako nije predhodno definisan simbol ili je obrisan sa direktivom #UNDEFINE.

#define test ...

#undefine test ...

ifndef test ...

endif

Direktive za podatke

CBLOCK Definie niz konstanti.

Cblock [] [:], [:]... endc

cblock 0x20 simbolika imena konstanti sa inkrementiranim adresama endc

DB Definie podatak duine jednog bajta. []db [, ,.....,]

db 't', 00f, 'e', 's', 012

DE Definie bajt prvenstveno u EEPROM-u.

[] de [, ,....., ]

de "Version 1.0" , 0

DT Definie tabelu podataka preko serije RETLW instrukcija.

[] dt [, ,........., ]

dt "Message", 0 dt first, second, third

_CONFIG Podeava konfiguracione bitove i to za oscilator, sigurnosni tajmer i kolo za resetovanje. Prvo se mora odrediti procesor sa PROCESSOR direktivom.

__CONFIG _CP_OFF & _WDT_ON & _BODEN_ON & _PWRTE_ON & _XT_OSC & _WRT_ENABLE_ON & _LVP_ON & _DEBUG_OFF & _CPD_OFF

PROCESSOR Definie se mikrokontrolerski model.

processor 16F876

NAINI ADRESIRANJA

RAM se moe adresirati na dva naina: direktno i indirektno. Direktno se obavlja kroz 9-bitnu adresu tako to se na 7-bitnu adresu iz instrukcije (op kod) dodaje dva bita RP1 i RP2 iz STATUS registra. Bilo koji pristup SFR registrima se moe uzeti kao primer direktnog adresiranja.

bsf STATUS, RP0 ;Bankl movlw 0xFF ;w=0xFF movwf TRISA ;adresa TRISA registra dobijena je iz instrukcije movwf

Indirektno adresiranje se izvodi pomoi IRP bita STATUS registra i FSR registra. Lokaciji se pristupa preko INDF registra koji sadri adresu na koju ukazuje FSR. Drugim reima, bilo koja instrukcija koja koristi INDF registar u stvari pristupa podacima na koje ukazuje FSR registar (INDF sadraj na ta ukazuje FSR, INDirektni F). Na primer, ako jedan GPR registar na adresi 0Fh sadri vrednost 20. Upisujui vrednost 0Fh u FSR, dobiemo pokaziva na adresi 0Fh. Ako proitamo vrednost INDF registra rezultat e biti 20, to znai da smo proitali prvi registar bez njegovog direktnog adresiranja.

Primer brisanja prvih 16 lokacija RAM-a od 20h do 2Fh (indirektno adresiranje)

MOVLW 0x20 ;initialize pointer MOVWF FSR ;to RAM NEXT: CLRF INDF ;clear INDF register INCF FSR,F ;inc pointer BTFSS FSR,4 ;all done? GOTO NEXT ;no clear next

ASEMBLER

Proces prevoenja generie datoteke tipa: HEX, ERR i LST. Prvom se puni programska memorija mikrokontrolera, druga sadri spisak greki i upozorenja. Trea je najkorisnija za programera, jer sadri, asdrese, programski kod, greke i dodatne informacije poput grafikog zauzea memorije.

Osnovni elementi asemblerskog jezika su sledei:

- labele, - instrukcije, - operandi, - direktive i - komentari.

Labele su tekstualni opisi nekog dela programa, i one se obino koriste kao taka u programu gde e doi do skoka. Mora poeti u prvoj koloni sa abedecenim znakom ili sa znakom _ a najvea duina iznosi 32 karaktera.

Instrukcije ili naredbe se piu za odreenu seriju mikrokontrolera po pripadajuim sintaksnim pravilima.

Operandi su delovi instrukcije i oznaavaju registar, varijablu ili konstantu.

Komentari se unose radi jasnoe i dokumetovanja a piu se iza instrukcija ili u praznom redu sa obaveznim znakom ; na poetku. Ne prevode se.

Direktive su asemblerske komande koje se pojavljuju u izvornom kodu ali se uobiajeno ne prevode u operacione kodove. Koriste se za kontrolu asemblerskog programa i alokacije podataka. Ne zavise od tipa mikrokontrolera.

STRUKTURA ASEBMLERSKOG PROGRAMA

;********************************************************************** ; This file is a basic code template for assembly code generation * ; on the PICmicro PIC16F876. This file contains the basic code * ; building blocks to build upon. * ; * ; If interrupts are not used all code presented between the ORG * ; 0x004 directive and the label main can be removed. In addition * ; the variable assignments for 'w_temp' and 'status_temp' can * ; be removed. * ; * ; * ;********************************************************************** ; * ; Filename: xxx.asm * ; Date: * ; File Version: * ; * ; Author: * ; Company: * ; * ; * ;********************************************************************** ; *

; Files required: * ; * ; * ; * ;********************************************************************** ; * ; Notes: * ; * ; * ;**********************************************************************

list p=16f876 ; list directive to define processor #include ; processor specific variable definitions

__CONFIG _CP_OFF & _WDT_ON & _BODEN_ON & _PWRTE_ON & _RC_OSC & _WRT_ENABLE_ON & _LVP_ON & _DEBUG_OFF & _CPD_OFF

; '__CONFIG' directive is used to embed configuration data within .asm file. ; The labeles following the directive are located in the respective .inc file.

;***** VARIABLE DEFINITIONS w_temp EQU 0x70 ; variable used for context saving status_temp EQU 0x71 ; variable used for context saving pclath_temp EQU 0x72 ; variable used for context saving

;********************************************************************** ORG 0x000 ; processor reset vector clrf PCLATH ; ensure page bits are cleared goto main ; go to beginning of program

ORG 0x004 ; interrupt vector location movwf w_temp ; save off current W register contents movf STATUS,w ; move status register into W register movwf status_temp ; save off contents of STATUS register movf PCLATH,w ; move pclath register into w register movwf pclath_temp ; save off contents of PCLATH register

; isr code can go here or be located as a call subroutine elsewhere

movf pclath_temp,w ; retrieve copy of PCLATH register movwf PCLATH ; restore pre-isr PCLATH register contents movf status_temp,w ; retrieve copy of STATUS register movwf STATUS ; restore pre-isr STATUS register contents swapf w_temp,f swapf w_temp,w ; restore pre-isr W register contents retfie ; return from interrupt

main

; remaining code goes here

END ; directive 'end of program'

PIC 16F876 poseduje mnotvo karakteristika za poveanje pouzdanosti sistema, minimizaciju cene eliminisanjem eksternih komponenata, reim niske potronje i zatitu koda.

Sleep reim rada mikrokontrolera obezbeuje vrlo nisku potronju kola (stand-by). Buenje se vri eksternim resetom, resetom na bazi WDT ili interaptom.

INSTRUKCIJE ZA PRENOS PODATAKA

MOVLW

MOVWF

MOVF

CLRF

SWAPF

Jednostavni programator PIC mikrokontrolera sa serijskog porta PC

I/O PORTOVI

DIP SOIC //

OSC1/CLKIN

9 9 I ST/CMOS clock

OSC2/CLKOUT 10 10 - , RC

MCLR/VPP 1 1 I/P ST

RA0/AN0 RA1/AN1 RA2/AN2/VREF- RA3/AN3/VREF+ RA4/TOCKI RA5/AN4

2 3 4 5 6 7

2 3 4 5 6 7

I/ I/ I/ I/ I/ I/

TTL TTL TTL TTL ST TTL

0 1 2, .. 3, clock 4

RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD

21 22 23 24 25 26 27 28

21 22 23 24 25 26 27 28

I/ I/ I/ I/ I/ I/ I/ I/

TTL/ST1 TTL TTL TTL/ST1 TTL TTL TTL/ST2 TTL/ST2

4 clock - data

RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK

RC7/RX/DT

11 12 13 14 15 16 17

18

11 12 13 14 15 16 17

18

I/ I/ I/ I/ I/ I/ I/ I/

ST ST ST ST ST ST ST

ST

Timer1 , clock Timer 1 /Capture2 /Capture1 /PWM2 Capture1 /Compare1 , PW1 SPI ili IIC komunikaciju SDI SPI / SDA IIC SDO SPI USART clock - USART -data

VSS 8, 19 8, 19 P - /

VDD 20 20 P -

: - , - , I/-/ , -, S-Schmit Trigger

PIC16F876 , , . / - I/. CPU . . , TRIS ( ), , . TRIS , .

TRIS , , 1 .

1.3.1

RA0, RA1...RA5. . RA4 TIMER0 clock RA4/T0CKI . . :

4 4

3 RA0, 1, 2, 3, 5

RA4 - , Schmit Trigger , TTL CMOS . TRIS . . TRIS DCON1 . TRISA 85h.

3. -

: x-

1.3.2.

8- . - , . TRISB : 86h 186h.

- PULL-UP , , RBPU OPTION . .

- (interrupt) . , .

- Low Voltage Programming Function : RB3/PGM , RB6/PGC , RB7/PGD.

4. -

:

-1- / Vdd Vss

-2- malog PULL-UP , (clear) RBPU (OPTION_REG-7-).

5 RB0-RB3

I/ Vdd Vss.

PULL-UP.

6 RB4-RB7

1.3.3.

8- (bidirectional) . - , , , TRISC : 87. - -. .2. Schmit Trigger . :

I/ Vdd Vss

/ select PORT DATA PERIPHERAL OUTPUT

(output enable) PERIPHERAL.

7 -

7 -

PROGRAMIRANJE DATA EEPROM E

DATA EEPROM 256 x 8 . . DATA EEPROM . DATA EEPROM EEADR EEDATA . SFR -Special Function Fegisters - : EECON1, EECON2, EEADR, EEDATA. EECON1 DATA EEPROM . EECON2 , -0-. . PIC16F876 , , 256 0h FFh.

EECON1 A

13 C1

0 RD (Read Control bit) - EEPROM- EEADR EEDATA . , EEDATA . 1- 0- 1 WR (Write Control bit) - EEPROM. EEDATA EEADR . 1- 0- 2 WREN( EEPROM Write Enable bit) - EEPROM. , EEPROM . 1- 0- 3 WRERR( EEPROM Error Flag bit) - EEPROM . 1- 0- EEPROM . 4, 5, 6 - 7 EEPGD(Program Data EEPROM Select bit) - 1- 0-

DATA EEPROM EEADR , EEPGD (EECON1) RD(EECON1). , EEDATA .

BSF STATUS, RP1 ; BCF STATUS, RP0 ;banka 2 MOVF ADDR, W ;adresa lokacije sa koje se ita MOVWF EEADR ;adresa se prebacuje u EEADR BSF STATUS, RP0 ;banka 3 bcf EECON1,EEPGD ; selektuj DATA EEPROM bsf EECON1,RD ; Citanje iz EEPROM-a BCF STATUS, RP0 ;banka 2 movf EEDATA,W

DATA EEPROM

EEPROM EEADR EEDATA . WREN EECON1 . EEPROM . WRN clear- EEPROM-. WREN . WR WREN . . WR . WR EEIF, .

55h AAh EEPROM. EECON2 EEPROM .

, - . .

BSF STATUS, RP1 ; BCF STATUS, RP0 ;banka 2 MOVF ADR, W ;adresa lokacije u koju se vri upis MOVWF EEADR ;adresa se prebacuje u EEADR MOVF PODATAK, W ;upisujemo vrednost MOVWF EEDATA ;podatak ide u EEDATA BSF STATUS, RP0 ;banka 3 BCF EECON1, EEPGD ; BSF EECON1, WREN ;omoguuje se upis BCF INTCON, GIE ;prekidi se onemoguuju MOVLW 55h ; Required MOVWF EECON2 ;prvi klju Sequence MOVLW AAh ; MOVWF EECON2 ;drugi klu BSF EECON1, WR ;inicira upis BSF INTCON, GIE ;prekidi se omoguuju

SLEEP ; BCF EECON1, WREN ;onemoguava se upis

WR .

bsf EECON1, WR btfsc EECON1, WR ; Da li je upis u EEPROM zavrsen ? goto $-1 ; Ne. Proveri ponovo bcf EECON1, WREN ; Da. Onemoguciti sluajan upis Bank0 return

- Interrupt - , . , . INTCON 0B , 8B , 10B 18B. , , . :

- EEPROM -R0 - RB4, RB5, RB6 i RB7 . - RB0/INT - -R1 R1 -R2 R2 -USART Rx -x

. . GIE . . PIC16F876 :

, . . . , . .

INT INTERRUPT

RB0/INT INTEDG OPTION (INTEDG=0). INT INTF INTCON. INTF. INTE INTCON. INT -Wake-up- SLEEP INTE .

TMR0 INTERRUPT

R0 ( FFh 00h ) T0IF INTCON . . e . 00h FFh R - . / / 0IE(INTKON).

-

PORTB RBIF (INTCON). , RB4, RB5, RB6 i RB7 . . . / / RBIE INTCON .

EEPROM

. EEPROM- 10ms ( ) , EEPROM. . EEIF, , EECON1. EEIE PIE2 .

- TMR0 -

PIC16F876 8- -. 28=256. - . OPTION . 256. 256- . . 256 . 256 T0IF INTCON . . T0IF , , . . 8- MR0 readable/writable . , MR0 . CLRWDT WDT . :

17

, RA4/T0CKI. OPTION T0CS. ( ) TOSE. MR0 .

18 MR0

TMR1

TIMER1 16- - TMR1H TMR1L . TMR1H-TMR1L 0000h FFFFh 0000h. TMR1 , TMR1 FFFFh 0000h, . () () TMR1 TMR1IE (PIE1) 1 :

- - -COUNTER

TMR1 clock-. 19 TIMER- 1. 10h.

19 TIMER1 T1CON

0 TMR1ON(TIMER1 ON Bit) TIMER1 1- TIMER1 0- TIMER1 1 TMR1CS(TIMER1 Clock Sourse Select Bit) TIMER1 CLOCK- 1- RC0,T1OSO,T1CKI( ) 0- (FOSC/4) 2 T1SYNC (TIMER1 External Clock Input Synchronization Control Bit) TMR1CS=1 1- 0- clock TMR1CS=0 ,TMR1 clock

3 T1OSCEN(TIMER1 Oscillator Enable Control Bit) 1- 0- 4,5 T1CKPS(TIMER1 Input Clock Prescale Select Bits) 11-1:8 10-1:4 01-1:2 00-1:1 6,7 , .

TIMER1 COUNTER :

20 TIMER1

TIMER1 , () . TIMER1 COUNTER , . 1:

21 -1

T1OSCEN .

-1 : Counter () TMR1CS. clock- RC1/T1OSI- T1OSCEN , RC0/T1OSO/T1CKI T1OSCEN . T1SYNC . , SLEEP- ,

. 1 : T1SYNC (T1CON) clock . TIMER1 , SLEEP- , , (WAKE-UP) -STAND-BY . 1 . CCP1 CCP2 Compare , 1 . 1 .

TIMER1:

22 TIMER1

Kako TMR1 moe imati vlastiti oscilator jedan od naina striktnog tajminga je presetovanje samo TMR1H registra u toku prekidne procedure. Konfigurisanjem preskalera na vrednost 1 i uitavanjem vrednosti 8000H u TMR1 registre prekid e se dogoditi posle tano jedne sekunde ako se izabere asovniki kvarc kristal rezonantne frekvencije 32768Hz. Prema tome, asinhroni rad TMR1 tajmera sa vlastitim kvarcnim oscilatorom daje mogunost projektantu da lako upravlja zadacima u realnom vremenu minimizirajui potronju i eksternu logiku. Tabela 1 prikazuje neke vrednosti TMR1H registra (TMR1L=0) i odgovarajue zadrke u sekundama pri frekvenciji kvarc kristala TMR1 tajmera od 32768Hz.

TMR1H (hex) Vreme brojanja do pojave interapta (s)

80 1 C0 0.5 E0 0.25 F0 0.125

PROGRAMIRANJE TMR1 TAJMERA U ASINHRONOM MODU org 0x00 ;Reset vector GOTO MAIN ; org 0x04 ;Interrupt vector ISR BCF STATUS, RP0 ; Bank0 BCF STATUS, RP1 BTFSC PIR1, TMR1IF ; Timer1 overflowed? GOTO T1_OVRFL ; YES, Service the Timer1 Overflow Interrupt ; ; Should NEVER get here ; ERROR1 ; NO, Unknown Interrupt Source BSF PORTB, 1 ; Toggle a portB pin to indicate error BCF PORTB, 1 GOTO ERROR1 ; T1_OVRFL BCF PIR1, TMR1IF ; Clear Timer1 Interrupt Flag MOVLW 0x80 ; Since doing key inputs, clear TMR1 MOVWF TMR1H ; for 1 sec overflow. : : ; Do Interrupt stuff here : RETFIE ; Return / Enable Global Interrupts ; ; MAIN ; POWER_ON Reset (Beginning of program) CLRF STATUS ; Do initialization (Bank0) BCF T1CON, TMR1ON ; Timer1 is NOT incrementing : : ; Do Initialization stuff here : MOVLW 0x80 ; TIM1H:TMR1L = 0x8000 gives 1 second MOVWF TMR1H ; overflow, at 32 KHz. CLRF TMR1L ; ; CLRF INTCON CLRF PIR1 BSF STATUS, RP0 ; Bank1 CLRF PIE1 ; Disable all peripheral interrupts ; BSF PIE1, TMR1IE ; Enable TMR1 Interrupt ; ; Initialize the Special Function Registers (SFR) interrupts ; BCF STATUS, RP0 ; Bank0 CLRF PIR1 BSF INTCON, PEIE ; Enable Peripheral Interrupts BSF INTCON, GIE ; Enable all Interrupts ; MOVLW b00001110 MOVWF T1CON ; Enable T1 Oscillator, Ext Clock, Async, prescaler = 1 BSF T1CON, TMR1ON ; Turn Timer1 ON ; Loop SLEEP GOTO Loop ; Sleep, wait for TMR1 interrupt

U S A R T (Universal Synchronous/Asynchronous Receiver Transmiter)

Serijska komunikacija je jednostavan na~in prenosa podataka izmedju mikrokontrolera i ra~unara ili mikrokontrolera i periferija kao {to su A/D konvertori, serijski EEPROM i programabilni uredjaji zasnovani na mikrora~unaru. Ve}ina PC ra~unara raspolaè sa jednim ili vie serijska porta zbog ~ega je ova forma komunikacije popularna, uklju~uju}i i ~injenicu da se prenos informacija moè vr{iti na relativno duòj distanci izmedju ra~unara i periferije. Takodje, veliki broj savremenih mernih, akvizicionih i komunikacionih uredjaja opremljen je serijskim portom. Osnovni nedostaci serijske komunikacije su relativno mala brzina prenosa kao i ~injenica da serijski port moè komunicirati samo sa jednom periferijom. Brzina prenosa podataka, medjutim, u odredjenim aplikacijama ne mora biti ograni~avaju}i faktor. Full-duplex reim prenosa podataka znai mogunost slanja i primanja podataka u isto vreme preko Tx i Rx linije, respektivno. Kada je konfigurisan USART kontrolie oba pina Rx i Tx mikrokontrolera tako da jedan od njih ne moe biti korien ka generalni I/O. Za komunikaciju sa serijskim portom PC (RS232 komunikacija) linijski RS-232 interfejs mora biti korien za prilagodjenje naponskih nivoa logi~ke jedinice i nule na strani mikrokontrolera (+5V i 0V) i ra~unara (+/-12V), respektivno. U ~ipu MAX232 je implementiran udvostru~ava~ napona i kolo naponskog invertora.

Korienje USART-a mikrokontrolera za RS232 komunikaciju

NRZ (Non Return to Zero) format serijskog prenosa podataka

Serijski prenos devetobitnog podatka (dva STOP bita)

Serijski prenos devetobitnog podatka. Bit parnosti (parna parnost) za kontrolu ispravnosti prenosa podataka (za ispravljanje greke na jednoj bitskoj poziciji)

USART moe biti konfigurisan u jednom od sledeih radnih modova:

1. Asinhroni (full-duplex) 2. Sinhroni Master (full-duplex) 3. Sinhroni Master (full-duplex)

Sinhronom master mod je zasnovan na tkzv. Half-duplex prenosu (predaja i prijem podataka nisu istovremeni). Sinhroni mod se konfigurie setovanjem bita SYNC (TXSTA). Dodatno, setovanjem bita SPEN (RCSTA) konfiguriu se RC6/TX/CK and C7/RX/DT I/O pinovi kao CK (clock) and DT (data) linije, respektivno. U master modu procesor generie master clock na CK liniji. Master mod se konfigurie setovanjem bita CSRC (TXSTA). U sinhronom slave modu takt (clock) generie periferija to doputa mikrokontroleru da prenese ili primi podatak dok je u SLEEP reimu. Slave mod se konfigurie setovanjem bita CSRC (TXSTA).

Primer izraunavanja:

4 MHz oscillator, 9600 baud Za BRGH = 1 SPBRG = 4000000/(16 x 9600) - 1 = 25.04

Za BRGH = 0 SPBRG = 4000000/(64 x 9600) - 1 = 5.51

Bolji izbor je BRGH = 1, SPBRG = 25 (manja greka)

Asinhrona transmisija podataka

Asinhroni prijem podataka

INICIJALIZACIJA USART-a

BANK1 movlw D25 movwf SPBRG ;initialize SPBRG movlw H24 movwf TXSTA ;initialize TXSTA BANK0 ;select bank 0 movlw H90 movwf RCSTA ;initialize RCSTA

SerialSetup Bank0 ;change from bank0 to bank1 bsf RCSTA,SPEN ;enable serial port bsf RCSTA,CREN ;enable reception Bank1 movlw .129 ;set baud rate 9.6k for 20Mhz clock movwf SPBRG bsf TXSTA,BRGH ;baud rate high speed option bcf TXSTA,SYNC bsf TXSTA,TXEN ;enable transmission Bank0 ;change from bank1 to bank0 return

SerialReceive Bank0 btfss PIR1,RCIF ;check if data received goto $-1 ;wait until new data movf RCREG,W ;get received data into W return

SerialTransmit Bank1 ;change from unknown bank to bank0 btfss TXSTA,TRMT ;check that shift reg. is empty goto $-1 Bank0 return

Devetobitna predaja/prijem podataka

USART moe rukovati 8-bitnom ili 9-bitnom duinom podataka. U najveem broju RS-232 aplikacija koristi se 8-bitni prenos. Postoji nekoliko razloga zbog ega se u nekim sluajevima koristi 9-bitni prenos:

Raspoloivi podatak je duzine 9 bitova Podatak je 8-bitni a zahtevaju se dva stop bita Podatak je 8-bitni a zahteva se bit pariteta Podatak je 8-bitni a zahteva se 9-ti bit za detekciju adrese

TX9 bit u TXSTA registru i RX9 bit u RCSTA registru moraju biti setovati da bi se omoguila devetobitna transmisija i prijem. Redosled itanja i upisa podataka je veoma vaan kada se radi sa devetobitnim operacijama. 9-ti bit uvek treba upisivati ili itati pre preostalih 8 bitova.

Programska sekvenca za omoguenje interapta prilikom prijema i transfera podatka

movlw 0xc0 ;enable global and peripheral interrupts movwf INTCON movlw 0x30 ;enable TX and RX interrupts Bank1 movwf PIE1

Vreme akvizicije

ADSetup Bank1 bcf PIE1, ADIE movlw B'10000000' movwf ADCON1 Bank0 movlw B'10000001' movwf ADCON0 return ;----------------------------------------------------------- DelayACQ movlw .25 ; (1uS) movwf TEMP ; (1uS) decfsz TEMP, F ; Delay loop (1uS - 2uS) goto $-1 ; (2uS) return ; (2uS) ;------------------------------------------------------------

IIC SERIJSKI EEPROM

32K x 8 bits

Generisanje START i STOP uslova

Adresiranje memorije

; Fosc=4MHz

;******************* Generisanje START uslova *******************

START Bank1

BSF TRISC, SDA ; SDA input (pull up -->1) BCF STATUS, RP0 ; Bank0

btfss PORTC, SDA

goto $-1

BSF PORTC, SCL ; SCL high

NOP ; 5us pre SDA low

BCF PORTC, SDA ; SDA low

BSF STATUS, RP0 ; Bank1

BCF TRISC, SDA ; SDA output

BCF STATUS, RP0 ; Bank0

NOP ; 4us pre SCL low

NOP

BCF PORTC, SCL ; startovanje clock-a RETURN

;******************* Generisanje STOP uslova *******************

STOP BCF STATUS, RP0 ; Bank0

BCF PORTC, SDA ; SDA low





NOP ; 4us pre SDA high


BSF TRISC, SDA ; SDA input (pull up-->1) BCF STATUS, RP0 ; Bank0

btfss PORTC, SDA

goto $-1

NOP

BCF PORTC, SCL ; SCL low

RETURN

;********* Rutina za transmisiju bajta smestenog u TRREG ka EEPROM-u *********

TXI2C MOVLW .8

MOVWF Count ; Count=8

TXLP RLF TRREG,F ; MSB bit iz TRREG u CARRY

CALL BITOUT ; Posalji bit DECFSZ Count,F ; Preneto 8 bitova ?

GOTO TXLP ; Ne

CALL BITIN ; Da. Citanje ACK-a BTFSC STATUS, C ; Provera ACK-a

BSF ERRFLAG, 0 ; EEPROM nije primio bajt.Postavi flag RETURN

;******* Podprogram za slanje jednog bita smestenog u CARRY ka EEPROM-u *******

BITOUT BTFSS STATUS, C ; Da li je 0 ili 1 ? GOTO BIT0

BIT1 BSF STATUS, RP0 ; Bank1

BSF TRISC, SDA ; SDA input (pull up -->1) BCF STATUS, RP0 ; Bank0

GOTO CLK1

;

BIT0 BCF STATUS, RP0 ; Bank0

BCF PORTC, SDA ; SDA low=0




NOP

;

CLK1 BSF PORTC, SCL ; SCL high

NOP

NOP

NOP

NOP

NOP

NOP ; SCL=1 u trajanju od 5us BCF PORTC, SCL ; SCL low

RETURN

;*********** Rutina za prijem bajta iz EEPROM-a i smestanje u REREG ***********

RXI2C MOVLW .8

MOVWF Count ; Count=8

CLRF REREG ; REREG=b'00000000'

RXLP CALL BITIN ; Prima jedan bit iz EEPROM-a, smesta ga u CARRY i RLF REREG, F ; ubacuje u REREG DECFSZ Count,F ; 8-mi bit ?

GOTO RXLP ; Ne. Primi sledeci bit

RETURN ; Primljeno svih 8 bitova

;***** Podprogram za prijem jednog bita iz EEPROM-a i njegovo smestanje u CARRY *****

BITIN BSF STATUS, RP0 ; Bank1

BSF TRISC, SDA ; SDA input



NOP

BCF STATUS, C ; CARRY=0

BTFSC PORTC, SDA ; Da li EEPROM salje 0 ili 1 ? BSF STATUS, C

NOP

NOP

BCF PORTC, SCL ; SCL low

RETURN

mikroprocesori-predavanje

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