migration and device emulation within the mpc560xb/c/d family
TRANSCRIPT
Freescale SemiconductorApplication Note
Document Number: AN4340Rev. 0, 08/2011
Contents
MPC5607B and MPC5604B comparison overview . . . . . 2List of differences between MPC5607B and MPC5604B 3
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.2 ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.3 eMIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.4 LinFlex. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Packages and pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Migrating from MPC5604B to MPC5607B. . . . . . . . . . . 23
5.1 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.2 ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245.3 LinFlex. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245.4 eMIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Migrating from MPC5607B to MPC5604B. . . . . . . . . . . 24
6.1 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256.2 Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256.4 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256.5 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256.6 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256.7 PIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256.8 eMIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266.9 ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266.10 CTU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266.11 LINFlex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266.12 DSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Migration and Device Emulation within the MPC560xB/C/D Family
The 32-bit MPC560xB/C/D automotive microcontrollers are a family of System-on-Chip (SoC) devices designed to be central to the development of the next generation of central vehicle body controller, smart junction box, front module, peripheral body, door control, and seat control applications.
Jointly developed by Freescale Semiconductor and STMicroelectronics™, the MPC560xB/C/D car body family is a series of automotive microcontrollers based on the Power Architecture™ Book E, and are designed specifically for embedded automotive applications.
The MPC560xB/C/D family is a highly scalable and compatible family of devices. However, designing an application that can be easily ported across different members of this family requires knowledge of their specific features and of any significant differences between them.
This document focuses specifically on migrating applications between two sets of products among the family:
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© Freescale Semiconductor, Inc., 2011. All rights reserved.
MPC5607B and MPC5604B comparison overview
• MPC5604B: For sales type MPC5604B/C, MPC5603B/C, and MPC5062B/C
• MPC5607B: For sales type MPC5607B, MPC5606B, and MPC5605B
The set namings refer to the most featured sale type in each set.
The following use cases will be addressed:
• Migrating from MPC5604B to MPC5607B
• Migrating from MPC5607B to the MPC5604B
1 MPC5607B and MPC5604B comparison overviewFeatures of the MPC5604B are, in general, a subset of ones available on the MPC5607B.
However, in some cases additional features have been added or enhancements have been made. Thus when designing an application that may be ported between the MPC5607B and the MPC5604B, it is imperative to understand clearly the differences between them.
The diagrams in Figure 1 highlight at a high level the key differences between these devices.
Migration and Device Emulation within the MPC560xB/C/D Family, Rev. 0
Freescale Semiconductor2
List of differences between MPC5607B and MPC5604B
Figure 1. MPC5607B and MPC5604B comparison overview
2 List of differences between MPC5607B and MPC5604B
2.1 IntroductionFor an overview of general differences between member of the MPC560xB/C/D Car Body device family, please refer to “MPC560xB/C/D family — Product Differences”.
512K
SYSTEM6 PIT
SIUINTCBAM
WatchdogVReg
FMPLLSTM & RTC
CROSSBAR
JTAG
I/O 512 KBBridge Code
Flash
64 KBDataFlash
48 KBSRAM
1.5M
SYSTEM PITSIUINTCBAM
WatchdogVReg
FMPLLSTM & RTC
CROSSBAR
e200z0 JTAGeDMA
I/O 1.5 MBBridge Code
Flash
64 KBDataFlash
96 KBSRAM
6
Fle
xCan
LinF
lex
with
Dm
a
LinF
lex
S
PI
eMIO
S
CT
U
12-b
it A
DC
DMA Mux
Key:Common to both devicesOnly available on highlighted deviceDifferences in module implementation
Nexus 2+
MPU
32 kHz Osc
LinF
lex
with
Dm
a
LinF
lex
LinF
lex
LinF
lex
LinF
lex
LinF
lex
LinF
lex
LinF
lex
IIC
10-b
it A
DC
eMIO
S
CA
N S
ampl
er
6
Fle
xCan
3 x
SP
I
CT
U
10-b
it A
DC
eMIO
S
8
6
Nexus 2+
32 kHz Osc
MPU
LinF
lex
LinF
lex
LinF
lex
LinF
lex
IIC
eMIO
S
CA
N S
ampl
er
Core
e200z0Core
Migration and Device Emulation within the MPC560xB/C/D Family, Rev. 0
Freescale Semiconductor 3
List of differences between MPC5607B and MPC5604B
The sections hereafter describe in more detail the specific differences between MPC5607B and MPC5604B that the user must be aware of when porting applications between these devices.
2.2 ADCMPC5607B implementation of ADC is the following:
• One 12-bit ADC with:
— Sixteen high-precision “ADC1_P” channels; pins shared with ADC 10-bit
— Eight normal “ADC1_S” channels; three pins shared with ADC 10-bit
— PIT6 injection trigger
— Three analog thresholds
• One 10-bit ADC with:
— Sixteen high precision “ADC0_P” channels; pins shared with ADC 12-bit
— Twenty-eight normal “ADC0_S” channels; three pins shared with ADC 12-bit
— Four normal “ADC0_X”channels that can be entries for external multiplexing for up to thirty-two external channels
— PIT2 injection trigger
— Six analog thresholds
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List of differences between MPC5607B and MPC5604B
Figure 2. ADC implementation of MPC5607B
MPC5604B implementation of ADC is the following:
• One 10-bit ADC with:
— Sixteen high precision “ADC0_P”channels
— Sixteen normal “ADC0_S” channels
— Four normal “ADC0_X” channels can be entries for external multiplexing for up to thirty-two external channels
— PIT2 injection trigger
— Four analog thresholds
Up to 32 channelsmedium accuracy
16 channelshigh accuracy (same pins as ADC 12b)
Up to 32 extended channelsthrough external MUX
ADC0_X[3]
ADC0_X[0]
ADC0_S[27]
ADC0_S[0]
ADC0_P[15]
ADC0_P[0]
eMIOS_0_0 toeMIOS_0_22
eMIOS_0_24 toeMIOS_0_31
PIT7
ADC control
ADC trigger
ADC done
MA[2:0]
CTU
MUX 8 MUX 8
3
DigitalInterface Analog
switch
eMIOS
PIT
INTC
D
A
MU
X 3
2M
UX
16
ADC 10-bit system
Ch0 toCh22 trig
Ch24 toCh31 trig
. . .
...
...
...
PIT3
16 channelshigh accuracy (same pins as ADC 10b)
ADC1_P[15]
ADC1_P[0]
DigitalInterface Analog
switch
INTC
D
A MU
X 1
6ADC 12-bit system
...
eMIOS_1_0 toeMIOS_1_22
eMIOS_1_24 toeMIOS_1_31
Ch32 toCh54 trig
Ch56 toCh63 trig
Ch23 trig
Ch55 trig
PIT6
PIT2
ADC control
ADC trigger
ADC done
Injectiontrigger
Injectiontrigger
ADC1_S[7]
ADC1_S[0]
...
MU
X 8 Up to 8 channels
medium accuracy (3 pins shared with ADC 10b)
(3 pins shared with ADC 12b)
Migration and Device Emulation within the MPC560xB/C/D Family, Rev. 0
Freescale Semiconductor 5
List of differences between MPC5607B and MPC5604B
Figure 3. ADC implementation of MPC5604B
The results of a conversion are stored in the appropriate result register. Software should account for the effective 2-bit offset of the MSB of the result between 10-bit ADC results and 12-bit ADC results.
In addition, analog threshold handling is different between MPC5607B and MPC5604B:
• MPC5604B uses four possible analog threshold ranges. Each single range can be allocated to one single channel.
• MPC5607B uses six possible analog threshold ranges (on its 10-bit ADC). A single range can be shared between several ADC channels. The 12-bit ADC follows the same rules with three analog thresholds.
The respective sets of registers to handle analog thresholds are different. This is therefore important from a migration perspective (see later in this document).
2.3 eMIOSThe eMIOS modules can have channel types shown in Table 1.
Up to 20 channelsmedium accuracy
16 channelshigh accuracy
Up to 32 extended channelsthrough external MUX
ADC0_X[3]
ADC0_X[0]
ADC0_S[27]
ADC0_S[0]
ADC0_P[15]
ADC0_P[0]
eMIOS_0_0 to
eMIOS_0_23
eMIOS_1_0 to
eMIOS_1_23
ADC control
ADC trigger
ADC done
MA[2:0]
CTU
MUX 8 MUX 8
3
DigitalInterface Analog
switch
eMIOS
PIT
INTC
D
A
MU
X 2
0M
UX
16
ADC 10-bit system
Ch0 to
Ch23 trig
Ch29 to
Ch52 trig
. . .
...
...
...
PIT3 Ch28 trig
PIT2Injectiontrigger
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List of differences between MPC5607B and MPC5604B
MPC5607B contains two eMIOS modules (eMIOS_0 and eMIOS_1) organized as shown in Figure 4.
Table 1. eMIOS channel types
Description NameChannel type
Type X Type Y Type F Type G Type H
General purpose input/output GPIO x x x x x
Single action input capture SAIC x x x x x
Single action output compare SAOC x x x x x
Modulus counter MC x — — — —
Modulus counter buffered (up/down) MCB x — — x —
Input pulse width measurement IPWM — — — x x
Input period measurement IPM — — — x x
Double action output compare DAOC — — — x x
Output pulse width and frequency modulation buffered
OPWFMB x — — x —
Center-aligned output PWM buffered with dead time
OPWMCB — — — x —
Output pulse width modulation buffered OPWMB x x — x x
Output pulse width modulation trigger OPWMT x x — x x
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List of differences between MPC5607B and MPC5604B
Figure 4. eMIOS Implementation of MPC5607B
MPC5604B contains two eMIOS modules (eMIOS_0 and eMIOS_1) organized as shown in Figure 5.
Ch1
Ch0
Ch2Ch3Ch4Ch5Ch6Ch7
Ch9Ch8
Ch10Ch11Ch12Ch13Ch14Ch15
Ch17
Ch16
Ch18Ch19Ch20Ch21Ch22Ch23
Ch25Ch24
Ch26Ch27
eMIOS_0
Co
un
ter_bus_B
Co
un
ter_bus_C
Co
un
ter_bus_E
Co
un
ter_
bus_
A
GlobalPrescaler
Clock
BusInterface
IP Bus
Chan Type_X Chan Type_Y
Co
un
ter_bus_D
Chan Type_G Chan Type_H
Ch28Ch29Ch30Ch31
Ch1
Ch0
Ch2Ch3Ch4Ch5Ch6Ch7
Ch9
Ch8
Ch10Ch11Ch12Ch13Ch14Ch15
Ch17
Ch16
Ch18Ch19Ch20Ch21Ch22Ch23
Ch25Ch24
Ch26Ch27
Co
un
ter_bus_B
Co
un
ter_bus_C
Co
un
ter_bus_E
Co
un
ter_
bus_
A
GlobalPrescaler
Clock
BusInterface
IP BusC
ou
nter_bu
s_D
Ch28Ch29Ch30Ch31
eMIOS_1
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Packages and pinout
Figure 5. eMIOS implementation of MPC5604B
2.4 LinFlexMPC5607B contains ten LinFlex modules. Two of them are enabled to issue DMA requests:
• LinFlex 0 and 1 can issue DMA requests
• LinFlex 2 to 9 are not DMA enabled
MPC5604B contains four LinFlex modules. None of them are enabled to issue DMA requests.
3 Packages and pinoutThe differences between the analog and digital functionality multiplexed on the pins of the MPC5607B and MPC5604B devices are summarized in the next tables. Only the 100LQFP and 144LQFP packages have been described since these are the only packages common to both of these devices.
Ch1
Ch0
Ch2Ch3Ch4Ch5Ch6Ch7
Ch9Ch8
Ch10Ch11Ch12Ch13Ch14Ch15
Ch17
Ch16
Ch18Ch19Ch20Ch21Ch22Ch23
Ch25Ch24
Ch26Ch27
eMIOS_0
Co
un
ter_bus_B
Co
un
ter_bus_C
Co
un
ter_bus_E
Co
un
ter_
bus_
A
GlobalPrescaler
Clock
BusInterface
IP Bus
Chan Type_X Chan Type_Y Chan Type_F
Co
un
ter_bus_D
Ch1
Ch0
Ch2Ch3Ch4Ch5Ch6Ch7
Ch9
Ch8
Ch10Ch11Ch12Ch13Ch14Ch15
Ch17
Ch16
Ch18Ch19Ch20Ch21Ch22Ch23
Ch25Ch24
Ch26Ch27
Co
un
ter_bus_B
Co
un
ter_bus_C
Co
un
ter_bus_E
Co
un
ter_
bus_
A
GlobalPrescaler
Clock
BusInterface
IP Bus
Co
un
ter_bus_D
eMIOS_1
Chan Type_G Chan Type_H
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Packages and pinout
Key
Function unique to MPC5604B
Function unique to MPC5607B
Function Common to MPC5604B and MPC5607B
Table 2. 100LQFP MPC5604B to MPC5607B comparison
Pin Pad Alternate input functionsAlternate I/O functions
ALT0 ALT1 ALT2 ALT3
1 PB[3] WKPU[11] LIN0RX GPIO[19] E0UC[31] SCL
2 PC[9] WKPU[13] LIN2RX GPIO[41] E0UC[7]
3 PC[14] EIRQ[8] GPIO[46] E0UC[14] SCK_2
4 PC[15] EIRQ[20] GPIO[47] E0UC[15] CS0_2
5 PA[2] WKPU[3] GPIO[2] E0UC[2] MA[2]
6 PE[0] WKPU[6] CAN5RX GPIO[64] E0UC[16] CAN_samp1_RX
7 PA[1] WKPU[2] GPIO[1] E0UC[1] NMI[0]
8 PE[1] GPIO[65] E0UC[17] CAN5TX
9 PE[8] GPIO[72] CAN2TX E0UC[22] CAN3TX
10 PE[9] WKPU[7] CAN2RX CAN3RX GPIO[73] CAN_samp2_RX
E0UC[23] CAN_samp3_RX
11 PE[10] EIRQ[10] GPIO[74] LIN3TX CS3_1 E1UC[30]
12 PA[0] WKPU[19] GPIO[0] E0UC[0] CLKOUT E0UC[13]
13 PE[11] WKPU[14] LIN3RX GPIO[75] E0UC[24] CS4_1
14 Vpp
15 VDD_HV
16 VSS_HV
17 RESET
18 VSS_LV
19 VDD_LV
20 VDD_BV
21 PC[11] WKPU[5] CAN1RX CAN4RX GPIO[43] CAN_samp1_RX
CAN_samp4_RX
MA[2]
22 PC[10] GPIO[42] CAN1TX CAN4TX MA[1]
23 PB[0] GPIO[16] CAN0TX E0UC[30] LIN0TX
24 PB[1] WKPU[4] CAN0RX LIN0RX GPIO[17] CAN_samp0_RX
E0UC[31]
25 PC[6] GPIO[38] LIN1TX E1UC[28]
26 PC[7] WKPU[12] LIN1RX GPIO[39] E1UC[29]
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Packages and pinout
27 PA[15] WKPU[10] GPIO[15] CS0_0 SCK_0 E0UC[1]
28 PA[14] EIRQ[4] GPIO[14] SCK_0 CS0_0 E0UC[0]
29 PA[4] WKPU[9] LIN5RX GPIO[4] E0UC[4] CS0_1
30 PA[13] GPIO[13] SOUT_0 E0UC[29]
31 PA[12] EIRQ[17] SIN_0 GPIO[12] E0UC[28] CS3_1
32 VDD_LV
33 VSS_LV
34 XTAL
35 VSS_HV
36 EXTAL
37 VDD_HV
38 PB[9] WKPU[26] ADC1_S[5] ADC0_S[1] GPIO[25]
39 PB[8] WKPU[25] ADC1_S[4] ADC0_S[0] GPIO[24]
40 PB[10] WKPU[8] ADC1_S[6] ADC0_S[2] GPIO[26]
41 PD[0] WKPU[27] ADC1_P[4] ADC0_P[4] GPIO[48]
42 PD[1] WKPU[28] ADC1_P[5] ADC0_P[5] GPIO[49]
43 PD[2] ADC1_P[6] ADC0_P[6] GPIO[50]
44 PD[3] ADC1_P[7] ADC0_P[7] GPIO[51]
45 PD[4] ADC1_P[8] ADC0_P[8] GPIO[52]
46 PD[5] ADC1_P[9] ADC0_P[9] GPIO[53]
47 PD[6] ADC1_P[10] ADC0_P[10] GPIO[54]
48 PD[7] ADC1_P[11] ADC0_P[11] GPIO[55]
49 PD[8] ADC1_P[12] ADC0_P[12] GPIO[56]
50 PB[4] ADC1_P[0] ADC0_P[0] GPIO[20]
51 VSS_HV_ADC0
52 VDD_HV_ADC0
53 PB[5] ADC1_P[1] ADC0_P[1] GPIO[21]
54 PB[6] ADC1_P[2] ADC0_P[2] GPIO[22]
55 PB[7] ADC1_P[3] ADC0_P[3] GPIO[23]
56 PD[9] ADC1_P[13] ADC0_P[13] GPIO[57]
57 PD[10] ADC1_P[14] ADC0_P[14] GPIO[58]
58 PD[11] ADC1_P[15] ADC0_P[15] GPIO[59]
*59 PB[11] Vss_HV_ADC1 ADC0_S[3] GPIO[27] E0UC[3] CS0_0
Table 2. 100LQFP MPC5604B to MPC5607B comparison (continued)
Pin Pad Alternate input functionsAlternate I/O functions
ALT0 ALT1 ALT2 ALT3
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Packages and pinout
*60 PD[12] Vdd_HV_ADC1 ADC0_S[4] GPIO[60] CS5_0 E0UC[24]
61 PB[12] ADC0_X[0] GPIO[28] E0UC[4] CS1_0
62 PD[13] ADC0_S[5] GPIO[61] CS0_1 E0UC[25]
63 PB[13] ADC0_X[1] GPIO[29] E0UC[5] CS2_0
64 PD[14] ADC0_S[6] GPIO[62] CS1_1 E0UC[26]
65 PB[14] ADC0_X[2] GPIO[30] E0UC[6] CS3_0
66 PD[15] ADC0_S[7] GPIO[63] CS2_1 E0UC[27]
67 PB[15] ADC0_X[3] GPIO[31] E0UC[7] CS4_0
68 PA[3] EIRQ[0] ADC1_S[0] GPIO[3] E0UC[3] LIN5TX CS4_1
69 VSS_HV
70 VDD_HV
71 PA[7] EIRQ[2] ADC1_S[1] GPIO[7] E0UC[7] LIN3TX
72 PA[8] EIRQ[3] ABS[0] LIN3RX GPIO[8] E0UC[8] E0UC[14]
73 PA[9] FAB GPIO[9] E0UC[9] CS2_1
74 PA[10] ADC1_S[2] GPIO[10] E0UC[10] SDA LIN2TX
75 PA[11] EIRQ[16] ADC1_S[3] LIN2RX GPIO[11] E0UC[11] SCL
76 PE[12] EIRQ[11] ADC1_S[7] SIN_2 GPIO[76] E1UC[19]
77 PC[3] EIRQ[6] CAN4RX CAN1RX GPIO[35] CS0_1 MA[0]
78 PC[2] EIRQ[5] GPIO[34] SCK_1 CAN4TX
79 PA[5] GPIO[5] E0UC[5] LIN4TX
80 PA[6] EIRQ[1] LIN4RX GPIO[6] E0UC[6] CS1_1
81 PH[10] GPIO[122] TMS
82 PC[1] GPIO[33] TDO
83 VSS_HV
84 VDD_HV
85 VDD_LV
86 VSS_LV
87 PC[0] GPIO[32] TDI
88 PH[9] GPIO[121] TCK
89 PE[2] EIRQ[21] SIN_1 GPIO[66] E0UC[18]
90 PE[3] GPIO[67] E0UC[19] SOUT_1
91 PC[5] EIRQ[7] GPIO[37] SOUT_1 CAN3TX
92 PC[4] EIRQ[18] SIN_1 CAN3RX GPIO[36] E1UC[31]
Table 2. 100LQFP MPC5604B to MPC5607B comparison (continued)
Pin Pad Alternate input functionsAlternate I/O functions
ALT0 ALT1 ALT2 ALT3
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Packages and pinout
NOTEPins 59 and 60 are implemented as ADC_1 power supplies pins VSS and VDD respectively on the MPC5607B in the 100LQFP package. Refer to section 5.1 and 6.1 for further details.
93 PE[4] EIRQ[9] GPIO[68] E0UC[20] SCK_1
94 PE[5] GPIO[69] E0UC[21] CS0_1 MA[2]
95 PE[6] EIRQ[22] GPIO[70] E0UC[22] CS3_0 MA[1]
96 PE[7] EIRQ[23] GPIO[71] E0UC[23] CS2_0 MA[0]
97 PC[12] EIRQ[19] SIN_2 GPIO[44] E0UC[12]
98 PC[13] GPIO[45] E0UC[13] SOUT_2
99 PC[8] GPIO[40] LIN2TX E0UC[3]
100 PB[2] GPIO[18] LIN0TX SDA E0UC[30]
Table 2. 100LQFP MPC5604B to MPC5607B comparison (continued)
Pin Pad Alternate input functionsAlternate I/O functions
ALT0 ALT1 ALT2 ALT3
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Packages and pinout
Here is a package-oriented view:
Figure 6. MPC5607B LQFP100 package
12345678910111213141516171819202122232425
75747372717069686766656463626160595857565554535251
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
LIN0RX / WKPU[11] / SCL / E0UC[31] / GPIO[19] / PB[3]LIN2RX / WKPU[13] / E0UC[7] / GPIO[41] / PC[9]EIRQ[8] / SCK_2 / E0UC[14] / GPIO[46] / PC[14]
EIRQ[20] / CS0_2 / E0UC[15] / GPIO[47] / PC[15]MA[2] / WKPU[3] / E0UC[2] / GPIO[2] / PA[2]
CAN5RX/ WKPU[6] / E0UC[16] / GPIO[64] / PE[0]WKPU[2] / NMI[0] / E0UC[1] / GPIO[1] / PA[1]
CAN5TX / E0UC[17] / GPIO[65] / PE[1]CAN3TX / E0UC[22] / CAN2TX / GPIO[72] / PE[8]
CAN3RX / CAN2RX / WKPU[7] / E0UC[23] / / GPIO[73] / PE[9]EIRQ[10] / E1UC[30] / CS3_1 / LIN3TX / GPIO[74] / PE[10]
WKPU[19] / E0UC[13] / CLKOUT / E0UC[0] / GPIO[0] / PA[0]LIN3RX / WKPU[14] / CS4_1 / E0UC[24] / GPIO[75] / PE[11]
VSS_HVVDD_HVVSS_HV
RESETVSS_LVVDD_LVVDD_BV
CAN4RX / CAN1RX / WKPU[5] / MA[2] / GPIO[43] / PC[11]MA[1] / CAN4TX / CAN1TX / GPIO[42] / PC[10]
LIN0TX / E0UC[30] / CAN0TX / GPIO[16] / PB[0]CAN0RX / WKPU[4] / LIN0RX / E0UC[31] / GPIO[17] / PB[1]
E1UC[28] / LIN1TX / GPIO[38] / PC[6]]
PA[11] / GPIO[11] / E0UC[11] / SCL / EIRQ[16] / LIN2RX / ADC1_S[3]PA[10] / GPIO[10] / E0UC[10] / SDA / LIN2TX / ADC1_S[2]PA[9] / GPIO[9] / E0UC[9] / CS2_1 / FABPA[8] / GPIO[8] / E0UC[8] / E0UC[14] / EIRQ[3] / ABS[0] / LIN3RXPA[7] / GPIO[7] / E0UC[7] / LIN3TX / EIRQ[2] / ADC1_S[1]VDD_HVVSS_HVPA[3] / GPIO[3] / E0UC[3] / LIN5TX / CS4_1 / EIRQ[0] / ADC1_S[0]PB[15] / GPIO[31] / E0UC[7] / CS4_0 / ADC0_X[3]PD[15] / GPIO[63] / CS2_1 / E0UC[27] / ADC0_S[7]PB[14] / GPIO[30] / E0UC[6] / CS3_ 0 / ADC0_X[2]PD[14] / GPIO[62] / CS1_1 / E0UC[26] / ADC0_S[6]PB[13] / GPIO[29] / E0UC[5] / CS2_0 / ADC0_X[1]PD[13] / GPIO[61] / CS0_1 / E0UC[25] / ADC0_S[5]PB[12] / GPIO[28] / E0UC[4] / CS1_0 / ADC0_X[0]VDD_HV_ADC1VSS_HV_ADC1PD[11] / GPIO[59] / ADC0_P[15] / ADC1_P[15]PD[10] / GPIO[58] / ADC0_P[14] / ADC1_P[14]PD[9] / GPIO[57] / ADC0_P[13] / ADC1_P[13]PB[7] / GPIO[23] / ADC0_P[3] / ADC1_P[3]PB[6] / GPIO[22] / ADC0_P[2] / ADC1_P[2]PB[5] / GPIO[21] / ADC0_P[1] / ADC1_P[1]VDD_HV_ADC0VSS_HV_ADC0
LIN
1RX
/ W
KP
U[1
2] /
E1U
C[2
9] /
GP
IO[3
9] /
PC
[7]
WK
PU
[10]
/ E
0UC
[1]
/ SC
K_0
/ C
S0_
0 / G
PIO
[15]
/ PA
[15]
EIR
Q[4
] / E
0UC
[0]
/ CS
0_0
/ SC
K_0
/ G
PIO
[14]
/ PA
[14]
LIN
5RX
/ W
KP
U[9
] / C
S0_
1 / E
0UC
[4] /
GP
IO[4
] / P
A[4
]E
0UC
[29]
/ S
OU
T_0
/ G
PIO
[13]
/ PA
[13]
EIR
Q[1
7] /
SIN
_0 /
CS
3_1
/ E0U
C[2
8] /
GP
IO[1
2] /
PA[1
2]V
DD
_LV
VS
S_L
VX
TAL
VS
S_H
VE
XTA
LV
DD
_HV
WK
PU
[26]
/AD
C1_
S[5
] / 3
2KX
TA /
AD
C0_
S[1
] / G
PIO
[25]
/ P
B[9
]W
KP
U[2
5]/A
DC
1_S
[4]
/ 32K
XTA
/ A
DC
0_S
[0] /
GP
IO[2
4] /
PB
[8]
AD
C1_
S[6
] / W
KP
U[8
] / A
DC
0_S
[2] /
GP
IO[2
6] /
PB
[10]
WK
PU
[27]
/ A
DC
1_P
[4]
/ AD
C0_
P[4
] / G
PIO
[48]
/ P
D[0
]W
KP
U[2
8] /
AD
C1_
P[5
] / A
DC
0_P
[5] /
GP
IO[4
9] /
PD
[1]
AD
C1_
P[6
] / A
DC
0_P
[6] /
GP
IO[5
0] /
PD
[2]
AD
C1_
P[7
] / A
DC
0_P
[7] /
GP
IO[5
1] /
PD
[3]
AD
C1_
P[8
] / A
DC
0_P
[8] /
GP
IO[5
2] /
PD
[4]
AD
C1_
P[9
] / A
DC
0_P
[9] /
GP
IO[5
3] /
PD
[5]
AD
C1_
P[1
0] /
AD
C0_
P[1
0] /
GP
IO[5
4] /
PD
[6]
AD
C1_
P[1
1] /
AD
C0_
P[1
1] /
GP
IO[5
5] /
PD
[7]
AD
C1_
P[1
2] /
AD
C0_
P[1
2] /
GP
IO[5
6] /
PD
[8]
AD
C1_
P[0
] / A
DC
0_P
[0] /
GP
IO[2
0] /
PB
[4]
PB
[2] /
GP
IO[1
8] /
LIN
0TX
/ S
DA
/ E
0UC
[30]
PC
[8] /
GP
IO[4
0] /
LIN
2TX
/ E0U
C[3
]P
C[1
3] /
GP
IO[4
5] /
E0U
C[1
3] /
SO
UT
_2P
C[1
2] /
GP
IO[4
4] /
E0U
C[1
2] /
EIR
Q[1
9] /
SIN
_2P
E[7
] / G
PIO
[71]
/ E
0UC
[23]
/ C
S2_
0 / M
A[0
] / E
IRQ
[23]
PE
[6] /
GP
IO[7
0] /
E0U
C[2
2] /
CS
3_0
/ MA
[1] /
EIR
Q[2
2]P
E[5
] / G
PIO
[69]
/ E
0UC
[21]
/ C
S0_
1 / M
A[2
]P
E[4
] / G
PIO
[68]
/ E
0UC
[20]
/ S
CK
_1 /
EIR
Q[9
]P
C[4
] / G
PIO
[36]
/ E
1UC
[31]
/ E
IRQ
[18]
/ S
IN_1
/ C
AN
3RX
PC
[5] /
GP
IO[3
7] /
SO
UT
_1 /
CA
N3T
X /
EIR
Q[7
]P
E[3
] / G
PIO
[67]
/ E
0UC
[19]
/ S
OU
T_1
PE
[2] /
GP
IO[6
6] /
E0U
C[1
8] /
EIR
Q[2
1] /
SIN
_1P
H[9
] / G
PIO
[121
] / T
CK
PC
[0] /
GP
IO[3
2] /
TD
IV
SS
_LV
VD
D_L
VV
DD
_HV
VS
S_H
VP
C[1
] / G
PIO
[33]
/ T
DO
PH
[10]
/ G
PIO
[122
] / T
MS
PA[6
] / G
PIO
[6] /
E0U
C[6
] / C
S1_
1 / E
IRQ
[1] /
LIN
4RX
PA[5
] / G
PIO
[5] /
E0U
C[5
] / L
IN4T
XP
C[2
] / G
PIO
[34]
/ S
CK
_1 /
CA
N4T
X /
EIR
Q[5
]P
C[3
] / G
PIO
[35]
/ C
S0_
1 / M
A[0
] / E
IRQ
[6] /
CA
N4R
X /
CA
N1R
XP
E[1
2] /
GP
IO[7
6] /
E1U
C[1
9] /
EIR
Q[1
1] /
SIN
_2 /
AD
C1_
S[7
]
LQFP100
Migration and Device Emulation within the MPC560xB/C/D Family, Rev. 0
Freescale Semiconductor14
Packages and pinout
Figure 7. MPC5604B LQFP100 package
12345678910111213141516171819202122232425
75747372717069686766656463626160595857565554535251
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
WKPU[11] / SCL / LIN0RX / GPIO[19] / PB[3]WKPU[13] / LIN2RX / GPIO[41] / PC[9]
EIRQ[8] / SCK2 / E0UC[14] / GPIO[46] / PC[14]CS0_2 / E0UC[15] / GPIO[47] / PC[15]
WKPU[3] / E0UC[2] / GPIO[2] / PA[2]WKPU[6] / CAN5RX / E0UC[16] / GPIO[64] / PE[0]
WKPU[2] / NMI / E0UC[1] / GPIO[1] / PA[1]CAN5TX / E0UC[17] / GPIO[65] / PE[1]
CAN3TX / E0UC[22] /CAN2TX / GPIO[72] / PE[8]WKPU[7] / CAN3RX / E0UC[23] /CAN2RX / GPIO[73] / PE[9]
EIRQ[10] / CS3_1 / LIN3TX / GPIO[74] / PE[10]WKPU[19] / CLKOUT / E0UC[0] / GPIO[0] / PA[0]WKPU[14] / CS4_1 / LIN3RX / GPIO[75] / PE[11]
VSS_HVVDD_HVVSS_HV
RESETVSS_LVVDD_LVVDD_BV
WKPU[5] / CAN4RX / CAN1RX / GPIO[43] / PC[11]MA[1] / CAN4TX / CAN1TX / GPIO[42] / PC[10]
CAN0TX / GPIO[16] / PB[0]WKPU[4] / CAN0RX / GPIO[17] / PB[1]
LIN1TX / GPIO[38] / PC[6]
PA[11] / GPIO[11] / E0UC[11] / SCLPA[10] / GPIO[10] / E0UC[10] / SDAPA[9] / GPIO[9] / E0UC[9] / FABPA[8] / GPIO[8] / E0UC[8] / LIN3RX / EIRQ[3] / ABS[0]PA[7] / GPIO[7] / E0UC[7] / LIN3TX / EIRQ [2]VDD_HVVSS_HVPA[3] / GPIO[3] / E0UC[3] / EIRQ[0]PB[15] / GPIO[31] / CS4_0 / E0UC[7] / ADC0_X[3]PD[15] / GPIO[63] / CS2_1 / ADC0_S[7] / E0UC[27]PB[14] / GPIO[30] / CS3_ 0 / E0UC[6] / ADC0_X[2]PD[14] / GPIO[62] / CS1_1 / ADC0_S[6] / E0UC[26]PB[13] / GPIO[29] / CS2_0 / E0UC[5] / ANX[1]PD[13] / GPIO[61] / CS0_1 / ADC0_S[5] / E0UC[25]PB[12] / GPIO[28] / CS1_0 / E0UC[4] / ANX[0]PD[12] / GPIO[60] / CS5_0 / ADC0_S[4] / E0UC[24]PB[11] / GPIO[27] / E0UC[3] / ADC0_S[3] / CS0_0PD[11] / GPIO[59] / ADC0_P[15]PD[10] / GPIO[58] / ADC0_P[14]PD[9] / GPIO[57] / ADC0_P[13]PB[7] / GPIO[23] / ADC0_P[3]PB[6] / GPIO[22] / ADC0_P[2]PB[5] / GPIO[21] / ADC0_P[1]VDD_HV_ADCVSS_HV_ADC
WK
PU
[12]
/ LI
N1R
X /
GP
IO[3
9] /
PC
[7]
WK
PU
[10]
/ S
CK
0 / C
S0_
0 / G
PIO
[15]
/ PA
[15]
EIR
Q[4
] / C
S0_
0 / S
CK
0 / G
PIO
[14]
/ PA
[14]
WK
PU
[9] /
E0U
C[4
] / G
PIO
[4] /
PA
[4]
SO
UT
_0 /
GP
IO[1
3] /
PA[1
3]S
IN_0
/ G
PIO
[12]
/ PA
[12]
VD
D_L
VV
SS
_LV
XTA
LV
SS
_HV
EX
TAL
VD
D_H
VO
SC
32K
_EX
TAL
/ AD
C0_
S[1
] / G
PIO
[25]
/ P
B[9
]O
SC
32K
_XTA
L / A
DC
0_S
[0] /
GP
IO[2
4] /
PB
[8]
WK
PU
[8] /
AD
C0_
S[2
] / G
PIO
[26]
/ P
B[1
0]A
DC
0_P
[4] /
GP
IO[4
8] /
PD
[0]
AD
C0_
P[5
] / G
PIO
[49]
/ P
D[1
]A
DC
0_P
[6] /
GP
IO[5
0] /
PD
[2]
AD
C0_
P[7
] / G
PIO
[51]
/ P
D[3
]A
DC
0_P
[8] /
GP
IO[5
2] /
PD
[4]
AD
C0_
P[9
] / G
PIO
[53]
/ P
D[5
]A
DC
0_P
[10]
/ G
PIO
[54]
/ P
D[6
]A
DC
0_P
[11]
/ G
PIO
[55]
/ P
D[7
]A
DC
0_P
[12]
/ G
PIO
[56]
/ P
D[8
]A
DC
0_P
[0] /
GP
IO[2
0] /
PB
[4]
PB
[2] /
GP
IO[1
8] /
LIN
0TX
/ S
DA
PC
[8] /
GP
IO[4
0] /
LIN
2TX
PC
[13]
/ G
PIO
[45]
/ E
0UC
[13]
/ S
OU
T_2
PC
[12]
/ G
PIO
[44]
/ E
0UC
[12]
/ S
IN_2
PE
[7] /
GP
IO[7
1] /
E0U
C[2
3] /
CS
2_0
/ MA
[0]
PE
[6] /
GP
IO[7
0] /
E0U
C[2
2] /
CS
3_0
/ MA
[1]
PE
[5] /
GP
IO[6
9] /
E0U
C[2
1] /
CS
0_1
/ MA
[2]
PE
[4] /
GP
IO[6
8] /
E0U
C[2
0] /
SC
K_1
/ E
IRQ
[9]
PC
[4] /
GP
IO[3
6] /
SIN
1 / C
AN
3RX
PC
[5] /
GP
IO[3
7] /
SO
UT
_1 /
CA
N3T
X /
EIR
Q[7
]P
E[3
] / G
PIO
[67]
/ E
0UC
[19]
/ S
OU
T_1
PE
[2] /
GP
IO[6
6] /
E0U
C[1
8] /
SIN
_1P
H[9
] / G
PIO
[121
] / T
CK
PC
[0] /
GP
IO[3
2] /
TD
IV
SS
_LV
VD
D_L
VV
DD
_HV
VS
S_H
VP
C[1
] / G
PIO
[33]
/ T
DO
PH
[10]
/ G
PIO
[122
] / T
MS
PA[6
] / G
PIO
[6] /
E0U
C[6
] / E
IRQ
[1]
PA[5
] / G
PIO
[5] /
E0U
C[5
]P
C[2
] / G
PIO
[34]
/ S
CK
1 / C
AN
4TX
/ E
IRQ
[5]
PC
[3] /
GP
IO[3
5] /
CS
0_1
/ MA
[0] /
CA
N1R
X /
CA
N4R
X /
EIR
Q[6
]P
E[1
2] /
GP
IO[7
6] /
SIN
_2 /
E1U
C[1
9] /
EIR
Q[1
1]
LQFP 100
Migration and Device Emulation within the MPC560xB/C/D Family, Rev. 0
Freescale Semiconductor 15
Packages and pinout
This is the description of the LQFP 144 packages:
Table 3. 144 LQFP MPC5604B to MPC5607B comparison
Pin Pad Alternate input functionsAlternate I/O functions
ALT0 ALT1 ALT2 ALT3
1 PB[3] WKPU[11] LIN0RX GPIO[19] E0UC[31] SCL
2 PC[9] WKPU[13] LIN2RX GPIO[41] E0UC[7]
3 PC[14] EIRQ[8] GPIO[46] E0UC[14] SCK_2
4 PC[15] EIRQ[20] GPIO[47] E0UC[15] CS0_2
5 PG[5] WKPU[18] SIN_3 GPIO[101] E1UC[14]
6 PG[4] GPIO[100] E1UC[13] SCK_3
7 PG[3] WKPU[17] GPIO[99] E1UC[12] CS0_3
8 PG[2] GPIO[98] E1UC[11] SOUT_3
9 PA[2] WKPU[3] GPIO[2] E0UC[2] MA[2]
10 PE[0] WKPU[6] CAN5RX GPIO[64] E0UC[16] CAN_samp1_RX
11 PA[1] WKPU[2] GPIO[1] E0UC[1] NMI[0]
12 PE[1] GPIO[65] E0UC[17] CAN5TX
13 PE[8] GPIO[72] CAN2TX E0UC[22] CAN3TX
14 PE[9] WKPU[7] CAN2RX CAN3RX GPIO[73] CAN_samp2_RX
E0UC[23] CAN_samp3_RX
15 PE[10] EIRQ[10] GPIO[74] LIN3TX CS3_1 E1UC[30]
16 PA[0] WKPU[19] GPIO[0] E0UC[0] CLKOUT E0UC[13]
17 PE[11] WKPU[14] LIN3RX GPIO[75] E0UC[24] CS4_1
18 Vpp
19 VDD_HV
20 VSS_HV
21 RESET
22 VSS_LV
23 VDD_LV
24 VDD_BV
25 PG[9] EIRQ[21] LIN7RX GPIO[105] E1UC[18] SCK_2
26 PG[8] EIRQ[15] GPIO[104] E1UC[17] LIN7TX CS0_2
27 PC[11] WKPU[5] CAN1RX CAN4RX GPIO[43] CAN_samp1_RX
CAN_samp4_RX
MA[2]
28 PC[10] GPIO[42] CAN1TX CAN4TX MA[1]
29 PG[7] WKPU[20] LIN6RX GPIO[103] E1UC[16] E1UC[30]
30 PG[6] GPIO[102] E1UC[15] LIN6TX
Migration and Device Emulation within the MPC560xB/C/D Family, Rev. 0
Freescale Semiconductor16
Packages and pinout
31 PB[0] GPIO[16] CAN0TX E0UC[30] LIN0TX
32 PB[1] WKPU[4] CAN0RX LIN0RX GPIO[17] CAN_samp0_RX
E0UC[31]
33 PF[9] WKPU[22] CAN2RX CAN3RX GPIO[89] E1UC[1] CS5_0
34 PF[8] GPIO[88] CAN3TX CS4_0 CAN2TX
35 PF[12] GPIO[92] E1UC[25] LIN5TX
36 PC[6] GPIO[38] LIN1TX E1UC[28]
37 PC[7] WKPU[12] LIN1RX GPIO[39] E1UC[29]
38 PF[10] GPIO[90] CS1_0 LIN4TX E1UC[2]
39 PF[11] WKPU[15] LIN4RX GPIO[91] CS2_0 E1UC[3]
40 PA[15] WKPU[10] GPIO[15] CS0_0 SCK_0 E0UC[1]
41 PF[13] WKPU[16] LIN5RX GPIO[93] E1UC[26]
42 PA[14] EIRQ[4] GPIO[14] SCK_0 CS0_0 E0UC[0]
43 PA[4] WKPU[9] LIN5RX GPIO[4] E0UC[4] CS0_1
44 PA[13] GPIO[13] SOUT_0 E0UC[29]
45 PA[12] EIRQ[17] SIN_0 GPIO[12] E0UC[28] CS3_1
46 VDD_LV
47 VSS_LV
48 XTAL
49 VSS_HV
50 EXTAL
51 VDD_HV
52 PB[9] WKPU[26] ADC1_S[5] ADC0_S[1] GPIO[25]
53 PB[8] WKPU[25] ADC1_S[4] ADC0_S[0] GPIO[24]
54 PB[10] WKPU[8] ADC1_S[6] ADC0_S[2] GPIO[26]
55 PF[0] ADC0_S[8] GPIO[80] E0UC[10] CS3_1
56 PF[1] ADC0_S[9] GPIO[81] E0UC[11] CS4_1
57 PF[2] ADC0_S[10] GPIO[82] E0UC[12] CS0_2
58 PF[3] ADC0_S[11] GPIO[83] E0UC[13] CS1_2
59 PF[4] ADC0_S[12] GPIO[84] E0UC[14] CS2_2
60 PF[5] ADC0_S[13] GPIO[85] E0UC[22] CS3_2
61 PF[6] ADC0_S[14] GPIO[86] E0UC[23] CS1_1
62 PF[7] ADC0_S[15] GPIO[87] CS2_1
63 PD[0] WKPU[27] ADC1_P[4] ADC0_P[4] GPIO[48]
Table 3. 144 LQFP MPC5604B to MPC5607B comparison (continued)
Pin Pad Alternate input functionsAlternate I/O functions
ALT0 ALT1 ALT2 ALT3
Migration and Device Emulation within the MPC560xB/C/D Family, Rev. 0
Freescale Semiconductor 17
Packages and pinout
64 PD[1] WKPU[28] ADC1_P[5] ADC0_P[5] GPIO[49]
65 PD[2] ADC1_P[6] ADC0_P[6] GPIO[50]
66 PD[3] ADC1_P[7] ADC0_P[7] GPIO[51]
67 PD[4] ADC1_P[8] ADC0_P[8] GPIO[52]
68 PD[5] ADC1_P[9] ADC0_P[9] GPIO[53]
69 PD[6] ADC1_P[10] ADC0_P[10] GPIO[54]
70 PD[7] ADC1_P[11] ADC0_P[11] GPIO[55]
71 PD[8] ADC1_P[12] ADC0_P[12] GPIO[56]
72 PB[4] ADC1_P[0] ADC0_P[0] GPIO[20]
73 VSS_HV_ADC0
74 VDD_HV_ADC0
75 PB[5] ADC1_P[1] ADC0_P[1] GPIO[21]
76 PB[6] ADC1_P[2] ADC0_P[2] GPIO[22]
77 PB[7] ADC1_P[3] ADC0_P[3] GPIO[23]
78 PD[9] ADC1_P[13] ADC0_P[13] GPIO[57]
79 PD[10] ADC1_P[14] ADC0_P[14] GPIO[58]
80 PD[11] ADC1_P[15] ADC0_P[15] GPIO[59]
81 PB[11] Vss_HV_ADC1 ADC0_S[3] GPIO[27] E0UC[3] CS0_0
82 PD[12] Vdd_HV_ADC1 ADC0_S[4] GPIO[60] CS5_0 E0UC[24]
83 PB[12] ADC0_X[0] GPIO[28] E0UC[4] CS1_0
84 PD[13] ADC0_S[5] GPIO[61] CS0_1 E0UC[25]
85 PB[13] ADC0_X[1] GPIO[29] E0UC[5] CS2_0
86 PD[14] ADC0_S[6] GPIO[62] CS1_1 E0UC[26]
87 PB[14] ADC0_X[2] GPIO[30] E0UC[6] CS3_0
88 PD[15] ADC0_S[7] GPIO[63] CS2_1 E0UC[27]
89 PB[15] ADC0_X[3] GPIO[31] E0UC[7] CS4_0
90 PA[3] EIRQ[0] ADC1_S[0] GPIO[3] E0UC[3] LIN5TX CS4_1
91 PG[13] GPIO[109] E0UC[27] SCK_4
92 PG[12] GPIO[108] E0UC[26] SOUT_4
93 PH[0] SIN_1 GPIO[112] E1UC[2]
94 PH[1] GPIO[113] E1UC[3] SOUT_1
95 PH[2] GPIO[114] E1UC[4] SCK_1
96 PH[3] GPIO[115] E1UC[5] CS0_1
Table 3. 144 LQFP MPC5604B to MPC5607B comparison (continued)
Pin Pad Alternate input functionsAlternate I/O functions
ALT0 ALT1 ALT2 ALT3
Migration and Device Emulation within the MPC560xB/C/D Family, Rev. 0
Freescale Semiconductor18
Packages and pinout
97 PG[1] EIRQ[14] CAN5RX GPIO[97] E1UC[24]
98 PG[0] GPIO[96] CAN5TX E1UC[23]
99 VSS_HV
100 VDD_HV
101 PF[15] EIRQ[13] CAN1RX CAN4RX GPIO[95] E1UC[4]
102 PF[14] GPIO[94] CAN4TX E1UC[27] CAN1TX
103 PE[13] GPIO[77] SOUT_2 E1UC[20]
104 PA[7] EIRQ[2] ADC1_S[1] GPIO[7] E0UC[7] LIN3TX
105 PA[8] EIRQ[3] ABS[0] LIN3RX GPIO[8] E0UC[8] E0UC[14]
106 PA[9] FAB GPIO[9] E0UC[9] CS2_1
107 PA[10] ADC1_S[2] GPIO[10] E0UC[10] SDA LIN2TX
108 PA[11] EIRQ[16] ADC1_S[3] LIN2RX GPIO[11] E0UC[11] SCL
109 PE[12] EIRQ[11] ADC1_S[7] SIN_2 GPIO[76] E1UC[19]
110 PG[14] GPIO[110] E1UC[0] LIN8TX
111 PG[15] LIN8RX GPIO[111] E1UC[1]
112 PE[14] EIRQ[12] GPIO[78] SCK_2 E1UC[21]
113 PE[15] GPIO[79] CS0_2 E1UC[22]
114 PG[10] SIN_4 GPIO[106] E0UC[24] E1UC[31]
115 PG[11] GPIO[107] E0UC[25] CS0_4
116 PC[3] EIRQ[6] CAN4RX CAN1RX GPIO[35] CS0_1 MA[0]
117 PC[2] EIRQ[5] GPIO[34] SCK_1 CAN4TX
118 PA[5] GPIO[5] E0UC[5] LIN4TX
119 PA[6] EIRQ[1] LIN4RX GPIO[6] E0UC[6] CS1_1
120 PH[10] GPIO[122] TMS
121 PC[1] GPIO[33] TDO
122 VSS_HV
123 VDD_HV
124 VDD_LV
125 VSS_LV
126 PC[0] GPIO[32] TDI
127 PH[9] GPIO[121] TCK
128 PE[2] EIRQ[21] SIN_1 GPIO[66] E0UC[18]
129 PE[3] GPIO[67] E0UC[19] SOUT_1
Table 3. 144 LQFP MPC5604B to MPC5607B comparison (continued)
Pin Pad Alternate input functionsAlternate I/O functions
ALT0 ALT1 ALT2 ALT3
Migration and Device Emulation within the MPC560xB/C/D Family, Rev. 0
Freescale Semiconductor 19
Packages and pinout
130 PC[5] EIRQ[7] GPIO[37] SOUT_1 CAN3TX
131 PC[4] EIRQ[18] SIN_1 CAN3RX GPIO[36] E1UC[31]
132 PE[4] EIRQ[9] GPIO[68] E0UC[20] SCK_1
133 PE[5] GPIO[69] E0UC[21] CS0_1 MA[2]
134 PH[4] GPIO[116] E1UC[6]
135 PH[5] GPIO[117] E1UC[7]
136 PH[6] GPIO[118] E1UC[8] MA[2]
137 PH[7] GPIO[119] E1UC[9] CS3_2 MA[1]
138 PH[8] GPIO[120] E1UC[10] CS2_2 MA[0]
139 PE[6] EIRQ[22] GPIO[70] E0UC[22] CS3_0 MA[1]
140 PE[7] EIRQ[23] GPIO[71] E0UC[23] CS2_0 MA[0]
141 PC[12] EIRQ[19] SIN_2 GPIO[44] E0UC[12]
142 PC[13] GPIO[45] E0UC[13] SOUT_2
143 PC[8] GPIO[40] LIN2TX E0UC[3]
144 PB[2] GPIO[18] LIN0TX SDA E0UC[30]
Table 3. 144 LQFP MPC5604B to MPC5607B comparison (continued)
Pin Pad Alternate input functionsAlternate I/O functions
ALT0 ALT1 ALT2 ALT3
Migration and Device Emulation within the MPC560xB/C/D Family, Rev. 0
Freescale Semiconductor20
Packages and pinout
Figure 8. MPC5607B LQFP144 package
123456789101112131415161718192021222324252627282930313233343536
108107106105104103102101100
999897969594939291908988878685848382818079787776757473
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
LIN0RX/WKPU[11]/SCL/E0UC[31]/GPIO[19]/PB[3]LIN2RX/WKPU[13]/E0UC[7]/GPIO[41]/PC[9]
EIRQ[8]/SCK2/E0UC[14]/GPIO[46]/PC[14]EIRQ[20]/CS0_2/E0UC[15]/GPIO[47]/PC[15]SIN_3/WKPU[18]/E1UC[14]/GPIO[101]/PG[5]
SCK_3/E1UC[13]/GPIO[100]/PG[4]WKPU[17]/CS0_3/E1UC[12]/GPIO[99]/PG[3]
SOUT_3/E1UC[11]/GPIO[98]/PG[2]MA[2]/WKPU[3]/E0UC[2]/GPIO[2]/PA[2]
CAN5RX/WKPU[6]/E0UC[16]/GPIO[64]/PE[0]WKPU[2]/NMI[0]/E0UC[1]/GPIO[1]/PA[1]
CAN5TX/E0UC[17]/GPIO[65]/PE[1]CAN3TX/E0UC[22]/CAN2TX/GPIO[72]/PE[8]
CAN3RX/CAN2RX/WKPU[7]/E0UC[23]/GPIO[73]/PE[9]EIRQ[10]/E1UC[30]/CS3_1/LIN3TX/GPIO[74]/PE[10]
WKPU[19]/E0UC[13]/CLKOUT/E0UC[0]/GPIO[0]/PA[0]LIN3RX/WKPU[14]/CS4_1/E0UC[24]/GPIO[75]/PE[11]
VSS_HVVDD_HVVSS_HV
RESETVSS_LVVDD_LVVDD_BV
LIN7RX/EIRQ[21]/SCK_2/E1UC[18]/GPIO[105]/PG[9]EIRQ[15]/CS0_2/LIN7TX/E1UC[17]/GPIO[104]/PG[8]CAN4RX/CAN1RX/WKPU[5]/MA[2]/GPIO[43]/PC[11]
MA[1]/CAN4TX/CAN1TX/GPIO[42]/PC[10]LIN6RX/WKPU[20]/E1UC[30]/E1UC[16]/GPIO[103]/PG[7]
LIN6TX/E1UC[15]/GPIO[102]/PG[6]LIN0TX/E0UC[30]/CAN0TX/GPIO[16]/PB[0]
LIN0RX/CAN0RX/WKPU[4]/E0UC[31]/GPIO[17]/PB[1]CAN2RX/CAN3RX/WKPU[22]/CS5_0/E1UC[1]/GPIO[89]/PF[9]
CAN2TX/CS4_0/CAN3TX/GPIO[88]/PF[8]LIN5TX/E1UC[25]/GPIO[92]/PF[12]E1UC[28]/LIN1TX/GPIO[38]/PC[6]
PA[11]/GPIO[11]/E0UC[11]/SCL/EIRQ[16]/LIN2RX/ADC1_S[3]PA[10]/GPIO[10]/E0UC[10]/SDA/LIN2TX/ADC1_S[2]PA[9]/GPIO[9]/E0UC[9]/FAB/CS2_1PA[8]/GPIO[8]/E0UC[8]/E0UC[14]/EIRQ[3]/ABS[0]/LIN3RXPA[7]/GPIO[7]/E0UC[7]/LIN3TX/EIRQ[2]/ADC1_S[1]PE[13]/GPIO[77]/SOUT_2/E1UC[20]PF[14]/GPIO[94]/CAN4TX/E1UC[27]/CAN1TXPF[15]/GPIO[95]/E1UC[4]/EIRQ[13]/CAN4RX/CAN1RXVDD_HVVSS_HVPG[0]/GPIO[96]/CAN5TX/E1UC[23]PG[1]/GPIO[97]/E1UC[24]/EIRQ[14]/CAN5RXPH[3]/GPIO[115]/E1UC[5]/CS0_1PH[2]/GPIO[114]/E1UC[4]/SCK_1PH[1]/GPIO[113]/E1UC[3]/SOUT_1PH[0]/GPIO[112]/E1UC[2]/SIN_1PG[12]/GPIO[108]/E0UC[26]/SOUT_4PG[13]/GPIO[109]/E0UC[27]/SCK_4PA[3]/GPIO[3]/E0UC[3]/LIN5TX/EIRQ[0]/CS4_1/ADC1_S[0]PB[15]/GPIO[31]/E0UC[7]/CS4_0/ADC0_X[3]PD[15]/GPIO[63]/CS2_1/E0UC[27]/ADC0_S[7]PB[14]/GPIO[30]/E0UC[6]/CS3_ 0/ADC0_X[2]PD[14]/GPIO[62]/CS1_1/E0UC[26]/ADC0_S[6]PB[13]/GPIO[29]/E0UC[5]/CS2_0/ADC0_X[1]PD[13]/GPIO[61]/CS0_1/E0UC[25]/ADC0_S[5]PB[12]/GPIO[28]/E0UC[4]/CS1_0/ADC0_X[0]VDD_HV_ADC1VSS_HV_ADC1PD[11]/GPIO[59]/ADC0_P[15]/ADC1_P[15]PD[10]/GPIO[58]/ADC0_P[14]/ADC1_P[14]PD[9]/GPIO[57]/ADC0_P[13]/ADC1_P[13]PB[7]/GPIO[23]/ADC0_P[3]/ADC1_P[3]PB[6]/GPIO[22]/ADC0_P[2]/ADC1_P[2]PB[5]/GPIO[21]/ADC0_P[1]/ADC1_P[1]VDD_HV_ADC0VSS_HV_ADC0
LIN
1RX
/WK
PU
[12]
/E1U
C[2
9]/G
PIO
[39]
/PC
[7]
E1U
C[2
]/L
IN4T
X/C
S1_
0/G
PIO
[90]
/PF
[10]
LIN
4RX
/WK
PU
[15]
/E1U
C[3
]/C
S2_
0/G
PIO
[91]
/PF
[11]
WK
PU
[10]
/E0U
C[1
]/S
CK
_0/C
S0_
0/G
PIO
[15]
/PA
[15]
LIN
5RX
/WK
PU
[16]
/E1U
C[2
6]/G
PIO
[93]
/PF
[13]
EIR
Q[4
]/E0U
C[0
]/C
S0_
0/S
CK
_0/G
PIO
[14]
/PA
[14]
CS
0_1\
LIN
5RX
/WK
PU
[9]/E
0UC
[4]/G
PIO
[4]/P
A[4
]E
0UC
[29]
/SO
UT
_0/G
PIO
[13]
/PA
[13]
CS
3_1\
EIR
Q[1
7]/S
IN_0
/E0U
C[2
8]/G
PIO
[12]
/PA
[12]
VD
D_L
VV
SS
_LV
XTA
LV
SS
_HV
EX
TAL
VD
D_H
VA
DC
1_S
[5]/
32K
XTA
L/W
KP
U[2
6]/A
DC
0_S
[1]/G
PIO
[25]
/PB
[9]
AD
C1_
S[4
]\32
KX
TAL/
WK
PU
[25]
/AD
C0_
S[0
]/GP
IO[2
4]/P
B[8
]A
DC
1_S
[6]\
WK
PU
[8]/A
DC
0_S
[2]/G
PIO
[26]
/PB
[10]
AD
C0_
S[8
]/CS
3_1/
E0U
C[1
0]/G
PIO
[80]
/PF
[0]
AD
C0_
S[9
]/CS
4_1/
E0U
C[1
1]/G
PIO
[81]
/PF
[1]
AD
C0_
S[1
0]/C
S0_
2/E
0UC
[12]
/GP
IO[8
2]/P
F[2
]A
DC
0_S
[11]
/CS
1_2/
E0U
C[1
3]/G
PIO
[83]
/PF
[3]
AD
C0_
S[1
2]/C
S2_
2/E
0UC
[14]
/GP
IO[8
4]/P
F[4
]A
DC
0_S
[13]
/CS
3_2/
E0U
C[2
2]/G
PIO
[85]
/PF
[5]
AD
C0_
S[1
4]/C
S1_
1/E
0UC
[23]
/GP
IO[8
6]/P
F[6
]A
DC
0_S
[15]
/CS
2_1/
GP
IO[8
7]/P
F[7
]A
DC
1_P
[4]\
AD
C0_
P[4
]/WK
PU
[27]
/GP
IO[4
8]/P
D[0
]A
DC
1_P
[5]\
AD
C0_
P[5
]/WK
PU
[28]
/GP
IO[4
9]/P
D[1
]A
DC
1_P
[6]/
AD
C0_
P[6
]/GP
IO[5
0]/P
D[2
]A
DC
1_P
[7]/
AD
C0_
P[7
]/GP
IO[5
1]/P
D[3
]A
DC
1_P
[8]/
AD
C0_
P[8
]/GP
IO[5
2]/P
D[4
]A
DC
1_P
[9]/
AD
C0_
P[9
]/GP
IO[5
3]/P
D[5
]A
DC
1_P
[10]
/AD
C0_
P[1
0]/G
PIO
[54]
/PD
[6]
AD
C1_
P[1
1]/A
DC
0_P
[11]
/GP
IO[5
5]/P
D[7
]A
DC
1_P
[12]
/AD
C0_
P[1
2]/G
PIO
[56]
/PD
[8]
AD
C1_
P[0
]/A
DC
0_P
[0]/G
PIO
[20]
/PB
[4]
PB
[2]/G
PIO
[18]
/LIN
0TX
/SD
A/E
0UC
[30]
PC
[8]/G
PIO
[40]
/LIN
2TX
/E0U
C[3
]P
C[1
3]/G
PIO
[45]
/E0U
C[1
3]/S
OU
T_2
PC
[12]
/GP
IO[4
4]/E
0UC
[12]
/EIR
Q[1
9]/S
IN_2
PE
[7]/G
PIO
[71]
/E0U
C[2
3]/C
S2_
0/M
A[0
]/EIR
Q[2
3]P
E[6
]/GP
IO[7
0]/E
0UC
[22]
/CS
3_0/
MA
[1]/E
IRQ
[22]
PH
[8]/G
PIO
[120
]/E1U
C[1
0]/C
S2_
2/M
A[0
]P
H[7
]/GP
IO[1
19]/E
1UC
[9]/C
S3_
2/M
A[1
]P
H[6
]/GP
IO[1
18]/E
1UC
[8]/M
A[2
]P
H[5
]/GP
IO[1
17]/E
1UC
[7]
PH
[4]/G
PIO
[116
]/E1U
C[6
]P
E[5
]/GP
IO[6
9]/E
0UC
[21]
/CS
0_1/
MA
[2]
PE
[4]/G
PIO
[68]
/E0U
C[2
0]/S
CK
_1/E
IRQ
[9]
PC
[4]/G
PIO
[36]
/E1U
C[3
1]/E
IRQ
[18]
/SIN
_1/C
AN
3RX
PC
[5]/G
PIO
[37]
/SO
UT
_1/C
AN
3TX
/EIR
Q[7
]P
E[3
]/GP
IO[6
7]/E
0UC
[19]
/SO
UT
_1P
E[2
]/GP
IO[6
6]/E
0UC
[18]
/EIR
Q[2
1]/S
IN_1
PH
[9]/G
PIO
[121
]/TC
KP
C[0
]/GP
IO[3
2]/T
DI
VS
S_L
VV
DD
_LV
VD
D_H
VV
SS
_HV
PC
[1]/G
PIO
[33]
/TD
OP
H[1
0]/G
PIO
[122
]/TM
SPA
[6]/G
PIO
[6]/E
0UC
[6]/E
IRQ
[1]/L
IN4R
X/C
S1_
1PA
[5]/G
PIO
[5]/E
0UC
[5]/L
IN4T
XP
C[2
]/GP
IO[3
4]/S
CK
_1/C
AN
4TX
/EIR
Q[5
]P
C[3
]/GP
IO[3
5]/C
S0_
1/M
A[0
]/EIR
Q[6
]/CA
N4R
X/C
AN
1RX
PG
[11]
/GP
IO[1
07]/E
0UC
[25]
/CS
0_4
PG
[10]
/GP
IO[1
06]/E
0UC
[24]
/E1U
C[3
1]/S
IN_4
PE
[15]
/GP
IO[7
9]/C
S0_
2/E
1UC
[22]
PE
[14]
/GP
IO[7
8]/S
CK
_2/E
1UC
[21]
/EIR
Q[1
2]P
G[1
5]/G
PIO
[111
]/E1U
C[1
]/LIN
8RX
PG
[14]
/GP
IO[1
10]/E
1UC
[0]/L
IN8T
XP
E[1
2]/G
PIO
[76]
/E1U
C[1
9]/E
IRQ
[11]
/SIN
_2/A
DC
1_S
[7]
144 LQFP
Top view
Migration and Device Emulation within the MPC560xB/C/D Family, Rev. 0
Freescale Semiconductor 21
Device ID
Figure 9. MPC5604B LQFP144 package
4 Device IDThe MCU ID registers MIDR1 and MIDR2 contain information pertaining to the device including part number, package type, mask set information, and parametric data such as flash size and inclusion of data flash.
The device identification register within the JTAG controller is read by debuggers to identify the device under test.
123456789101112131415161718192021222324252627282930313233343536
108107106105104103102101100
999897969594939291908988878685848382818079787776757473
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
LIN0RX/WKPU[11]/SCL/GPIO[19]/PB[3]LIN2RX/WKPU[13]/GPIO[41]/PC[9]
EIRQ[8]/SCK2/E0UC[14]/GPIO[46]/PC[14]CS0_2/E0UC[15]/GPIO[47]/PC[15]
WKPU[18]/E1UC[14]/GPIO[101]/PG[5]E1UC[13]/GPIO[100]/PG[4]
WKPU[17]/E1UC[12]/GPIO[99]/PG[3]E1UC[11]/GPIO[98]/PG[2]
WKPU[3]/E0UC[2]/GPIO[2]/PA[2]CAN5RX/WKPU[6]/E0UC[16]/GPIO[64]/PE[0]
WKPU[2]/NMI[0]/E0UC[1]/GPIO[1]/PA[1]CAN5TX/E0UC[17]/GPIO[65]/PE[1]
CAN3TX/E0UC[22]/CAN2TX/GPIO[72]/PE[8]CAN3RX/CAN2RX/WKPU[7]/E0UC[23]/GPIO[73]/PE[9]
EIRQ[10]/CS3_1/LIN3TX/GPIO[74]/PE[10]WKPU[19]/CLKOUT/E0UC[0]/GPIO[0]/PA[0]LIN3RX/WKPU[14]/CS4_1/GPIO[75]/PE[11]
VSS_HVVDD_HVVSS_HV
RESETVSS_LVVDD_LVVDD_BV
SCK_2/E1UC[18]/GPIO[105]/PG[9]EIRQ[15]/CS0_2/E1UC[17]/GPIO[104]/PG[8]
CAN4RX/CAN1RX/WKPU[5]/GPIO[43]/PC[11]MA[1]/CAN4TX/CAN1TX/GPIO[42]/PC[10]
E1UC[16]/GPIO[103]/PG[7]E1UC[15]/GPIO[102]/PG[6]
CAN0TX/GPIO[16]/PB[0]CAN0RX/WKPU[4]/GPIO[17]/PB[1]
CAN2RX/CAN3RX/CS5_0/GPIO[89]/PF[9]CAN2TX/CS4_0/CAN3TX/GPIO[88]/PF[8]
E1UC[25]/GPIO[92]/PF[12]LIN1TX/GPIO[38]/PC[6]
PA[11]/GPIO[11]/E0UC[11]/SCLPA[10]/GPIO[10]/E0UC[10]/SDAPA[9]/GPIO[9]/E0UC[9]/FABPA[8]/GPIO[8]/E0UC[8]/EIRQ[3]/ABS[0]/LIN3RXPA[7]/GPIO[7]/E0UC[7]/LIN3TX/EIRQ[2]PE[13]/GPIO[77]/SOUT_2/E1UC[20]PF[14]/GPIO[94]/CAN4TX/E1UC[27]/CAN1TXPF[15]/GPIO[95]/EIRQ[13]/CAN4RX/CAN1RXVDD_HVVSS_HVPG[0]/GPIO[96]/CAN5TX/E1UC[23]PG[1]/GPIO[97]/E1UC[24]/EIRQ[14]/CAN5RXPH[3]/GPIO[115]/E1UC[5]/CS0_1PH[2]/GPIO[114]/E1UC[4]/SCK_1PH[1]/GPIO[113]/E1UC[3]/SOUT_1PH[0]/GPIO[112]/E1UC[2]/SIN_1PG[12]/GPIO[108]/E0UC[26]PG[13]/GPIO[109]/E0UC[27]PA[3]/GPIO[3]/E0UC[3]/EIRQ[0]/ADC1_S[0]PB[15]/GPIO[31]/E0UC[7]/CS4_0/ADC0_X[3]PD[15]/GPIO[63]/CS2_1/E0UC[27]/ADC0_S[7]PB[14]/GPIO[30]/E0UC[6]/CS3_ 0/ADC0_X[2]PD[14]/GPIO[62]/CS1_1/E0UC[26]/ADC0_S[6]PB[13]/GPIO[29]/E0UC[5]/CS2_0/ADC0_X[1]PD[13]/GPIO[61]/CS0_1/E0UC[25]/ADC0_S[5]PB[12]/GPIO[28]/E0UC[4]/CS1_0/ADC0_X[0]PB[11]/GPIO[27]/ADC0_S[3]/E0UC[3]/CS0_0PD[12]/GPIO[60]/ADC0_S[4]/E0UC[24]/CS5_0PD[11]/GPIO[59]/ADC0_P[15]PD[10]/GPIO[58]/ADC0_P[14]PD[9]/GPIO[57]/ADC0_P[13]PB[7]/GPIO[23]/ADC0_P[3]PB[6]/GPIO[22]/ADC0_P[2]PB[5]/GPIO[21]/ADC0_P[1]VDD_HV_ADC0VSS_HV_ADC0
LIN
1RX
/WK
PU
[12]
/GP
IO[3
9]/P
C[7
]G
PIO
[90]
/PF
[10]
WK
PU
[15]
/GP
IO[9
1]/P
F[1
1]W
KP
U[1
0]/S
CK
_0/C
S0_
0/G
PIO
[15]
/PA
[15]
WK
PU
[16]
/E1U
C[2
6]/G
PIO
[93]
/PF
[13]
EIR
Q[4
]/CS
0_0/
SC
K_0
/GP
IO[1
4]/P
A[1
4]LI
N5R
X/W
KP
U[9
]/E0U
C[4
]/GP
IO[4
]/PA
[4]
SO
UT
_0/G
PIO
[13]
/PA
[13]
EIR
Q[1
7]/S
IN_0
/GP
IO[1
2]/P
A[1
2]V
DD
_LV
VS
S_L
VX
TAL
VS
S_H
VE
XTA
LV
DD
_HV
32K
XTA
L/A
DC
0_S
[1]/G
PIO
[25]
/PB
[9]
32K
XTA
L/A
DC
0_S
[0]/G
PIO
[24]
/PB
[8]
WK
PU
[8]/A
DC
0_S
[2]/G
PIO
[26]
/PB
[10]
AD
C0_
S[8
]/CS
3_1/
E0U
C[1
0]/G
PIO
[80]
/PF
[0]
AD
C0_
S[9
]/CS
4_1/
E0U
C[1
1]/G
PIO
[81]
/PF
[1]
AD
C0_
S[1
0]/C
S0_
2/E
0UC
[12]
/GP
IO[8
2]/P
F[2
]A
DC
0_S
[11]
/CS
1_2/
E0U
C[1
3]/G
PIO
[83]
/PF
[3]
AD
C0_
S[1
2]/C
S2_
2/E
0UC
[14]
/GP
IO[8
4]/P
F[4
]A
DC
0_S
[13]
/CS
3_2/
E0U
C[2
2]/G
PIO
[85]
/PF
[5]
AD
C0_
S[1
4]/E
0UC
[23]
/GP
IO[8
6]/P
F[6
]A
DC
0_S
[15]
/GP
IO[8
7]/P
F[7
]A
DC
0_P
[4]/G
PIO
[48]
/PD
[0]
AD
C0_
P[5
]/GP
IO[4
9]/P
D[1
]A
DC
0_P
[6]/G
PIO
[50]
/PD
[2]
AD
C0_
P[7
]/GP
IO[5
1]/P
D[3
]A
DC
0_P
[8]/G
PIO
[52]
/PD
[4]
AD
C0_
P[9
]/GP
IO[5
3]/P
D[5
]A
DC
0_P
[10]
/GP
IO[5
4]/P
D[6
]A
DC
0_P
[11]
/GP
IO[5
5]/P
D[7
]A
DC
0_P
[12]
/GP
IO[5
6]/P
D[8
]A
DC
0_P
[0]/G
PIO
[20]
/PB
[4]
PB
[2]/G
PIO
[18]
/LIN
0TX
/SD
AP
C[8
]/GP
IO[4
0]/L
IN2T
XP
C[1
3]/G
PIO
[45]
/E0U
C[1
3]/S
OU
T_2
PC
[12]
/GP
IO[4
4]/E
0UC
[12]
/SIN
_2P
E[7
]/GP
IO[7
1]/E
0UC
[23]
/CS
2_0/
MA
[0]
PE
[6]/G
PIO
[70]
/E0U
C[2
2]/C
S3_
0/M
A[1
]P
H[8
]/GP
IO[1
20]/E
1UC
[10]
/CS
2_2/
MA
[0]
PH
[7]/G
PIO
[119
]/E1U
C[9
]/CS
3_2/
MA
[1]
PH
[6]/G
PIO
[118
]/E1U
C[8
]/MA
[2]
PH
[5]/G
PIO
[117
]/E1U
C[7
]P
H[4
]/GP
IO[1
16]/E
1UC
[6]
PE
[5]/G
PIO
[69]
/E0U
C[2
1]/C
S0_
1/M
A[2
]P
E[4
]/GP
IO[6
8]/E
0UC
[20]
/SC
K_1
/EIR
Q[9
]P
C[4
]/GP
IO[3
6]/E
IRQ
[18]
/SIN
_1/C
AN
3RX
PC
[5]/G
PIO
[37]
/SO
UT
_1/C
AN
3TX
/EIR
Q[7
]P
E[3
]/GP
IO[6
7]/E
0UC
[19]
/SO
UT
_1P
E[2
]/GP
IO[6
6]/E
0UC
[18]
/SIN
_1P
H[9
]/GP
IO[1
21]/T
CK
PC
[0]/G
PIO
[32]
/TD
IV
SS
_LV
VD
D_L
VV
DD
_HV
VS
S_H
VP
C[1
]/GP
IO[3
3]/T
DO
PH
[10]
/GP
IO[1
22]/T
MS
PA[6
]/GP
IO[6
]/E0U
C[6
]/EIR
Q[1
]PA
[5]/G
PIO
[5]/E
0UC
[5]
PC
[2]/G
PIO
[34]
/SC
K_1
/CA
N4T
X/E
IRQ
[5]
PC
[3]/G
PIO
[35]
/CS
0_1/
MA
[0]/E
IRQ
[6]/C
AN
4RX
/CA
N1R
XP
G[1
1]/G
PIO
[107
]/E0U
C[2
5]P
G[1
0]/G
PIO
[106
]/E0U
C[2
4]P
E[1
5]/G
PIO
[79]
/CS
0_2/
E1U
C[2
2]P
E[1
4]/G
PIO
[78]
/SC
K_2
/E1U
C[2
1]/E
IRQ
[12]
PG
[15]
/GP
IO[1
11]/E
1UC
[1]
PG
[14]
/GP
IO[1
10]/E
1UC
[0]
PE
[12]
/GP
IO[7
6]/E
1UC
[19]
/EIR
Q[1
1]/S
IN_2
144 LQFP
Top view
Migration and Device Emulation within the MPC560xB/C/D Family, Rev. 0
Freescale Semiconductor22
Migrating from MPC5604B to MPC5607B
Table 4 details the register contents for each device and package option. Software that depends on the contents of this register should be modified. Refer to the respective device reference manuals for full bit level descriptions of these registers.
:
NOTE0xXX denote mask set and revision number.
5 Migrating from MPC5604B to MPC5607BWhile migrating an application from MPC5604B to MPC5607B, the user should pay attention to:
• Pins
• ADC
• LinFlex
• eMIOS
5.1 PinsPB11 and PD12 are available on MPC5604B on all packages. PB11 and PD12 are not available on MPC5607B on the LQFP100 and LQFP144 packages. If an application on the MPC5604B uses these pins then a modification will be mandatory to route these features to other IOs.
Table 4. Device ID Registers (table to be updated)
Device Package Flash size MIDR1 MIDR2 JTAGC ID
MPC5604C 100LQFP 512 KB 0x5604_34XX 0x2800_4310 TBD
MPC5604B 144LQPF 512 KB 0x5604_34XX 0x2800_4210 TBD
MPC5604B 100LQFP 512 KB 0x5604_24XX 0x2800_4210 TBD
MPC5603C 100LQPF 384 KB 0x5603_24XX 0x2200_4310 TBD
MPC5603B 144LQPF 384 KB 0x5603_34XX 0x2200_4210 TBD
MPC5603B 100LQPF 384 KB 0x5603_24XX 0x2200_4210 TBD
MPC5602C 100LQPF 256 KB 0x5602_24XX 0x2000_4310 TBD
MPC5602B 144LQPF 256 KB 0x5602_34XX 0x2000_4210 TBD
MPC5602B 100LQPF 256 KB 0x5602_24XX 0x2000_4210 TBD
MPC5601D 100LQPF 128 KB 0x5601_24XX 0x1800_4410 0x0AE4401D
MPC5601D 64LQPF 128 KB 0x5601_04XX 0x1800_4410 0x0AE4401D
MPC5602D 100LQPF 256 KB 0x5602_24XX 0x2000_4410 0x0AE4401D
MPC5602D 64LQPF 256 KB 0x5602_04XX 0x2000_4410 0x0AE4401D
Migration and Device Emulation within the MPC560xB/C/D Family, Rev. 0
Freescale Semiconductor 23
Migrating from MPC5607B to MPC5604B
5.2 ADCMPC5607B and MPC5604B have the same number of ADC0 10-bit channels (sixteen precise, twenty-eight standard, and four extended). However, threshold implementation is different. An application using them on MPC5604B should be modified as follows to migrate to MPC5607B:
• Do not use Threshold Control Registers (TRC[0..3]) since they are unavailable on MPC5607B.
— Instead use Channel Watchdog Enable Register (CWEN0), with Channel Watchdog Selection Registers (CWSEL[0..1]).
• Rewrite usage of Watchdog Threshold Interrupt Mask Register (WTIMR) and Watchdog Threshold Interrupt Status Register (WTISR).
— MPC5604B low and high threshold bits are grouped in the registers.
— MPC5607B low and high threshold bits are grouped two by two. Therefore usage of these registers must be rewritten.
— In addition, MPC5607B Analog Watchdog Out of Range Register (AWORR0) gives information about channel numbers that were out of analog range.
5.3 LinFlexThe two first LinFlex modules of the MPC5607B are actually LinFlexD modules, which can handle DMA requests and FIFO for UART mode. Since this module is a superset of the standard LinFlex module present on MPC5604B, there will be no issue in migration, due to this upward compatibility.
5.4 eMIOSImplementation of MPC5607B is a superset of the one present on MPC5604B. Therefore, there will be no issue in migration, due to this upward compatibility.
6 Migrating from MPC5607B to MPC5604BWhile migrating an application from MPC5607B to MPC5604B, the user should pay attention to:
• Pins
• Regulator
• Clocks
• RAM
• Flash
• DMA
• PIT
• eMIOS
• ADC
• CTU
• LINFlex
Migration and Device Emulation within the MPC560xB/C/D Family, Rev. 0
Freescale Semiconductor24
Migrating from MPC5607B to MPC5604B
• DSPI
6.1 PinsOn their common set of features, there will be no issue on pin mapping while migrating. Refer to the pin mapping differences for further details.
6.2 RegulatorMPC5607B ballast feature is not available on MPC5604B.
6.3 ClocksMPC5607B ability to have system or RTC clock on the CLKOUT is not available with MPC5604B. Any application relying on this feature will not work.
6.4 RAMMPC5604B has less available RAM in Power Domain 2 than MPC5607B. An application will have to be recoded to fit the smaller RAM size.
6.5 FlashMPC5604B has less available code flash than MPC5607B. An application will have to be recoded to fit the smaller code flash size.
Data flash is the same in both cases.
6.6 DMAMPC5607B has a DMA with DMAMUX — MPC5604B does not. Therefore, any code or usage of registers or interrupts related to DMA will not work. An application will need to be recoded without DMA usage.
6.7 PITMPC5607B has eight PITs. MPC5604B has six. Table 5 and Table 6 show respective implementation details regarding internal connections.
Table 5. MPC5607B PIT details
PIT Interrupt Peripheral
triggerDMA trigger
0 YES NO YES
1 YES NO YES
2 YES 10-bit ADC NO
3 YES CTU ch28 NO
Migration and Device Emulation within the MPC560xB/C/D Family, Rev. 0
Freescale Semiconductor 25
Migrating from MPC5607B to MPC5604B
Therefore, an application using PIT6 and PIT7 will not work with MPC5604B and must be reworked.
6.8 eMIOSMPC5604B has fewer channels on each eMIOS, and its channels have a different feature set than MPC5607B. Refer to eMIOS comparison to see how to adapt an application for migration.
6.9 ADCMPC5607B has two ADCs, one with 10-bit resolution (ADC0 10-bit) and one with 12-bit resolution (ADC1 12-bit). MPC5604B has only one ADC 10 bit. Any application using ADC1 on MPC5607B will have to be modified to use the ADC0 of MPC5604B.
In addition, an application that uses the analog threshold feature will have to be recoded with scheme and quantities of thresholds available on MPC5604B.
6.10 CTUAll CTU channels above 31 in MPC5607B do not exist on MPC5604B.
6.11 LINFlexMPC5607B LinFlex 4 to 9 can’t be used on MPC5604B. In addition, LinFlex 0 and 1 lose their DMA ability, FIFO on UART mode, and byte length in UART mode, on MPC5604B.
4 YES NO YES
5 YES NO YES
6 YES 12-bit ADC NO
7 YES CTU ch51 NO
Table 6. MPC5604B PIT details
PIT Interrupt Peripheral
triggerDMA trigger
0 YES NO Not applicable
1 YES NO Not applicable
2 YES 10-bit ADC Not applicable
3 YES CTU ch28 Not applicable
4 YES NO Not applicable
5 YES NO Not applicable
Table 5. MPC5607B PIT details (continued)
PIT Interrupt Peripheral
triggerDMA trigger
Migration and Device Emulation within the MPC560xB/C/D Family, Rev. 0
Freescale Semiconductor26
Migrating from MPC5607B to MPC5604B
6.12 DSPIMPC5607B DSPI 3 to 5 cannot be used on MPC5604B.
Migration and Device Emulation within the MPC560xB/C/D Family, Rev. 0
Freescale Semiconductor 27
Document Number: AN4340Rev. 008/2011
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