migrating from powerquicc ii pro processors to qoriq p1020 and

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.

FTF-NET-F0810

Migrating from PowerQUICC II Pro Processors to QorIQ P1020 and P2020 Dual-Core Processors

June, 2010

Farshid Parandian

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 2

Session Objectives

►This session will: • Provide overview and highlight the new features introduced with the

QorIQ™ P1 and P2 device family of processors • Provide the detail on migrating designs from PowerQUICC® II Pro to the

QorIQ™ family

Presenter

Presentation Notes

The objective of this session is to: provide the audience with an high level overview on QorIQ™ P2020 Processor and discus some of the new features. Provide the detail on migrating designs from PowerQUICC II Pro™ to the QorIQ™ family In addition we will also Provide status update of documentation and collaterals currently available for P2020.


Introducing Freescale’s QorIQ Platforms

►Designed to enable the development of the next era of networking applications by delivering

• Improved Processing Performance – High-performance Power Architecture® based multicore solutions

• Power-Efficiency – 45nm process technology for industry-leading power-to-performance solution

• Programmability – Programming tools, ecosystem partners, common software and pin compatible processors

P2020Wire Bond TEPBGA-II~100M transistors>1B vias and contacts

1st silicon in houseTeams validating part atcomponent and board levelAlpha samples launched in

February 2009

Presenter

Presentation Notes

Part of on-going evolution of Freescale Power architecture products. Freescale’s new QorIQ Platform. It includes all SoCs which are based on e500 core, essentially designed for multi-core architecture. The 83xx Socs which have used to so far were using 90 nanometer technology. QorIQ P1xxx & P2xxx SoCs will use 45 nm technology (the P series). Complex processor, more interfaces, higher frequencies and still fit in your power budget (because the 45 nm technology consumes less power). It is easy to migrate since all the components of the ecosystem are already in place to support the new platform (debugger, compiler, OS, boot-loader etc.)


e500 @533MHz-800MHzDual-core / Single-core

256KB L2 Cache3 x GigE (SGMII), PCI-Exp, 2 x USB, DDR2/3, SD FLASH, Security, TDM

5.0W for Dual-Core 800MHz

e500 @800MHz-1200MHzDual-core / Single core

512KB L2 Cache,3 x GigE (SGMII), 2x PCI-Exp,

2x SRIO, 2 x USB, DDR2/3, SD FLASH, Security,

8W @ DC 1200MHz

PowerQUICC II Pro to QorIQ EvolutionP

erfo

rman

ce &

Pow

er

2006 2007 2008 2009 2010 2011

MPC8349E

MPC8347E

MPC8343E

MPC8378E

MPC8379E

MPC8377E

MPC8315E

MPC8314E

266-667MHz2 x GigE2 x PCI

USB, DDR1/2,Security

<5.0W @ 667MHz

MPC8313E

333MHz2 x GigE (SGMII)

PCI, USB, DDR1/2,Security

<2.0W @ 333MHz

400-800MHz2 x GigE (SGMII)

PCI , PCI-ExpUSB, DDR1/2,

Security, SATA<5.0W @ 667MHz

90nm 130nm

Legend45nm

400MHz2 x GigE (SGMII)

PCI, PCI-ExpUSB, DDR1/2,

Security<2.0W @ 400MHz

P2020E

P1020E

Planning Execution ProductionProposal

P2010E

P1011E

4 Devices – All pin compatible

Presenter

Presentation Notes

2006 – 834x (8349/8347/8343) - max power consumption 5 W @ 667 Mhz frequency 2007 – 8313 – 1.2 W @ 333 Mhz frequency 2008 – 837x (8378/8379/8377) –5W @ 667 Mhz 8315, 8314 – 1.6W @ 400 Mhz 2009 – P2020/2010 – 8W @ dual core 1200 Mhz 2010 – P1020/1011 – 5W for dual core 800 Mhz Conclusion: similar power budget and higher frequency and dual core (P1020/1011)


QorIQ™ P1 and P2 Series Summary

Features BenefitsBest in class ecosystem Faster time to market

Migration path Improved performance/watt/$ migrating from PowerQUICC II, PowerQUICC II Pro, and PowerQUICC III

High performance e500 2.4MIPS/MHz Power Architecture™ core

High efficiency and frequency cores means fewer cores to get the job done

Best-in-class power Enables fanless, “green” and low cost designs, improves reliability

Integrated Ethernet, TDM, USB, SD Flash controller, IEEE1588, PCI-Express, Serial RapidIO

Flexibility to address a wide range of applications and reduced system cost

4.5x performance range in a single package (533MHz to 2x1200MHz)

Common hardware platform to enable wide range of system performance

Dual and single cores Move to dual core at your own pace without hardware changes

Presenter

Presentation Notes

Point # 4 - Low power Point # 5 – almost all interfaces on the same SoC. No need to add an extra chip on your board # 6 – same Soc can be used for a variety of applications. From low performance to high performance applications. #7 – The SoCs in P1xxx and P2xxx have a single and dual core versions and upgrading to dual core is easy since the pinout and the package is the same.


QorIQ P2020 / P2010 Block Diagram

Coherency Module

System Bus

32KB I-

Cache

e500 Core

32KBD-

Cache

System Bus

Enhanced Local Bus

64b

Perf Mon, DUART, MPIC2x I2C, Timers

On-Chip Network

32KBI-

Cache

e500 Core

32KBD-

Cache

512KB L2

DDR2/DDR3, SDRAM

Controller

Security Accel

XOR16b

USB2.0

SPI

SD/MMC

3x GE MAC

x4 SerDes

►Single/Dual e500 Power Architecture™ core• 800 - 1200 MHz• 512KB Frontside L2 cache w/ECC, HW cache coherent• 36 bit physical addressing, DP-FPU

►System Unit• 64/32b DDR2/DDR3 with ECC• Integrated SEC 3.1 Security Engine • Open-PIC Interrupt Controller, Perf Mon, 2x I2C, Timers,

16 GPIO’s, DUART• 16-bit Enhanced Local Bus supports booting from NAND

Flash• One USB 2.0 Host Controller with ULPI interface• SPI controller supporting booting from SPI serial Flash• SD/MMC card controller supporting booting from Flash

cards• Three 10/100/1000 Ethernet Controllers (eTSEC) w/

Jumbo Frame support, SGMII interface• Enhanced features: Parser/Filer, QOS, IP-Checksum

Offload, Lossless Flow Control• IEEE 1588v2 support

• Two Serial Rapid I/O Controllers with integrated message unit operating up to 3.125GHz

• Three PCI Express 1.0a Controllers operating at 2.5GHz

►Process & Package• 45nm SOI, 1.05V +/- 50mV, 0C to 125C Tj

• with -40C to 125C Tj option• 689-pin TePBGAII, 31x31mm

► 4.9 W Typ (Est) - Dual Core at 1.2GHz

2x DMA PCI Express

Serial RapidIO

PCI Express

PCI Express

Serial RapidIO

P2020 only

Red = NewBlue = Same

(Compared toPQ2 Pro)

Presenter

Presentation Notes

Changes from 83xx: E300 to e500, second core........... L2 cache which was not in 83xx devices...................except 837x & 8360, all other 83xx devices had 16 KB i-cache and d-cache................ DDR 3 is supported(not in PQ2 Pro) elbc, duart, i2c, timers , usb and spi are all the same as in 83xx PQ....831x and 837x - perf mon monitored performance of e300 core while QorIQ - perf mon monitors the performance of the e500 core as well the that of the complete system 837x is the only soc in 83xx family to support SD/MMC (P2020/10, P1020/11, P1022/13)................... security accelerator / xor is the same with some enhancements Gigabit ethernet MAC is the same......................... All 83xx chips has PCI. additionally only 8315 and 837x have PCI express. QorIQ will have no PCI support. no 83xx has SRIO (Serial rapid IO). ........................... 83xx did not have on-chip network. (OcN) connects all high-speed interfaces to the system bus...........................coherency module is new. maintains data coherency.


►Single / Dual e500 Power Architecture® core; 533 -800 MHz

• 256KB Frontside L2 cache w/ECC, HW cache coherent

• 36 bit physical addressing, DP-FPU►System Unit

• 32-bit DDR2/DDR3, 667 MHz data rate w/ECC• Integrated SEC 3.3 Security Engine • Open-PIC Interrupt Controller, Perf Mon, 2x I2C,

Timers, 16 GPIO’s, DUART• 16-bit Enhanced Local Bus supports booting from

NAND Flash• Two USB 2.0Controllers Host/Device support• SPI controller supporting booting from SPI serial Flash• SD/MMC card controller supporting booting from Flash

cards• TDM interface• Three 10/100/1000 Ethernet Controllers (eTSEC) w/

Jumbo Frame support, SGMII interface• Enhanced features: Parser/Filer, QOS, IP-Checksum Offload, Lossless Flow Control with Interface options:•IEEE1588v2 Support

• Two PCI Express 1.0a Controllers operating up to 2.5Gbps

• Power Management►Process & Package

• 45nm SOI, 0.95V+/-50mV, -40C to 125C Tj• 689-pin TePBGAII

QorIQ1020 / P1011 Block Diagram

Coherency Module

System Bus

32kB I-Cache

e500 Core

32kB D-Cache

System Bus

2x DMA

On-Chip Network

256KB L2

PCI Express

PCI Express

Security AccelXOR

TDM

3x G

E M

AC

32kB I-Cache

e500 Core

32kB D-Cache

Enhanced Local Bus

DDR2/DDR3, SDRAM

Controller

USB2.0

SD/MMC

Perf Mon, DUART, MPIC2x I2C, Timers

SPI

Power Manage-

ment

► X W Typ at 800MHz

P1020 only

SGMII

x4 SERDES

Presenter

Presentation Notes

No SRIO, lesser no. of PCI Express Power management is new wrt P2020 (saves you power by putting the core in power down mode when not in use) TDM is supported so you can use it for applications such VoIP


MPC834x/831x to QorIQ P1 MigrationFeature MPC8343E MPC8313E MPC8314E/ MPC8315E P1020E / P1011E

Core e300 e300 e300 Dual / Single e500v2

CPU Speed Up to 400MHz Up to 400 MHz Up to 400 MHz 533MHz - 800MHz

L1 I/D Cache 32K I/D 16K I/D 16K I/D 32K I/D

L2 Cache - - - 256K I/D

Memory Controller

32/64 bit DDR2 up to 333MHz

16/32 bit DDR/2 up to 333MHz

16/32 bit DDR/2 up to 266MHz 32 bit DDR2/3, up to 667MHz

Ethernet 2-10/100/1000(MII, RGMII & RTBI only) 2-10/100/1000 with SGMII 2-10/100/1000 with SGMII 3-10/100/1000 with SGMII

Local Bus 8/16/32-bit ROM boot 8/16-bit/66MHz w/ NAND & NOR Boot

8/16-bit/66MHz w/ NAND & NOR Boot

8/16/32-bit 83MHz w/ NOR, 8/16-bit NAND Boot

PCIE - - x2 supported 2 Controllers, up to x4 lanes

SATA - - x2 (MPC8315E only) -

USB Hi-SpeedHost or Device

1 -2.0 Host or Device w/PHY

1 -2.0 Host or Device w/PHY 2 x 2.0 Host or Device

Security E version only SEC 2.2 SEC 3.3 SEC 3.3.1

Other1x 32Bit / 66MHz PCI, Dual

I2C, DUART, SPIInterrupt Controller

1x 32Bit / 66MHz PCI,Dual I2C, DUART, SPIInterrupt Controller,

2 SERDES Lanes

1x 32Bit / 66MHz PCI,Dual I2C, DUART, SPIInterrupt Controller,

2 SERDES Lanes

SD/MMC Support, TDM, DUART, Dual I2C, SPI, Interrupt

controller4 SERDES Lanes

Package 620 PBGA 516 TePBGA 620 TePBGA 689 TePBGA II

Power <5W @ 667MHz ~2W @ 333MHz ~2W ~ 5 W (typ) @ 800MHz Dual Core

Samples Now Now Now May 2010

Production Now Now Now Q4 2010

Process 130nm 90nm 90nm 45nm

Presenter

Presentation Notes

Lower performance 834x and 831x Socs can be migrated to P1 series Socs


MPC837x to QorIQ P1 /P2 MigrationMPC8379E MPC8378E MPC8377E P1020 / P1011 P2020 / P2010

Core e300 e300 e300 Dual e500v2 /Single e500v2

Dual e500v2 /Single e500v2

CPU Speed Up to 800 MHz Up to 800 MHz Up to 800 MHz 533MHz - 800MHz 800MHz / 1200 MHz

L1 I/D Cache 32KI/ 32KD 32KI/32KD 32KI/32KD 32K I/D 32K I/D

L2 Cache 256K I/D 512K I/D

Memory Controller




32 bit DDR2/3 up to 667MHz

32/64 bit DDR2/3 up to 800MHz

Local bus 32 bit w/NAND boot support

32 bit w/NAND boot support

32 bit w/NAND boot support

8/16/32-bit 83MHz w/ NOR, 8/16-bit NAND Boot

Support

8/16-bit/ 150MHz w/ NAND & NOR Boot

PCI 1-32 bit up to 66MHz (2.3)

1-32 bit up to 66MHz (2.3)

1-32 bit up to 66MHz (2.3) - -

PCI Express - 2-x1 2-x12 PCIE (1.0a) Controllers

Up to x4 Lanes

3 PCIE (1.0a) Controllers

Up to x4 LanesSATA 4x1 SATA 2.0 w/PHY - 2x1 SATA 2.0 w/PHY - -

Ethernet 2-10/100/1000 (RGMII, RTBI, RMII, MII)

2-10/100/1000 (SGMII, RGMII, RTBI, RMII, MII)

2-10/100/1000 (RGMII, RTBI, RMII, MII)

3-10/100/1000with SGMII support

3-10/100/1000with SGMII support

USB 1- 2.0 Host or Device 1-2.0 Host or Device 1- 2.0 Host or Device 2 x 2.0 Host orDevice

1 x 2.0 Host orDevice

Security SEC 3.0 SEC 3.0 SEC 3.0 SEC 3.3.1 SEC 3.1

OtherDual UART

Dual I2CInterrupt Controller

Dual UARTDual I2C

Interrupt Controller

Dual UARTDual I2C

Interrupt Controller

SD/MMC, TDM, Dual UART


SD/MMC, Dual UART,


Package Te PBGA Te PBGA Te PBGA 689 TePBGA II 689 TePBGA IIGeneral Samples Oct 2007 Oct 2007 Oct 2007 May 2010 Now

Production NOW NOW NOW Q4 2010 July 2010

Presenter

Presentation Notes

The higher performance 837x SoCs should be migrated to either P1 or P2 series socs.


Challenges of Migration

►Before we move on, lets consider what are some of the challenges of design migration…

►Hardware design• Power supply design • What level of actual re-design is required?

Can I use existing interfaces? What are the requirements for new interfaces?

• Power management and thermal performance• Future-proofing and design re-use for other platforms

►Software design • Code set migration – instruction set, library and function support• Operating system and tool support • Software portability and level of re-coding for new features

►Migrating to dual core and multicore

Presenter

Presentation Notes

Lets look at the challenges of migration from PQII pro to P1/P2 From H/W design perspective We have to consider power supply design Re-use of design for existing interfaces Design requirements for new interfaces introduced in P1 / P2 device family. From S/W design perspective We have to consider code set migration OS, Tool support And lastly migration to dual dual and multi core.


QorIQ P1 / P2 Device Features


e500v2 Core Architecture

► Up to 1.2 GHz► L1: 32KB, 8-way set

associative, Parity► L2: Front Side: 8-way

set associative, ECC► Cache line locking

supported► MESI cache coherence► Peak IPC 2 Instructions

plus 1 branch► Out of Order Execution► Multiple Book E APUs► 16 TLB variable page

sizes► 512-entry 4K Pages► 36-bit Physical Address

Instruction Unit

CFX SFX2 LSU

GPRs

RenameBuffers

L1 Data MMUDTLBs

L1 Instruction MMUI-TLBs

Memory Unit

SFX1

L2 Unified MMUs

Book E APUs:Performance

Monitor,SPE, DPFPIsel, BTB,

Cache Line Locking,MachineCheck

Shared512kB Unified

Frontside L2 Cache

CompletionUnit

Instruction Queue (12)

Branch Processing

Unit

GPR Issue (2)

DispatchUnit

Sequencer Fetcher 32KB

InstructionCacheTa

gsTa

gs 32KBData

Cache

MA

S

Core Complex Bus36-bit Address Bus

128-bit Rd/Wr Data Bus

Presenter

Presentation Notes

Signal-Processing Engine (SPE) SPE double-precision floating-point instruction set using 64-bit operands SPE single-precision floating-point instruction set using 32- or 64-bit operands This is the simplified version of the E500 V2 core architecture block diagram. The E500 V2 core Supports: Up to 1.2GHz The L1 cache supports 32KByte, 8-way set associative, w/Parity The L2 cache Front Side is 8-way set associative, w/ ECC Other features are …. Cache line locking Out of Order Execution Multiple Book E APUs 16 TLB Super Pages 512-entry 4K Pages And suport for… 36-bit Physical Address


e500 Core 1

32KB D-cachew/Parity

RD1 RD2 WR

L2 Cache Controller

► Shared 256KB / 512 KB unified front-side L2 cache

► Eight-way associatively (each way: 64 KB)

► Assignment Granularity :• One, two, four, or all eight “ways” of the cache can be

assigned as the following:• SRAM• Stash-Only• CPU0 L2 Only• CPU1 L2 Only• Both CPU0 and CPU1 L2

► Stash-Only regions can now be defined• Prevents stash data from polluting processor data and vice-

versa• One, two or four “ways” of the cache can be dedicated as

Stash-Only

► Stash Allocate Disable mode added• Allows update of all resident cache lines without allocation

of new lines

e500 Core 0

32 KB D-cachew/Parity

32 KB I-cachew/Parity

Core Complex Bus

CoherencyModule

e500v2 Core

64

128

128

RD1 RD2 WRRD_IN DOUT WR_IN

Stash Only

CPU0 & 1 L2CPU1 L2

Example

Presenter

Presentation Notes

Overview of Features in L2 Cache and SRAM • Supports for 36-bit address space • Write-through, front-side cache supports Valid, locked, and stale states • Two input data buses (64 and 128 bits wide) and one output data bus (128 bits wide) • All accesses are fully pipelined and non-blocking • 512-Kbyte array organized as 2048 eight-way sets of 32-byte cache lines • Eight-way set associativity • I/O devices can store data into the cache in a process called ‘stashing.’ • The L2 cache regions are configurable to allocate instructions, data, or both. • Multiple cache locking methods are supported Individual line locks are set and cleared using e500 cache locking APU instructions • In SRAM mode, regions are created by configuring 1, 2, 4 or 8 ways of each set to be reserved for memory-mapped SRAM. • Regions can reside at any location in the memory map aligned to the SRAM size. • SRAM memory is byte addressable; for accesses of less than a cache line, ECC is updated using read-modify-write transactions. • Also, I/O devices access SRAM regions by marking transactions as snoopable (global).


e500 Internal Busses

►e300 uses internal coherent system bus CSB to interconnect cores and interfaces

►Core Complex Bus (CCB) is evolution of CSB bus• Offers extended addressing and enhanced data flow performance• Used to connect e500 cores and caches together to the rest of device via ECM

module

►e500 Coherency Module (ECM)• Module used to ensure coherency between e500 cache and external interfaces

on the board • Functions include queuing & buffering functions for CCB, arbitration across CCB

and I/O masters, and transaction processingLow-latency path between DDR controllers and cores / caches

►On-Chip Network (OCeaN) Switch Fabric• A multi-port, on-chip, non-blocking crossbar switch fabric designed for high-

speed interconnects2.7GByte/s peak bandwidth per port

Presenter

Presentation Notes

The CSB bus and the newer CCB bus are effectively evolutions of the 60x bus. The ECM bus consists of multiple interfaces to the CCB bus - 64-bit data bus for data from ECM to the cores and L2 cache - A 128-bit bus for sinking data from the L2 cache - A 128-bit from each core


DDR Controller

► QorIQ P1 / P2 platforms offer DDR2 & DDR3 support• No DDR support – change from PowerQUICC II Pro

► QorIQ P1020 / P1011• 32/36-bit data bus support without/with ECC• Support up to 667MHz DDR interface speed.• Support for up to 4Gb devices, x8, x16, x32 configurations• Max memory support of 8GB, with 2 memory banks supported

► QorIQ P2020 / P2010• Support 64 (72-bit w/ECC) and 32 (40-bit w/ECC) data bus configuration.• Support up to 800MHz DDR interface speed.• Support for up to 4Gb devices, x8, x16, x32 configurations• Max memory support 16GB, with 4 memory banks supported

► Other common features• Supports self-refresh mode• Battery backup• Initialization bypass• Chip-select interleaving• Automatic DRAM initialization• Error injection• On die termination ECM

e500 Core

System Bus

DDR2/DDR3, SDRAM

Controller

e500 Core

Presenter

Presentation Notes

PQII Pro supports DDR1 and DDR2 QorIQ supports DDR2 and DDR3 (no support for DDR1) P1 supports 32 bit DDR while the P2 supports 32/64 bit DDR P1 has two memory banks while the P2 has 4 memory banks Each memory bank supports 4 GB RAM.


DDR Controller►DDR 3 – New feature

• Lower power performance – ~25% compared to DDR2 ( Source - JEDEC)• Supply voltage reduced from 1.8V to 1.5V.• Support for “Fly by” routing,

Results in fewer stubs and improved signal integrity for faster clock speeds

• Introduced additional registers for write-levelling control for DDR3• Asynchronous reset pin for cold or warm reset of memories• Separate voltage reference pins for address and data signals for noise reduction• Improved pin-out for signal integrity and reduced skew.• Dynamic ODT for also aids signal integrity

►DDR clocking – ability to asynchronously clock from platform clock supported for higher speed memory devices

Presenter

Presentation Notes

The DDR3 consumes approx. 25% lower power as per the JEDEC standard The supply voltage for DDR3 is 1.5 v while it was 1.8 for DDR2 QorIQ platforms support a separate clock for DDR controller from the main platform clock


Enhanced Three-Speed Ethernet (eTSEC) Controllers

► eTSEC MAC controllers support 10Mbps, 100Mbps, 1Gbps Ethernet /IEEE 802.3 interfaces• Similar in specification to MPC831x & MPC837x devices

► Backwards compatible with TSEC controllers used on MPC834x ► Support following PHY interfaces

• GMII, RGMII, MII, TBI, RMII, RTBI, SGMII, & 8/16-bit FIFO mode• SGMII interfaces share available SERDES lanes

► Advanced functions part of enhanced controller:• TCP/IP acceleration• QOS support for up to 8 queues• MAC address recognitions• CRC generation & checking• Extraction and allocation of data to L2 cache• Remote monitoring statistics support

► IEEE® 1588 Timer support► Interrupt virtualisation added to P1 devices

• eTSEC controllers and interrupts can be grouped, to be assigned to a particular core by software

• Further available information in software section

Presenter

Presentation Notes

The first 5 bullets are the same for the PQII Pro and QorIQ In QorIQ P1 series, we have introduced eTSEC 2.0 which supports virtualization for a multi-core environment I will discuss virtualization later in the presentation


Security► Embedded security block (SEC) used

for off-loading computationally intensive security functions

► Existing SEC architecture migrated to QorIQ P1 / P2 devices.

► SEC block contains specialised execution unit for different encryption algorithms

• PKE – Public Key Encryption Unit• AES – Advanced Encryption Standard Unit• DES – Data Encryption Standard Execution

Unit• CRC – Cyclic Redundancy Check Unit• MDE – Message Digest Execution Unit• RNG – Random Number Generator• SNOW3G & KASUMI - 2G/GSM & 3G

encryption

► Execution unit support varies depending on target silicon application

► Backwards compatible driver support across various SEC engine versions

On-ChipSystem

InterfaceControl PKEU

MDEU RNG

crypto-channel

FIFO

FIFO

CRC

FIFO

DEU AESUXOR

FIFO

FIFO

crypto-channel

crypto-channel

crypto-channel

4 Crypto-channels are initiators and data fetchers for the SEC block

Presenter

Presentation Notes

Security is pretty much the same in the PQII Pro platform All these features are available in both PQII Pro and in QorIQ


SERDES Interfaces

►SERDES interface is consistent with MPC831x / MPC837x devices• Additional SERDES support added to QorIQ P1 & P2 devices• 4 SERDES lanes shared across PCIe, SGMII, & SRIO controllers

►PCI Express v1.0a• Up to x4 lane support on P1 & P2 devices, supports 8Gbps(half-duplex) max data rate -

as per PowerQUICC II Pro• Up to 3 PCIe controllers available on P2 devices, for multiple configurations

►Serial RapidIO – P2 devices• New high-speed switched fabric for embedded systems • Supports multiple lane configurations & speeds (1.25/2.5/3.125Gbauds)• Max data rate of 10Gbps (half-duplex, 4x)

►SGMII – Up to 2 SGMII interfaces with PCIe / SRIO support

Presenter

Presentation Notes

SERDES interface in QorIQ is consistent with MPC831x / MPC837x devices However, Additional SERDES support has been added to QorIQ P1 & P2 devices 4 SERDES lanes shared across PCIe, SGMII, & SRIO controllers. PCIe controller remains the same SRIO is a new introduction in the QorIQ devices It is a New high-speed switched fabric for embedded systems It Supports multiple lane configurations & speeds (1.25/2.5/3.125Gbauds) Max data rate is 10Gbps (half-duplex, 4x)


e500

Root Complex/ Endpoint

e500



PCI Express® Interface► PCI Express 1.0a compatible► Supports x1, x2, and x4 link widths @ 2.5 Gbaud, 2.0 Gb/s

• Auto-detection of number of connected lanes

► Selectable as root complex or endpoint at initialization

► 32- and 64-bit addressing into PCI Express address space

► Root complex inbound support for MSI and INTx

► Endpoint support for outbound MSI ► Reads/writes carried across ports, but not a switch

► 256 byte maximum payload size

► One virtual channel

► Strong and relaxed ordering rules

► 8 non-posted, 6 posted transactions

► 3 inbound + 1 configuration window• Translates upper 52b of PCI addr to upper 24b of local addr• Window sizes of 4 KB to 64 GB• Settings: read/write type, prefetchable, and target• 1 MB Config window maps to CCSR region

► 4 outbound + 1 default window• Translates upper 24b of local addr to upper 52b of PCI addr• Select I/O or memory for reads and writes• Window sizes of 4 KB to 64 GB

Switch

Peripheral Endpoint

Peripheral Endpoint

Peripheral Endpoint

ATMUs

Peripheral Endpoint

Presenter

Presentation Notes

P2020 offers one, two, or three PCI Express interfaces with up to x4 link width. PCI Express is mostly used as an on-the-board connection between the p2020 and an ASIC or other peripheral device. Here, the master-slave hierarchy matches the relationship of the p2020 to the peripheral device. Two ports are useful for the common case that full duplex traffic is being supported on an upstream port and a downstream port. One PCI express port sends traffic to and receives traffic from an ASIC oriented downstream. The other communicates with an ASIC oriented towards a fabric. The PCI Express ports can be configured as either Root Complexes or Endpoints. They support MSI and INTx interrupts to the processor.


P102x / P101x SERDES Configurations

Description Lane 0 Lane 1 Lane 2 Lane 3

One x1 PCI-E Lane (2.5Gbauds) x1 PCI-E

Two x1 PCI-E Lanes (2.5Gbauds) x1 PCI-E x1 PCI-E


One x4 PCI-E lane (2.5bauds) x4 PCI-Express

2 SGMII eTSEC (1.25bauds) SGMII SGMII

x1 PCI-E (2.5Gbauds) & 2 SGMII eTSEC (1.25Gbauds) X1 PCI-E SGMII SGMII

Two x1 PCI-E (2.5Gbauds) & 2 SGMII eTSEC (1.25bauds) x1 PCI-E x1 PCI-E SGMII SGMII

One x2 PCI-E (2.5Gbauds) & 2 SGMII eTSEC (1.25bauds) x2 PCI-E SGMII SGMII

► Speeds specified for each lane in one direction – Half-duplex

Presenter

Presentation Notes

This slide shows how the SERDES interface is used in P1020 in various configurations For example, (last line) One cross two PCI-E lanes (Lane 0 and Lane 1) along with two SGMII ports (on Lane 2 and Lane 3)


P2020 / P2010 SERDES Configurations

Description Lane 0 Lane 1 Lane 2 Lane 3


Two x1 PCI-E & One x2 PCI-E (2.5Gbauds) x1 PCI-E x1 PCI-E x2 PCI-E

Two x2 PCI-E lanes (2.5Gbauds) x2 PCI-E x2 PCI-E

One x4 PCI-E lane (2.5Gbauds) x4 PCI-Express

One 4x SRIO interface (1.25 /2.5 /3.125Gbauds) 4x SRIO

Two 1x SRIO interfaces (1.25 /2.5 /3.125Gbauds) 1x SRIO 1x SRIO

Two 1x SRIO (1.25 / 2.5Gbauds) & 2 SGMII eTSEC (1.25Gbauds) 1x SRIO 1x SRIO SGMII SGMII

x1 PCI-E (2.5Gbauds), 1x SRIO (2.5Gbps), & 2 SGMII eTSEC (1.25Gbauds) x1 PCI-E 1x SRIO SGMII SGMII

Two x1 PCI-E (2.5Gbps) & 2 SGMII eTSEC (1.25Gbauds) x1 PCI-E x1 PCI-E SGMII SGMII

Two x1 PCI-E (2.5Gbps) & 2 SGMII eTSEC (1.25Gbauds) x2 PCI-E SGMII SGMII

► Speeds specified for each lane in one direction – Half-duplex

Presenter

Presentation Notes

This is similar to the previous slide. This slide shows how the SERDES interface is used in P2020 in various configurations


Enhanced Secure Digital Host Controller (eSDHC)

►Memory card interface available on QorIQ Platforms

• Similar in specification to the eSDHC on MPC837x

►Provides high-speed, flexible data storage capability to a system

►Designed to work with various SD & MMC card formats

• SD, SDHC, miniSD, SD Combo, MMC, MMCplus & RS-MMC cards

►Supports capacities of up to 32GB, with different speeds

►Boot interface support – new feature

• On-chip ROM used to load device driver prior to loading of boot data from the card.

CMD/Data

Channel TX/RX Handler

CMD

DAT4

SD_CLK

DAT3

DAT2

DAT1

DAT0

SD_CD SD_WP

Status Register &Interrupt Controller

Embedded DMA

Clock Controller &

Reset Manager

SD Bus Monitor & Gating

Controller & Buffer RAM

Register Bank

Logic Control

CRC

CMD Channel State

Machine

Logic Control

CRC

Data Channel State

Machine

System Interface

eSDHCController

CMD

DAT4

SD_CLK

DAT3

DAT2

DAT1

DAT0

SD_CD SD_WP

Logic Control

CRC

CMD Channel State

Machine

Logic Control

CRC

Data Channel State

Machine

eSDHCController

CMD/Data

Channel TX/RX Handler

Status Register &Interrupt Controller

Embedded DMA

Clock Controller &

Reset Manager

SD Bus Monitor & Gating

Controller & Buffer RAM

Register Bank

Logic Control

CRC

CMD Channel State

Machine

Logic Control

CRC

Data Channel State

Machine

System Interface

Presenter

Presentation Notes

eSDHC is present in 837x devices A new feature introduced in the QorIQ P1/P2 is the ability to boot from eSDHC interface. Everything else is the same.


Additional Features

►Programmable Interrupt Controller (PIC) • Interrupts added between cores and for SRIO• Interrupts based on OpenPIC architecture• 16 interrupt priority levels (15 is highest)

Priority level is the reversed from PowerQUICC II Pro• Critical interrupts

►Performance monitoring • Core performance monitoring available from PowerQUICC II Pro• Device performance monitoring available as well on QorIQ /

PowerQUICC III devices • Debug and monitor events on DDR, DMA, ECM bus, PCIe & other

interfaces

Presenter

Presentation Notes

These features have been improved in the QorIQ platform PIC – It is now based on OpenPIC architecture where we can route different interrupts to different cores PM – used to monitor performance of the core. In QorIQ can monitor of the complete device including that of the core


Additional Interfaces (Continue)

►DMA Controller• 4 channel DMA controller located on OCeaN switched fabric • Used for internal data movement and external movement to/from the device• Accessible by all cores, all internal interfaces and external masters • 2 DMA controllers available on P2020 for additional I/O performance

►USB • High-speed USB 2.0 interface, with host or device support

USB on-the-go capability supported as well.• Supports ULPI interface to an external PHY

►eSPI controller• Interface consistent with PowerQUICC II Pro device family

►Local Bus – Enhanced local bus controller• Supports 8-bit / 16-bit interface with NAND / NOR Flash support

Presenter

Presentation Notes

These interfaces exist in PQII Pro. However, there are improvements in DMA controller and the eSPI controller DMA – used to have only one controller, now in P2020 we have two. DMA signal comes out of the SoC to support DMA transactions with external interfaces. In PQII Pro the signal does not come out of the SoC. eSPI – The QorIQ device can boot from the eSPI


Hardware Design Considerations


Hardware Design Electrical Specifications

Description Symbols MPC831x MPC837x QorIQ P1 QorIQ P2

Core VDD 1.0V 1.0V 0.95V 1.05V

PLL supply AVDD 1.0V 1.0V 0.95V 1.05V

SERDES Core Supply SVDD / XCOREVDD

1.0V 1.0V / 1.05V*** 0.95V 1.05V

SERDES pad supply XVDD / XPADVDD

1.0V 1.0V / 1.05V*** 0.95V 1.05V

DDR2 / DDR3 I/O GVDD 1.8V / - 1.8V / - 1.8V / 1.5V 1.8V / 1.5V

Ethernet I/O LVDD 3.3V / 2.5V

3.3V / 2.5V 3.3V / 2.5V 3.3V / 2.5V

DUART, system control, I2C, GPIO, JTAG

NVDD /OVDD 3.3V 3.3V 3.3V 3.3V

Local Bus NVDD / BVDD 3.3V 3.3V / 2.5V /1.8V

3.3V / 2.5V /1.8V

3.3V / 2.5V /1.8V

USB, eSPI**, eSDHC* USB_VDD/ CVDD

3.3V 3.3V / 2.5V /1.8V

3.3V / 2.5V /1.8V

3.3V / 2.5V /1.8V

* eSDHC not available on MPC831x** SPI interface shares same supply as I2C & JTAG on MPC831x / MPC837x*** SERDES supply specs for 600MHz / 800MHz devices respectively

Presenter

Presentation Notes

The above slide compares the power specifications for P1 / P2 against the MPC831x and MPC837x. Device power structure for P1 / P2 is consistent with PowerQUICC II Pro, there is a Core supply (VDD). Each PLL has its own supply to ensure stability. The PLL supply is a filtered version of the core supply. There are separate supplies for the SerDes lanes Main difference is with core voltage and the supplies which are derived from the core (PLL supplies and SerDes). The P2 runs at 1.05V Designers can minimise re-design effort my using supplies that are voltage adjustable between 0.9V – 1.1V.


Power Sequencing

►Power sequencing is different from PowerQUICC II Pro

►P1/P2 devices requires power rails to be applied in a specific sequence in order to ensure proper device operation. These requirements are as follows for power-up:

• VDD, AVDD_n, BVDD, LVDD, OVDD,CVDD, XVDD_SRDS and XVDD_SRDS

• GVDD

• NOTE: Items on the same line have no ordering requirement with respect to one another.

• NOTE: If any of the I/O power supplies ramp prior to VDD core supplies, the associated I/O supply may drive a logic one or zero during power- up thus causing excessive current to be drawn by the device.

►All supplies must be at their stable values within 50 ms.

Presenter

Presentation Notes

Major area of change from the PowerQUICC II Pro. The PowerQUICC II Pro devices require VDD and AVDD supplies to come up before I/O voltages. This requirement also appears on P1 / P2 QorIQ. Further on P1 / P2, the DDR supply GVDD must come up after the other supplies. This is to ensure that the device is fully up and running before the DDR initialisation state machine starts.


PLL Filter Circuit

►Provide independent filter circuit to each of the AVDD pins• AVDD_PLAT, AVDD_CORE[0:1], AVDD_DDR, and AVDD_LBIU, respectively• Independent circuits reduces chance of noise injection between PLLs

• Circuit will filter noise in 500 KHz to 10 MHz range• Use surface mount capacitors with a low Effective Series Inductance (ESL)• Place as close to AVDD as possible to reduce noise

►Filter specifications changed from PowerQUICC II Pro family

VDD AVDD

R

C1 C2

GNDLow ESL surface mount capacitors

R = 5 W ± 5% C1 = 10mF ± 10%, 0603, X5R, with ESL <= 0.5

nH C2 = 1.0 mF ± 10%, 0402, X5R, with ESL <=

0.5 nH

Presenter

Presentation Notes

Each PLL has its own supply for stability. Each supply is a filtered version of the VDD core supply. The filter configuration are similar to the configurations used on the PowerQUICC II Pro, however designers are advised to check the recommended resistor and capacitor values from the device HW specifications.


SerDes: PLL Filter Circuit

►AVDD_SRDS should be a filtered version of SVDD

►The AVDD_SRDS signal provides power for the analog portions of the SerDes PLL. To ensure stability of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in following figure. For maximum effectiveness, the filter circuit is placed as closely as possible to the AVDD_SRDS ball to ensure it filters out as much noise as possible. The ground connection should be near the AVDD_SRDS ball.

►All traces should be kept short, wide, and direct.


SERDES: Power Supply

►There are three different supplies used for SERDES block, consistent with PowerQUICC II Pro family

• SVDD: Core power supply for SERDES transceivers• XVDD: Pad power supply for SERDES transceivers• AVDD_SRDS: SERDES PLL supply – NEW

AVDD_SRDS should be a filtered version of SVDDThe AVDD_SRDS signal provides power for the analog portions of the SerDes PLL. To ensure stability of the internal clock. For maximum effectiveness, the filter circuit is placed as closely as possible to the AVDD_SRDS ball. The ground connection should be near the AVDD_SRDS ball.

►All traces should be kept short, wide, and direct.►Additional SERDES power supply decoupling requirements for QorIQ

devices

Presenter

Presentation Notes

NOTE: Must supply power to all SERDES I/F whether used or not. The following slide summarises the power requirements for the SerDes interface. The P1 / P2 QorIQ have tighter SerDes power requirements compared to the PowerQUICC II Pro. There are 3 supplies for the SerDes block, SVDD, XVDD and AVDD_SRDS. The latter is a new addition. AVDD is for the analog portion of the SerDes PLL circuitry. The supply is derived from a filtered version of SVDD. The filter should be placed as close possible to the device pin.


SERDES: Power Decoupling (SVDD and XVDD) - New

►Additional SERDES power supply decoupling recommendations (taken from HW specifications)

• The SERDES block requires a clean, tightly regulated source of power (SVDD and XVDD) to ensure low jitter on transmit and reliable recovery of data in the receiver. Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance.

• First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible to the supply balls of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the device as close to the supply and ground connections as possible.

• Second, there should be a 1-µF ceramic chip capacitor on each side of the device. This should be done for all SERDES supplies.

• Third, between the device and any SERDES voltage regulator there should be a 10-µF, low equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all SERDES supplies (XVDD and SVDD).

Presenter

Presentation Notes

The following slide outlines some further technical requirements for the SerDes power supply. Highlight the following key items: - Need clean tightly regulated power supply with low jitter. - Additional decoupling required on the supply and the device pins to ensure stability.


POR Configuration Inputs► P1/P2 platforms have power on reset (POR) signals used for device configuration

• Signals are muxed with existing I/O pins

► The settings for the following POR pins will determine CPU boot enable, PLL ratios and boot device selection:

• LA[29:31] - cfg_sys_pll[0:2]• LBCTL, LALE, LGPL2 - cfg_core0_pll[0:2]• LWE0, UART_SOUT1, READY_P1 - cfg_core1_pll[0:2]• TSEC1_TXD[6:4],TSEC1_TX_ER - cfg_rom_loc[0:3]• LA[27] - cfg_cpu0_boot• LA[16] - cfg_cpu1_boot

• LGPL3, LGPL5 - cfg_boot_seq[0:1]

► Further configuration signals may be used in the future to control functionality. It is advised that boards are built with the ability to pull-up or pull-down these pins.

• LA[20] - cfg_eng_use[00] • LA[21] - cfg_eng_use[01]• LA[22] -cfg_eng_use[02]• UART_SOUT[00]- cfg_eng_use[03]• TRIG_OUT -cfg_eng_use[04]• MSRCID[01] -cfg_eng_use[05]• MSRCID[04]- cfg_eng_use[06]• DMA1_DDONE[00]- cfg_eng_use[07]

► POR signals are sampled on HRESET negation

Presenter

Presentation Notes

The P1 / P2 devices configuration is carried out by sampling a series of signals on the device during HRESET# assertion The signals are taken from existing signals on the device and hence are internally multiplexed in the device. After HRESET, the signals revert back to their normal operation. The signals are generally configured through internal pull-ups, or external pull-downs / pull-ups on the device. Above is a list of the signals on the P1020/21 and P2020/10. Designers need to be aware of the dual function of these signals and accommodate these functions accordingly in their board layout.


►The following pins must NOT be pulled down during power-on reset, otherwise it may trigger the internal test mode:

• DMA1_DACK[00]

• USB1_STP

• HRESET_REQ

• MSRCID[2:3]

• MDVAL

• ASLEEP

POR Configuration Pins Termination Requirements

Presenter

Presentation Notes

Please be careful while handling these pins during reset as the SoC will enter in test mode if they are low during POR


DDR Interface Design

►DDR2 interface requirements consistent with PowerQUICC II Pro family

►Refer to Application Note AN2910:• “Hardware and Layout Design Considerations for DDR2 SDRAM Memory

Interfaces”

►DDR3 guidelines available from AN108• “Designing for DDR3 Memory on Freescale Microprocessors”

►DDRCLK input• Input is only required when the DDR controller is running in asynchronous mode.• Not required if DDR controller is selected to work in synchronous mode, via

POR setting cfg_ddr_pll[0:2]=111. • It is recommended to tie it off to GND when DDR controller is running in

synchronous mode.• DDR3 is only supported in asynchronous mode

Presenter

Presentation Notes

For DDR2 interface and specifications are the same as those for the PowerQUICC II Pro. Designers are recommended to use app note AN2910, which applies to all DDR2 based Power architecture devices. For DDR3 interface design, use the app note AN108. The app note lists the new features of DDR3 and how they can be accommodated on supported Power architecture products The DDR CLK input is a new feature which has been added to newer devices. The input is only required if the DDR interface is to be run in asynchronous mode. Designers need to use a suitable clock based on DDR_CLK specs. Highlight DDR3 is only supported in asynchronous mode due to the fact that min freq of DDR3 is 333MHz, which produces a data rate of 667Mbps, which is greater than the CCB freq.


►Addition termination requirements for eTSECs compared to PowerQUICC II Pro

• When eTSEC1 and eTSEC2 are used as parallel interfaces, pins TSEC1_TX_EN and TSEC2_TX_EN requires an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively driven.

• TSEC2_TXD[01] is used as cfg_dram_type. It must be valid at power-up, even before HRESET assertion.

►Unused eTSEC pin terminationFor I/Os, tie signals high or low through a resistor. Recommended resistor values are 2–10K ohm. For inputs, tie signals to their inactive state through a resistor; clock inputs may be tied high or low. Recommended resistor values are 2–10 K ohm.

eTSEC Pin Termination

Presenter

Presentation Notes

- Highlight need for 4.7K ohm pull up on TSEC_TX_EN to prevent the PHY from seeing false data - TSEC signals also used as PORESET registers and used to define PHY configuration of TSEC, eg GMII, MII RGMII, RTBI etc.


Local Bus Termination

►Termination is not needed on output signals.

►For bidirectional I/Os, tie signals high or low though a resistor. Recommended resistor values are 2–10 K ohm.

►For inputs, tie signals to their inactive state through a resistor. Recommended resistor values are 2–10 K ohm.

Presenter

Presentation Notes

Designer must ensure that all input signals of eLBC are in a valid state. They may be pulled high or low depending on the requirement.


Suggestion on Power Supply and Power Supply Test Point

► Following applies for both PowerQUICC II Pro and QorIQ devices

► For prototype board, suggest isolating power supplies and have independent controls over:• VDD, AVDDs ( Core and PLLs)• SVDD (SerDes core) • XVDD (SerDes pad)• OVDD (DUART, I2C,JTAG etc...)• LVDD (eTSECs)• GVDD (DDR)• BVDD (local bus)• CVDD (USB,eSPI,eSDHC)

► The voltage range should be adjustable. • Particularly for VDD, AVDDs, SVDD and XVDD, they should be adjustable at least between 1.0V to 1.1 V

nominal. Also allows for easier migration between device families • Have test points near processor for these supplies

► QorIQ P1 /P2 devices have a voltage select configuration pins for Local bus, Ethernet & USB I/O• Incorrect voltage selection of L/B/CVDD_VSEL can lead to irreversible device damage.

► Have visibility of all processor BGA pins on the back of card.

Presenter

Presentation Notes

Having separate power supplies and ability to fine tune them on board helps. For example Vdd is .95V in P1020. You may need to fine tune variable power regulators to adjust the voltages. Moreover if PCB has all BGA pins exposed, changes/tests can performed directly on board.


Debug

► QorIQ P1 / P2 devices have specific debug assist pins• TRIG_OUT/READY (This helps to verify the end of the reset sequence)• TRIG_IN (Trigger in to trigger the watchpoint and trace buffers. • MSRCID [0:4] & MDVAL – memory debug signals

► General list of signals to have accessible for analysis on all devices• DDR2/3 – address, data, control & clock signals• Local bus – address, data, control & clock signals• Machine check & interrupt signals• SERDES - Transmission lanes & reference clock signals• HRESET# / HRESET_B• SD_PLL_TPA, & SD_PLL_TPD (SerDes Analog and Digital PLL lock indication)

► Debug signals specific to the MPC831x / MPC837x• CFG_RESET[0:3] source signals• SRESET_B• PORESET_B

►Debug signals specific to the P1 / P2 platforms• HRESET_REQ (This helps to verify proper boot sequencer functions and reset requests)• ASLEEP (This helps to verify the end of the reset sequence)• SYSCLK (To verify input clock at the device pin) • CLK_OUT (This helps to verify the CCB clock)• DDRCLK ( To verify DDR Clk when in asynchronous mode)• CKSTP_OUT[0:1] (e500 checkstop indication)• Debug Assist pins

Presenter

Presentation Notes

It’s always useful to have some hardware debug capabilities on the board . The slide details the signals that a board designer should attach to some header or test points for use when debugging the board on bring-up. The slide details signals for PowerQUICC II Pro and P1 / P2 QorIQ devices.


Reset Configuration, Clocking and Initialisation


POR Configuration

►QorIQ P1 / P2 devices use power-on reset (POR) configuration pins, which are sampled during the assertion of HRESET_B.

• PowerQUICC II Pro devices load reset configuration words to initialize various device functions

►All POR configuration pins are typically multiplexed with the output signals

►All POR configuration pins have internal pull-up resistor (~20 KΩ) and those resistors are activated only during the POR configuration

• POR pins can be pulled high or low by external resistors for configuration.• Signals can also be driven by CPLD / FPGA device

►During HRESET, all other signal drivers connected to these POR configuration signals must be in the high-impedance state

• Reason: If other devices also drive POR pin during HRESET, device may sample the wrong POR configuration information from the POR pin.

Presenter

Presentation Notes

- The POR configuration is a new feature on P1 / P2 QorIQ compared to PowerQUICC II Pro. The PQII Pro is configured by loading reset configuration words via the I2C interface upon reset. Due to the fact that the P1 / P2 QorIQ devices are more complex devices which require more configuration features, a faster approach of sampling values on certain signals upon HRESET# assertion has been devised. - Features configured include clock PLL register settings, boot location, I/O config and eTSEC configuration. - The signals are taken from existing signals on the device and hence are internally multiplexed in the device. After HRESET, the signals revert back to their normal operation. Note any external drivers to these signals must be in a high impedance state during the power up configuration procedure. The signals are generally configured through internal pull-ups, or external pull-downs / pull-ups on the device. However for a complex design it can be advisable to use an active device such as a microcontroller or CPLD for adjusting signal timings and debug.


Power-On Reset

►Power-On reset sequence is significantly different from PowerQUICC II Pro family

• HRESET# – Now input only and replaces PORESET# input• HRESET_REQ# – Output, used to request reset • SRESET# – Input only• READY_P0 / TRIG_OUT – Core 0 ready output / external trigger output • READY_P1 – Core 1 ready output (if available)

►Signals no longer available• CFG_RESET_SOURCE[0:3] – Used to load configuration words. Function

replaced by POR configuration pins• CFG_CLKIN_DIV# – Clock division selection is carried out by POR PLL config

pins

Presenter

Presentation Notes

The following slide details the change in the reset signals on the P1 / P2 compared to the PowerQUICC II Pro. Change to HRESET# and PORESET# request signals. SRESET# is an input only signal. On MPC837x devices this was a input and output Removal of CFG_RESET_SOURCE and CFG_CLKIN_DIV# Addition of ready output to show when each core is ready


Power-On Reset Sequence

Stable PLL configuration input

POR Configuration input

Stable SYSCLK signal

Presenter

Presentation Notes

The POR sequence for the P2020 is as follows: Power is applied to P2020 Integrated Processor per Hardware Specifications. The system asserts HRESET and TRESET, causing all registers to be initialized to their default states The system applies a stable SYSCLK signal and stable PLL configuration inputs, and the device PLL begins locking to SYSCLK. The ASLEEP signal negates synchronized to a rising edge of SYSCLK, indicating the ready state of the system.


Clocking Quick Reference

Functional Block Clocked by… Restrictions

Local Bus CCB_clk / [ 4, 8, 16] LBIU PLL bypass mode is recommended when LBIU frequency is at or below 83 MHz; When LBIU operates above 83 MHz, LBIU PLL is recommended to be enabled

PCI Express® and Serial RapidIO® digital logic

CCB_clk/2

SerDes for PCIe, sRIO and SGMII

SD_REF_CLK/SD_REF_CLK_B

100 MHz ref clk for PCIe 1.25 Gbps and 2.5 Gbps100 MHz ref clk for SRIO 1.25 Gbps and 2.5 Gbps125 MHz ref clk for SRIO 3.125 Gbps100 MHz ref clk for SGMII 1.25 Gbps For PCIe, CCB_clk > (527 MHz x PCI Express link width) / 8For sRIO, CCB_clk > 2×(0.80)×(Serial RapidIO interface frequency)×(Serial RapidIO link width) /64

I2C CCB_clk / (2* I2CFDR[FDR]ratio)

Real Time Clock (RTC) External source or CCB_clk

The minimum pulse width of the RTC signal should be greater than 2x the period of the CCB clock; The minimum RTC frequency is zero.

Presenter

Presentation Notes

Slide details the clocking configuration for each of the clocks featured on the P1 / P2. Local bus has range of speed levels based on the speed of the CCB platform bus clock. PCI-E and SRIO Digital Logic – This is the clock used to clock the actual SRIO and PCI-E controllers. The actual SerDes lanes are clocked from SD_REF_CLK Real time clock input – This clock is used as a time watch functions.


Clocking Quick Reference (continued)

Functional Block Clocked by… Restrictions

e500 core and L1 cache

Core-complex-bus clock (CCB_clk) times a multiplier

533 MHz=< core freq =<1.2 GHz

L2 cache and ECM CCB_clk 266 MHz=< CCB_clk (platform clock) =<600 MHz

SYSCLK External clock source SYSCLK 66.66 MHz=min, & 100 MHz=max

DDR CCB_clk / 2 400 MHz=< DDR data rate =<800 MHz;For DDR3: the minimum data rate is 667 MHzNote:For asynchronous operation the DDR clock speed is derived from the DDR_CLK input

eTSECs eTSEC logic layer is clocked by CCB_clk /2;MAC layer is clocked by 125 MHz from PHY or External;

EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation.EC_GTX_CLK125 duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cyclegenerated by the eTSEC GTX_CLK.

eTSEC FIFO mode TSECn_RX_CLK and TSECn_TX_CLK

For FIFO GMII mode: FIFO TX/RX clock frequency <= platform clock frequency / 4.2For FIFO encoded mode: FIFO TX/RX clock frequency <= platform clock frequency / 3.2

Presenter

Presentation Notes

The e500 core and cache are clocked by the core frequency as are the CCB clock The SYSCLK is the input that the user supplies to the device. This clock is the one used to define the CCB, and core clocks on the device. The SYSCLK is fed into a series of PLLs which are used to provide the required frequencies. The PLL configuration is carried out by the values of the POR configuration signals DDR_CLK – For synchronous operation the DDR_CLK is half the freq of the platform clock. For asynchronous operation the DDR clock speed is derived from the DDR_CLK input


e500 Clock Control Architecture and Low Power StatesProcessor

ClocksSnoops

Respond toInterrupts

Respond toComments

On Yes Yes All units operating normally.Dynamic Power Management (DPM) may be enabled

On Yes Yes The core has halted instruction fetching, but all other functional blocks in the core and device are running.

Off except time base

No Yes The core has halted instruction fetching.Snooping of the L1 caches is disabled.All of the core’s functional units except the timer are shut down. All functional blocks in the device are running.

Off No Yes Instruction fetching is halted.snooping of L1 caches is disabled.Most functional blocks are shut down in both the e500 cores and the system logic, except to the interrupt controller (PIC) unit

Run

Doze

Nap

Sleep

Presenter

Presentation Notes

Doze: -The core has halted instruction fetching, but all other functional blocks in the core and device are running. Nap: -The core has halted instruction fetching. snooping of the L1 caches is disabled. All of the core’s functional units except the timer facilities are shut down. -All functional blocks in the device are running. Sleep: -Instruction fetching is halted. -snooping of L1 caches is disabled. -Most functional blocks are shut down in both the e500 cores and the system logic.


Boot Modes

►Possible Boot interfaces• Local bus • DDR2 / DDR3 memory controller• PCI Express interface• Serial RapidIO (P2020)• eSPI interface• eSDHC interface

►Boot sequencer – Migrated from PowerQUICC II Pro

►Boot hold-off – registers used to suspend core booting• Used when booting two cores. CPU0 boots while CPU1 waits• Used when external master boots device over eg. RapidIO or PCIe

►Reset – e500 begins execution from fixed location of 0xFFFF_FFFC

New boot interfaces supported on P1 & P2

Presenter

Presentation Notes

- Booting options Boot sequencer is via I2C interface. The I2C interface can get access to all the registers in the CCSR bar config space Boot hold-off mode is a new feature which can be used to prevent the core from booting straight away from power-up. The feature allows an external master to configure the DDR, MMU, cache and other features on the core before it boots up. It is useful when the core is being configured by an external master, this can be another CPU on the device, or it can be connected to the device via SRIO or PCIe. The external master informs the core when it has completed the boot sequence by setting a bit in the device config space.


Runtime Power Management

►Dynamic power management• Withholds clocks to e500’s unused execution units, MMUs, caches, and other

blocks without performance impact►Programmable power mode

• Programmable transition (per core) between e500 modes: full power, doze, nap, and sleep

• Three external pins track power mode of cores• POWMGTCR puts device into sleep or doze

►Memory controller• Dynamic power management

Doesn’t clock DRAM when no transactions• Sleep/doze mode. DRAM put into self-refresh mode, controller goes into sleep

mode► I/O power management

• eTSEC’s Magic Packet support: specially defined Ethernet packet received on eTSEC wakes chip from sleep

Presenter

Presentation Notes

No information on the PCI Express power states: D0 – D3, L0 – L3


Configuration Power Management

►Multiplier flexibility to optimize core, internal bus, and DDR performance and power

►Disable unused blocks through DEVDISR register• e500 (each individually)• PCI Express (all three individually)• Local bus• Security block• USB• eSDHC• SPI• DMAs (both individually)• eTSECs (each individually)• DDR controller• I2C (both together)• DUART• Timers (both sets individually)


Software Design Considerations


Memory Map

►e500v2 based QorIQ devices deploy a 36-bit local address space• PowerQUICC II Pro, e300 based, devices deploy a 32-bit local addressing scheme

►Local Access Windows (LAWs)• Support multiple access windows like e300 devices• Maximum window size increased from 2GBytes to 32GBytes

►ATMU – Address Translation & Mapping Unit • Used for translating between local & external address spaces• Further ATMUs added on QorIQ platforms for additional PCIe controllers & SRIO

►CCSR – Command, Configuration & Status Registers• Replacement to IMMR space registers on PowerQUICC II Pro • All registers contained within a 1MByte address region• Offers additional flexibility – can be relocated, and provides easier external access

Presenter

Presentation Notes

E500 v2 has 36 bit address as opposed to 32 bit bus of e300. Programmer should configure LAW windows to ensure the address thrown at system bus is directed to right interface. - The 36-bit real address is equal to the 32-bit effective address, with the 4 MSbits of the 36-bit real address equal to 0. CCSR is analog of IMMR used in 83xx devices. All the registers of SoC are mapped in 1MB window of CCSRBAR


eTSEC Updates - Memory mapping

►New eTSEC features introduced to P1 devices

• P2 and earlier devices have eTSEC 1.x• P1 devices have eTSEC 2.x

►eTSEC 1.x has one common 4k block of common registers which can be used by any core

►In eTSEC 2.x, the Ethernet traffic can be categorized in two groups

►Separate 4k block of status & control registers are for each groups. These 4k blocks can be associated to each of the cores

►Another 4k block, common to both the core, is available for management

4k Block

Group 0

4k Block

for MDIO

4k Block

Group 1

Core 0Core 1eT

SE

C 2

.x

P1020

4k Block

Core 0

Core 1

eTS

EC

1.x

P2020

Presenter

Presentation Notes

eTSEC 2.0 has been introduced in P1020. Ethernet traffic can be categorized in two groups. Each of these groups can be associated to individual cores. eTSEC provides set of 4k registers for each ggroup. Additionally there is another set of 4k registers which are common to both the groups. These are used ethernet management.


eTSEC Updates - Interrupt steering

Interrupt routing in eTSEC 2.x

► In eTSEC 1.x, all the Rx and Tx interrupts are routed to any one core through PIC

► In eTSEC 2.x, the hardware queues can be mapped to any of the two groups.

► The interrupt controller gets two Rx and two Tx interrupts from each eTSECs.

► These interrupts can be routed to either of the cores.

PICRing 1Ring 2Ring 3Ring 4Ring 5Ring 6Ring 7Ring 8

Group 0

Group 1

eTSEC1

Group 0

Group 1

eTSEC1

Core 0

Core 1

Ring 1Ring 2Ring 3Ring 4Ring 5Ring 6Ring 7Ring 8

PICCore 0

Core 1eTSEC 2

eTSEC 1

Interrupt routing in eTSEC 1.x P2020

P1020

Presenter

Presentation Notes

One of the major change in eTSEC2.x is steering of interrupts. This has been specially designed for multicore environment. In earlier versions of eTSEC, all the Rx or TX interrupts of an interrupts can be routed to one of the cores. In the new version, programmer can define up to 8 rings which can be grouped in 2 groups. Rx and TX interrupts of these groups can be independently routed to any of the cores. All interrupt lines are operated either in legacy mode or multi-group mode


e300 to e500v2 MigrationPrivileges: Programming Model

►Power Architecture cores operate one of the following two modes:

• Supervisor Mode: This is the highest privilege mode where entire programming model is available for the software. Operating systems and boot loaders operate on this mode.

• User Mode: Resources, which can affect whole system, are not available in this mode. User-level applications or non-trustable programs operate on this mode.

Presenter

Presentation Notes

Supervisor Mode: This is the highest privilege available for the software. And is typically the OS and boot loaders operate on this mode. User Mode: Only for user – level applications.


e300 to e500v2 Migration User Level Registers

0 63FPR0FPR1------

FPR30FPR31

GPR0GPR1------

GPR30GPR31

0 31 32 63

CR

CTR

LR

XER

TBL

TBU

FPSCR

ATBL

ATBU

SPEFSCR

ACC

L1CFG0

L1CFG1

PMGC0

PMC0PMC1PMC2PMC3

PMLCa0PMLCa1PMLCa2PMLCa3

PMLCb0PMLCb1PMLCb2PMLCb3

USPRG0

SPRG3SPRG4SPRG5SPRG6SPRG7

BBEAR

BBTAR

e300e500v2

FPU Registers

GeneralPurposeRegisters

InstructionAccessibleRegisters

Time-BaseRegisters(Read Only)

PerformanceMonitorRegisters(Read Only)

SPE Register

User General SPR

General SPRs (Read Only)

L1 Cache (Read Only)

Branch Buffer Registers

Presenter

Presentation Notes

If a user-level application binary for of e300 doesn’t use floating point unit, it can be directly run on e500. Floating point operations are done by an APU named SPE. E500 also gives access to few additional read only registers to a user level program like Cache related registers, few SPRs.. Alternate time base register is available in e500 . It is recommended to recompile e300 based user level application to run on e500. User should use libraries available for floating point operations.


e300 to e500v2 Migration Supervisor Level Registers

TBL

TBU

DEC

DECAR

L1CSR0

L1CSR1

PMGC0

PMC0PMC1PMC2PMC3

PMLCa0PMLCa1PMLCa2PMLCa3

PMLCb0PMLCb1PMLCb2PMLCb3

SPRG0SPRG1

----SPRG7

BBEAR

BBTAR

e300e500v2

Time-BaseRegisters

PerformanceMonitorRegisters

General SPRs

L1 Cache

Branch Buffer Registers

IBAT0UIBAT0L

* * *IBAT7UIBAT7LDBAT0UDBAT0L

* * *DBAT7UDBAT7L

DMISSIMISS

HASH1HASH2

DCMP

SR0SR1* * *

SR15

SDR1

ICMP

RPA

PID0PID1PID2

MMUCSR0

MAS0MAS1

----MAS7

MMUCFGTLB0CFGTLB1CFG

DARDSISR

MCSR

SRR0SRR1

CSRR0CSSR1

MCSRR0MCSSR1

ESRDEARIVPR

IVOR0IVOR1

* * *IVOR15IVOR32

* * *IVOR35MCAR

MCARU

IBCRDBCR

DABRDABR2IABRIABR2

DebugTCR

TSR

Interrupt Registers

MMUMMU

DBCR0DBCR1DBCR2

DBSR

IAC1IAC2DAC1DAC2

Debug

MSRPVRSVR

PIR

MiscellaneousHID0HID1

BUCSR

Presenter

Presentation Notes

There are many differences in supervisor level registers though. As can be seen in the figure, MMU, Interrupt handing are different. We’ll talk about in later slides.


e300 to e500v2 Migration Exceptions

► While exceptions had fixed vector addresses in e300, they are programmable in e500v2 except reset vector

► In e300, reset vectors at 0x0000_0100 while it vectors at 0xFFFF_FFFC in e500v2

► e500v2 has a new category of exception – Machine check

Presenter

Presentation Notes

Except reset vector, vectors of all other exception are programmable in e500. In e500 reset vectors to ffff_fffc. A new category of interrupt has been introduced called Machine Check. This gives flexibility to nest machine check interrupts over other interrupts as shown in next slide.


e300 to e500v2 Migration Exception Handling

Main

Program

Interrupt Service Routine

Critical Interrupt Service Routine

Machine Check

Interrupt Service Routine

PC → SRR0MSR → SRR1

PC → CSRR0MSR → CSRR1

PC → MCSRR0MSR → MCSRR1

PC ← SRR0MSR ← SRR1

PC ← CSRR0

MSR ← CSRR1

PC ← MCSRR0

MSR ← MCSRR1

e300 e500v2

A new category of Machine check interrupt has been added in e500v2

Presenter

Presentation Notes

New registers MCSRR0 & MCSRR1 are introduced. If an event of machine check occurs while any other interrupt is being handled, PowerPC uses these new registers to vector to new location for Machine Check ISR.


e300 to e500v2 MigrationMMU

► e300 supports BAT and page translations while e500v2 has 512 entries of fixed 4k pages and 16 entry variable size pages

► e300 endian mode is controlled on system basis while e500v2 allows endian confirguration per page basis

► Unlike e300, MMU is always on in e500v2

► After reset, a default entry in MMU maps logical address 0xffff_f000 to physical address 0xffff_f000

Presenter

Presentation Notes

BAT is not supported in e500. It supports only TLBs. There are 512 fixed size entries available along with 16 variable size entries. Programmer can configure endianness of every page. MMU cannot be switched off in e500. On reset, MMU gives a default fixed page entry with one-to-one mapping to address ffff_f000.


e300 to e500v2 Migration MMU Translation Difference

Effective Address

Segment descriptor

Virtual Address

Physical Address Physical Address Physical Address

Segment descriptor

e300 Translations

Match with BAT registers

e500v2 Translations

Real addressing mode

Block address translation

Page address translation

Address Space | PID | byte address

Presenter

Presentation Notes

While in e300, a logical address may become physical address in MMU is turned off ….. or .. Translation can be done using BAT tables .. Or ….. Logical address may search of table lookup entries to obtain physical address………… In e500 every address is translated using TLBs.


Cache

► e300 has 16/32k L1 I/D cache while e500v2 has 32k L1 I/D cache and 256k L2 cache

► e300 supports way-locking while e500v2 supports line-locking

► e500v2 has non-blocking caches (support hit under misses and miss under misses)

► e500v2 supports stashing on L2

Presenter

Presentation Notes

Bigger L1 cache with 256k of L2 front-side cache makes memory access faster. in e500 , it is possible to lock a line of cache instead of locking the whole way (as we did on e300). The cache is non-blocking which means that cache access is allowed even after a miss. Moreover programmer can choose to use stashing mechanism to avoid undue reads of buffer descriptors filled by IOs.


Software Migration ConsiderationsOperating System Migration

►e500v2 imposes numerous changes to classic PowerPC operating systems

►Areas affected include:• Instruction set use• Context switching• Exception handling• MMU operation• Reset

►Necessary changes have already been made by PowerPC OS vendors

►Linux BSPs with gcc based toolchain available from Freescale• http://www.freescale.com/linux

http://www.freescale.com/linux


Software Migration ConsiderationsMigrating to Dual Core

►Dual core systems support for AMP & SMP architectures

►SMP – Symmetric Multi-Processing architecture• Configuration where two or more identical cores can connect to a single shared

memory space. Equal access to memory and resources

►AMP – Asymmetric Multi-Processing architecture• Configuration where the processing elements in a multi-core processor can be

used to run separate tasks. Processing elements are treated separately with own resources and memory space.

►AMP & SMP BSPs available from Freescale for MPC8572

►Selection of architecture depends upon application

Presenter

Presentation Notes

With dual core systems, user has the flexibility to partition the software in AMP architecture or use SMP architecture. In SMP Architecture, User level applications run as if there is a single core underneath. The kernel assigns a core for each task depending on the current load on the cores. This is done in the run-time. In AMP Architecture, programmer can choose to run some application on a particular core and dedicate other core for other functions. Processes running on different process can talk to each other using some shared memory. This way a core can be dedicated to a critical applications like handling data-path while other core handles all the routine jobs of control path. Also user may choose to run different OS in different cores. BSP of 8572 already supports both the architecture.


MemoryMemoryCPU

CPU

I/OI/O

Cache

Cache

Cache

Cache CPU

CacheCache

CacheCache

CPU

Symmetric Multi-processing (SMP)

► SMP is a multi-processor homogeneous computer architecture where two or more identical processors are connected to a globally shared main memory…

► Processors could be separate devices,all on 1 device or a mix

► Typically all CPUs share memory,I/O and are run one OS instance

► Each processor can run independentprocesses and threads

► Any idle processor can be assigned any task

► Issues / challenges• Challenges of migrating legacy code to multithreaded architecture • Additional overhead with scheduling and managing cores

► Performance speed-up depends on application

Presenter

Presentation Notes

AN example of SMP – any desktop PC with dual/quad core running Windows XP or Vista Symmetric means an core can run any process or thread. Easy to use. Software partitioning is headache of OS. It is recommended to use multi-threading application to efficiently use both the core available. (OS can assign threads to individual cores)


Asymmetric Multi-processing (AMP)

► A multi-processing usage model in which individual processors are dedicated to particular tasks, such as running the operating system or performing user requests

► Each core has its own dedicated resources, no scheduling required with other devices

► Software will run as it does on a single core environment

► Issues / Challenges:• System design - deciding how to partition resources between cores• Cannot take advantage of idle time on another CPU

Power Architecture™Core

D-Cache I-Cache

L2 Cache

Control / Interrupts (Linux OS)

Power Architecture™Core

D-Cache I-Cache

L2 Cache

Data PlaneProcessing

(Custom OS)Memory

Core B

Shared

Core A

ETH1 ETH2

Presenter

Presentation Notes

In case user wants to portions software himself, choose AMP. You may run different OS or applications on different cores. As shown in the figure, user may choose to use one core dedicatedly for data plane processing and other for control plane. Beware : AMP does not need to imply heterogeneous hardware !�It is perfectly possible to implement an software AMP system design on SMP hardware


Development System & Ecosystem

Operating System

Optimized High-Speed Drivers

Applications – VortiQA & 3rd Party Vendors

Freescale PowerQUICC II Pro / QorIQ

SiliconSimulation Models

CodeWarrior, GCC,

Freescale-supplied SDK items

Freescale Linux

CodeWarrior, GDB

IDE (com

piler / debugger / build tools)

Presenter

Presentation Notes

Established ecosystem for tools and operating systems


ATX P2020DS-PA (Development System)► P/N: P2020DS-PA (orderable)

► Availability: June-09

► Software: Prototype Linux® AMP/SMP BSP

► Memory• DDR3 – 1GB• NOR Flash – 128 MBN• NAND Flash – 1 GB• SPI ROM – 16 MB • NVRAM: 256B

► PCI Express®: Dual x2 slot

► Ethernet• eTSEC1: RGMII• eTSEC2: RGMII or SGMII• eTSEC3: RGMII or SGMII

► IEEE® 1588• Clock input from DAC / VCXO circuitry• Accessible via test header

► Dual I2C

► SD/MMC card slot

► USB Type A connector

► UARTs: Two DB9 connectors

► SATA2

► GPIO: 16


P2020RDB (Mini-ITX Reference Design Board)► P/N: P2020RDB-PA

► Availability: July-09

► SW: Linux® BSP

► Memory• DDR2 – 1GB • NOR Flash – 16 Mbyte (128Mbit device)• NAND Flash – 32 MByte• SPI ROM – 16 MByte

► PCI Express®• One standard PCIe connector (x1)• One mini PCIe connector (x1)

► Ethernet• Six 10/100/1000 ports as follows:• 4-ports from L2 switch connected to eTSEC1• 1 SGMII PHY connected to eTSEC2• 1 RGMII PHY connected to eTSEC3

► IEEE® 1588• Clock input from DAC / VCXO circuitry• Accessible via test header

► Dual I2C

► SD/MMC card slot

► USB• Option #1 -Mini AB connectors on IO Panel

(default)• Option #2 –Type A connectors (front panel)

► UARTs: Two DB9 connectors


Application Migration – Hardware

Issue Solution with QorIQ P1 /P2Power supply Same voltage architecture. Adjustable supplies will

ease migration from 1.1V on PowerQUICC II Pro to 0.95V for QorIQ P1

Existing interfaces Re-use design for existing interfaces such as Ethernet, DDR2, eSPI, JTAG and USB

New interfaces Use application notes, evaluation boards and other resources from http://www.freescale.com.

Power performance Best-in-class power performance, enable fanless “green” design. Advanced power management.

Simulation IBIS models available for all devices

Future expansion Pin compatibility between P1011, P1020, P2020 and P2020 devices simple migration to a higher performance or lower power application

►New board design required for QorIQ device

Presenter

Presentation Notes

- The slide details the hardware related issues - New board design required. Minor changes required to power design and new interfaces . However much of the existing design can be re-used making the jump to P1 / P2 QorIQ very small. - Pin compatibility across multiple devices provides performance vs power flexibility


Application Migration – Software

Issue Solution with QorIQ P1 /P2Code base migration

General code compatibility with exceptions in certain areas – floating point, interrupts, supervisor instructions. See resources at www.freescale.com

Operating systems & tools

Established ecosystem of operating systems BSPs, tools and drivers for e500 based platforms, thus reducing development time

Software compatibility for reused interfaces

Code used for existing interfaces such as Ethernet and security block will migrate

New interfaces and features

Driver-level source code available for Freescale evaluation platforms from www.freescale.com

►Migration from e300 to e500 based platform

Presenter

Presentation Notes

Software Migration - Use Freescale’s extensive resources and ecosystem which reduce the task of migrating code from e300 to e500

http://www.freescale.com/


Application – Migrating to Dual Core

►Consider why? • Achieve increased performance of existing application • Accommodate new services and functions• Integration of external functions to achieve lower cost

►Do you choose AMP or SMP?• How will the application be partitioned? • Consider memory and resource access on device

►Is the existing application single threaded or multi-threaded• Single threaded

AMP – Run existing code as is on single coreSMP – Run multiple versions of existing code

• Multi-threadedSMP – Run single instance of un-modified application

►Profile existing code and recode critical spots, make use of parallel processing to optimise performance

Presenter

Presentation Notes

Migrating from single core to dual core. - First of all lets consider why are you migrating to a dual or multicore approach. It is generally to increase the performance capability of the current application. It can be to put down to trying to improve processing performance of existing functions or add more services functions which will overall reduce processing unit cost in $. User needs to decide how they want to partition their application based on AMP and SMP architecture AMP – Cores work almost independent of each other. Each core has access to a fixed set of resources on the device. Example - eTSEC 1 will be assigned to a core hence data from this interface will only ever be processed by the same core, regardless of the core’s workload For SMP cores work together and share resources. More inter-core communication required, resource and memory management becomes important. For the above scenario, packet data from an eTSEC will go to the first available core, thus improving the packet processing time. Another issue to consider is whether or not the existing application is single or multi-threaded. If single threaded, a user can run the application as it is for AMP and SMP configurations. For a multithreaded configuration, the code is best suited for an SMP environment. The final note is that there is “no golden bullet” for migrating to a dual or multicore system. A user needs to profile and study their existing code to find areas of parallelisation, which will bring the ultimate improvement in performance

migrating from powerquicc ii pro processors to qoriq p1020 and

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