mid semester a project presentation instructor: mr. almog assaf real time image processing presented...

Mid Semester A Project Mid Semester A Project PresentationPresentation

Instructor:Instructor:

Mr. Almog AssafMr. Almog Assaf

Real Time Image Real Time Image ProcessingProcessing

Presented by:Presented by:

Baruch KorenBaruch Koren

Shahaf FisherShahaf Fisher

Technion – Israel Institute Of TechnologyTechnion – Israel Institute Of Technology

Electrical Engineering DepartmentElectrical Engineering DepartmentHigh speed digital systems laboratory

AgendaAgenda• Project’s Goals.Project’s Goals.

• System Block Diagram and System System Block Diagram and System overview.overview.

• Defining DVI interface and generic Defining DVI interface and generic blocks.blocks.

• Image Processing Background- Color Image Processing Background- Color Spaces.Spaces.

• Image Processing Development Image Processing Development Stages.Stages.

• Time table.Time table.



Project’s GoalsProject’s Goals• Preparing a systematic infrastructure Preparing a systematic infrastructure

for future laboratories projects. for future laboratories projects.

• Preparing instructions for integrating Preparing instructions for integrating new components to this system.new components to this system.

• Studying this complex system - the Studying this complex system - the environment and the designing tools.environment and the designing tools.

• Studying VHDL language, with an Studying VHDL language, with an emphasis on coding style, modular emphasis on coding style, modular and generic design.and generic design.



Project’s GoalsProject’s Goals• Studying and implementing topics in Studying and implementing topics in

image processing, especially image processing, especially algorithms that can be implemented algorithms that can be implemented in real time video systems.in real time video systems.



System Top Hierarchy Block System Top Hierarchy Block DiagramDiagram

DVI inputDVI input DVI OutputDVI Output

RX TX

qe_rxqe_rx



de_rxde_rxhsync_rxhsync_rx

odck_rxodck_rx

vsync_rxvsync_rx

idck_txidck_tx

de_txde_tx

vsync_txvsync_tx

hsync_txhsync_tx

data_txdata_tx

i2c and control

i2c and control

DVI_interface_2txDVI_interface_2tx

1

block1block1

24bit24bit 12bit

DVI_interface_2rDVI_interface_2rxx

11data_en_indata_en_in

vsync_invsync_in

hsync_inhsync_in

data_indata_in

ClkClk

24bit

ClkClk

vsync_outvsync_out

data_outdata_out

data_en_outdata_en_out

hsync_outhsync_out

24bit

block1block1 block1block1

Gidel’s block

top_iftop_if

24bit

clk1clk1

clk0clk0

Local BusLocal Bus

External ddrII External ddrII Memory Memory interfaceinterface

pll4ddrII

user_pll

clkclkclk_plusclk_plusclk_minusclk_minus

ck_ack_a

ck_bck_b

System System OverviewOverview

•DVI interfaces. DVI interfaces.

•System Clocks.System Clocks.

•Generic modules.Generic modules.

•Gidel interface.Gidel interface.





RX TX

qe_rxqe_rx




odck_rxodck_rx

vsync_rxvsync_rx

idck_txidck_tx

de_txde_tx

vsync_txvsync_tx

hsync_txhsync_tx

data_txdata_tx

i2c and control

i2c and control


1

block1block1

24bit24bit 12bit



vsync_invsync_in

hsync_inhsync_in

data_indata_in

ClkClk

24bit

ClkClk

vsync_outvsync_out

data_outdata_out


hsync_outhsync_out

24bit


Gidel’s block

top_iftop_if

24bit

clk1clk1

clk0clk0

Local BusLocal Bus


pll4ddrII

user_pll


ck_ack_a

ck_bck_b



RX TX

qe_rxqe_rx




odck_rxodck_rx

vsync_rxvsync_rx

idck_txidck_tx

de_txde_tx

vsync_txvsync_tx

hsync_txhsync_tx

data_txdata_tx

i2c and control

i2c and control

DVI_interface_2tDVI_interface_2txx

1

block1block1

24bit24bit 12bit



vsync_invsync_in

hsync_inhsync_in

data_indata_in

ClkClk

24bit

ClkClk

vsync_outvsync_out

data_outdata_out


hsync_outhsync_out

24bit


Gidel’s block

top_iftop_if

24bit

clk1clk1

clk0clk0

Local BusLocal Bus


pll4ddrII

user_pll


ck_ack_a

ck_bck_b

DVI interfacesDVI interfaces• ConnectionConnection between the DVI Reciever and between the DVI Reciever and

Transmitter to the FPGA’s top level hierarchy. Transmitter to the FPGA’s top level hierarchy.

• SettingsSettings for using default for using default DVI ReceiverDVI Receiver (SiI1171) operation mode: (SiI1171) operation mode: not programmable - with no I2C involvenot programmable - with no I2C involve 24-bit pixel data for one pixel per clock24-bit pixel data for one pixel per clock

• SettingsSettings for using default for using default DVI TransmitterDVI Transmitter (SiI1172) operation mode: (SiI1172) operation mode: not programmable - with no I2C involve.not programmable - with no I2C involve. samples one-half pixel (12 bit) at every latch falling samples one-half pixel (12 bit) at every latch falling

and rising edge of the clock. and rising edge of the clock.



Before DVI interfacesBefore DVI interfaces

DVI input

DVI Output

RX TX

qe_rxqe_rx



de_rxde_rx

hsync_rxhsync_rx

odck_rxodck_rx

vsync_rxvsync_rx

idck_txidck_tx

de_txde_tx

vsync_txvsync_tx

hsync_txhsync_tx

data_txdata_tx

CLKCLK

i2c and control

24bit 12bit

i2c and control

After DVI interfacesAfter DVI interfaces

DVI inputDVI inputDVI OutputDVI Output

RX TX

qe_rxqe_rx




odck_rxodck_rx

vsync_rxvsync_rx

idck_txidck_tx

de_txde_tx

vsync_txvsync_tx

hsync_txhsync_tx

data_txdata_tx

i2c and control

i2c and control


24bit24bit 12bit

DVI_interface_2rxDVI_interface_2rx

24bit



RX TX

qe_rxqe_rx




odck_rxodck_rx

vsync_rxvsync_rx

idck_txidck_tx

de_txde_tx

vsync_txvsync_tx

hsync_txhsync_tx

data_txdata_tx

i2c and control

i2c and control


1

block1block1

24bit24bit 12bit



vsync_invsync_in

hsync_inhsync_in

data_indata_in

ClkClk

24bit

ClkClk

vsync_outvsync_out

data_outdata_out


hsync_outhsync_out

24bit


Gidel’s block

top_iftop_if

24bit

clk1clk1

clk0clk0

Local BusLocal Bus


pll4ddrII

user_pll


ck_ack_a

ck_bck_b



System CLOCKsSystem CLOCKs

System ClocksSystem Clocks

• Input Clocks: Input Clocks: Main clock (clk0,clk1).Main clock (clk0,clk1). Local bus clock (lclk).Local bus clock (lclk). Slower clock (clk2). Slower clock (clk2).

• System PLLs: System PLLs: pll4ddr2.pll4ddr2. user_pll.user_pll.



Generic modulesGeneric modules

•Generic block type 1Generic block type 1

•Generic block type 2Generic block type 2



Defining Defining Generic block Generic block type 1type 1



vsync_outvsync_out

ClkClk

data_en_indata_en_in

vsync_invsync_inhsync_inhsync_in

data_in(23 DOWNTO 0)data_in(23 DOWNTO 0)

1

data_out(23 DOWNTO 0)data_out(23 DOWNTO 0)data_en_outdata_en_outhsync_outhsync_out

Integrating Integrating Generic block Generic block type 1type 1

DVI input

DVI Output

RX TX

qe_rxqe_rx



de_rxde_rx

hsync_rxhsync_rx

odck_rxodck_rx

vsync_rxvsync_rx

idck_txidck_tx

de_txde_tx

vsync_txvsync_tx

hsync_txhsync_tx

data_txdata_tx

i2c and control

i2c and control

data_en_indata_en_in

vsync_invsync_in

hsync_inhsync_in

data_indata_in


ClkClk

1

ClkClk

vsync_outvsync_out

data_outdata_out


hsync_outhsync_out

block1block1 DVI_interface_2rxDVI_interface_2rx

24bit 24bit 24bit12bit




read_reqread_req

Write_enWrite_en 2

data_outdata_out

Controller

read_en 2

data_outdata_out

Write_reqWrite_req Write_reqWrite_req

Write_enWrite_en Write_enWrite_en

Write_reqWrite_req

data_indata_in data_indata_in

ClkClkClkClk

syncs_insyncs_in syncs_insyncs_insyncs_outsyncs_out syncs_outsyncs_out

Generic block type 2Generic block type 2



read_reqread_req

Write_enWrite_en

data_outdata_out

read_en

Write_reqWrite_req

data_indata_in

ClkClk

Buffer(FIFO)

X

X

X

X

X

X

X

X

X

X

X

X

Example Use of block type 2

…

…

…

syncs_insyncs_in

syncs_outsyncs_out



RX TX

qe_rxqe_rx




odck_rxodck_rx

vsync_rxvsync_rx

idck_txidck_tx

de_txde_tx

vsync_txvsync_tx

hsync_txhsync_tx

data_txdata_tx

i2c and control

i2c and control


1

block1block1

24bit24bit 12bit



vsync_invsync_in

hsync_inhsync_in

data_indata_in

ClkClk

24bit

ClkClk

vsync_outvsync_out

data_outdata_out


hsync_outhsync_out

24bit


Gidel’s block

top_iftop_if

24bit

clk1clk1

clk0clk0

Local BusLocal Bus


pll4ddrII

user_pll


ck_ack_a

ck_bck_b



System System Block Diagram Block Diagram and Portsand Ports

GidelGidelInterfacInterfacee

Image Processing Image Processing Background- Background- Color Color SpacesSpaces

Definition: A color space is a mathematical way is a mathematical way

of specifying the color of a pixel in a of specifying the color of a pixel in a color image.color image.

Objective: convert our video input to a color

space which suits best image processing algorithms.



Color Spaces-RGBColor Spaces-RGB

RGB model uses three numerical RGB model uses three numerical components to represent a color in a components to represent a color in a three-dimensional Cartesian coordinate three-dimensional Cartesian coordinate system. system.

Each component has a rangeEach component has a range

of 0 to 255 (for a 8-bit of 0 to 255 (for a 8-bit

representation per color).representation per color).



RGB is an RGB is an additiveadditive color system and that color system and that is why RGB color space is the most is why RGB color space is the most common choice for computer graphics and common choice for computer graphics and image and video displayers.image and video displayers.



Color Spaces-RGBColor Spaces-RGB

Incompatibility of RGB space to Incompatibility of RGB space to Image ProcessingImage Processing

• processing an image in the RGB space is processing an image in the RGB space is more complex.more complex.

• Using RGB requires wider bandwidth and Using RGB requires wider bandwidth and larger storage space. larger storage space.



Which Color Space Suits Best Which Color Space Suits Best Image Processing AlgorithmsImage Processing Algorithms??

The human Eye is much more sensitive to The human Eye is much more sensitive to intensity changes than to colors. intensity changes than to colors.



Most image processing algorithms operates Most image processing algorithms operates on the image on the image intensityintensity..

If we use a color space which does a separation If we use a color space which does a separation between intensity component and chrominance between intensity component and chrominance components,components,

Image processing algorithms will be Image processing algorithms will be fasterfaster, , demand demand less bandwidthless bandwidth and and less storage less storage space,space, andand cheapercheaper..

Color Spaces-YCbCrColor Spaces-YCbCr

The YCbCr is a model which does a separation between intensity (luma) component (component Y) and chrominance components (Cb,Cr).



Color Spaces-YCbCrColor Spaces-YCbCr

The basic equations to convert The basic equations to convert between gamma-corrected RGB between gamma-corrected RGB (notated as R’G’B’) and YCbCr are:(notated as R’G’B’) and YCbCr are:



128

128

b

r

b

r

Y 0.257 0.504 0.098 R' 16

C = -0.148 -0.291 0.439 G' + 128

0.439 -0.368 -0.071 B' 128C

R' 1.164 0 1.596 Y-16

G' = 1.164 0.391 -0.813 C

B' 1.164 2.018 0 C

Development StagesDevelopment Stages BackgroundBackground

• DesignDesign

• CodingCoding

• SimulationSimulation

• Integration & Integration &

ImplementationImplementation



Development Stages - Development Stages - SimulationSimulation



SIM. UUT ANA.

FilesIn

FilesOut

Test Bench

WeeWeek k

DatesDatesActionActionCommenCommentsts

1-21-25.11.06 -5.11.06 -Introduction to the Lab, Introduction to the Lab, comprehending and defining the comprehending and defining the project goals.project goals. 18.11.0618.11.06

3319.11.06 19.11.06 --

Studying the understanding the Studying the understanding the complex system and its complex system and its designing tools available. designing tools available.

25.11.0625.11.06

4426.11.06 26.11.06 --

Preparing and presenting the Preparing and presenting the characterization report.characterization report.

Project Project CharacterizatioCharacterization Presentationn Presentation

2.12.062.12.06

553.12.06 -3.12.06 -Preparing a detailed blocks Preparing a detailed blocks diagram of the system.diagram of the system.

9.12.069.12.06

Time TableTime Table



WeeWeek k


6610.12.06 10.12.06 --

Defining and characterizing the Defining and characterizing the abstract generic block, which will abstract generic block, which will be implemented when defining a be implemented when defining a processing block.processing block.

16.12.0616.12.06

7-107-1017.12.06 17.12.06 --

Preparing and presenting the Preparing and presenting the Midterm Presentation and report.Midterm Presentation and report.Defining the memory and the Defining the memory and the display controllers interfaces.display controllers interfaces.

Midterm Midterm PresentationPresentation

13.01.0713.01.07

111114.01.07 14.01.07 --

Studying and writingStudying and writing background on the meaning of background on the meaning of color spaces and converting color spaces and converting between color spaces needed for between color spaces needed for processing algorithms processing algorithms DesigningDesigning a Basic processing a Basic processing unit – color spaces converter.unit – color spaces converter.

20.01.0720.01.07

12-12-1313

21.01.07 21.01.07 --

VHDL VHDL codingcoding of the Basic of the Basic processing unit – color spaces processing unit – color spaces converter.converter.

3.02.073.02.07

Time TableTime Table



Time TableTime TableWeeWeek k


141404.02.07 04.02.07 --

SimulationSimulation of the Basic of the Basic processing unit – color spaces processing unit – color spaces converter.converter.

10.02.0710.02.07

15-15-

End End SemSemAA

11.02.07 11.02.07 --

Integration and Implementation Integration and Implementation of the Basic processing unit – of the Basic processing unit – color spaces converter.color spaces converter.

Preparing and presenting the Preparing and presenting the semester A Project Presentation semester A Project Presentation and report.and report.

Exams periodExams period

Final A Final A semester semester Project Project PresentationPresentation

06.03.0706.03.07



THE END!THE END!

Auxiliary Auxiliary slides slides



Basic System Basic System Block Diagram Block Diagram and Portsand Ports



--======================================================================--= DVI Transmitter connections (on PSDB_DVI) =--======================================================================

data_tx : OUT STD_LOGIC_VECTOR( 11 DOWNTO 0 ); -- Transitter data outputdata_tx : OUT STD_LOGIC_VECTOR( 11 DOWNTO 0 ); -- Transitter data outputmsen_tx : IN STD_LOGIC; -- Monitor Sensemsen_tx : IN STD_LOGIC; -- Monitor Sensepd_tx : OUT STD_LOGIC; -- Power Down (Active Low)pd_tx : OUT STD_LOGIC; -- Power Down (Active Low)de_tx : OUT STD_LOGIC; -- Data Enablede_tx : OUT STD_LOGIC; -- Data Enablehsync_tx : OUT STD_LOGIC; -- Horizontal Synchsync_tx : OUT STD_LOGIC; -- Horizontal Syncvsync_tx : OUT STD_LOGIC; -- Vertical Syncvsync_tx : OUT STD_LOGIC; -- Vertical Syncscl_tx : INOUT STD_LOGIC; -- I2C Clockscl_tx : INOUT STD_LOGIC; -- I2C Clocksda_tx : INOUT STD_LOGIC; -- I2C Datasda_tx : INOUT STD_LOGIC; -- I2C Dataidck_tx : OUT STD_LOGIC; -- Transmitter data clockidck_tx : OUT STD_LOGIC; -- Transmitter data clockisel_rst_tx : OUT STD_LOGIC; -- I2C Interface Selectisel_rst_tx : OUT STD_LOGIC; -- I2C Interface Selectctl3_tx : OUT STD_LOGIC; -- Transmitter Control ctl3_tx : OUT STD_LOGIC; -- Transmitter Control

SignalSignal

SiI1172 ports – DVI SiI1172 ports – DVI TransmitterTransmitter



--======================================================================--= DVI Receiver connections (on PSDB_DVI) =--======================================================================

qe_rx : IN STD_LOGIC_VECTOR( 23 DOWNTO 0 ); -- Receiver even data inputqe_rx : IN STD_LOGIC_VECTOR( 23 DOWNTO 0 ); -- Receiver even data inputqo_rx : IN STD_LOGIC_VECTOR( 23 DOWNTO 0 ); -- Receiver odd data inputqo_rx : IN STD_LOGIC_VECTOR( 23 DOWNTO 0 ); -- Receiver odd data inputodck_rx : IN STD_LOGIC; -- Receiver data clockodck_rx : IN STD_LOGIC; -- Receiver data clockscdt_rx : IN STD_LOGIC; -- Sync detectscdt_rx : IN STD_LOGIC; -- Sync detectctl1_rx : IN STD_LOGIC; -- Receiver control signalctl1_rx : IN STD_LOGIC; -- Receiver control signalctl2_rx : IN STD_LOGIC; -- Receiver control signalctl2_rx : IN STD_LOGIC; -- Receiver control signalctl3_rx : IN STD_LOGIC; -- Receiver control signalctl3_rx : IN STD_LOGIC; -- Receiver control signalstag_out_rx : OUT STD_LOGIC; -- Staggered Outputstag_out_rx : OUT STD_LOGIC; -- Staggered Outputpixs_rx : OUT STD_LOGIC; -- Pixel Selectpixs_rx : OUT STD_LOGIC; -- Pixel Selectst_sda_rx : INOUT STD_LOGIC; -- I2C Data / Output Drivest_sda_rx : INOUT STD_LOGIC; -- I2C Data / Output Drivepd_rx : OUT STD_LOGIC; -- Power Downpd_rx : OUT STD_LOGIC; -- Power Downhs_djtr_rx : OUT STD_LOGIC; -- Horisontal Sync De-jitterhs_djtr_rx : OUT STD_LOGIC; -- Horisontal Sync De-jitterock_inv_scl_rx : INOUT STD_LOGIC; -- ODCK Polarity / I2C Clockock_inv_scl_rx : INOUT STD_LOGIC; -- ODCK Polarity / I2C Clockmode_rx : OUT STD_LOGIC; -- Mode Selectmode_rx : OUT STD_LOGIC; -- Mode Selecthsync_rx : IN STD_LOGIC; -- Horizontal Synchsync_rx : IN STD_LOGIC; -- Horizontal Syncvsync_rx : IN STD_LOGIC; -- Vertical Syncvsync_rx : IN STD_LOGIC; -- Vertical Syncde_rx : IN STD_LOGIC; -- Data Enablede_rx : IN STD_LOGIC; -- Data Enablepdo_rx : OUT STD_LOGIC; -- Output driver power downpdo_rx : OUT STD_LOGIC; -- Output driver power downhpd_rx : IN STD_LOGIC hpd_rx : IN STD_LOGIC

SiI1171 ports - DVI ReceiverSiI1171 ports - DVI Receiver



----DVI Transmitter connections DVI Transmitter connections ((on PSDB_DVIon PSDB_DVI))

pd_tx <pd_tx <= = '1';'1';----de_tx <de_tx <= = de_rx;de_rx;----hsync_tx <hsync_tx <= = hsync_rx;hsync_rx;----vsync_tx <vsync_tx <= = vsync_rx;vsync_rx;----scl_tx <scl_tx <= = '0';'0';----sda_tx <sda_tx <= = '0';'0';----idck_tx <idck_tx <= = odck_rx;odck_rx;----isel_rst_tx <isel_rst_tx <= = '0';'0';----ctl3_tx <ctl3_tx <= = '0';'0';----

----DVI Receiver connections DVI Receiver connections ((on PSDB_DVIon PSDB_DVI))stag_out_rx <stag_out_rx <= = '1';'1';----pixs_rx <pixs_rx <= = '0';'0';----st_sda_rx <st_sda_rx <= = '1';'1';----pd_rx <pd_rx <= = '1';'1';----hs_djtr_rx <hs_djtr_rx <= = '1';'1';----ock_inv_scl_rx <ock_inv_scl_rx <= = '0';'0';----mode_rx <mode_rx <= = '1';'1';----pdo_rx <pdo_rx <= = '1';'1';----

SiI1171 and SiI1172 SiI1171 and SiI1172 configurationconfiguration

Settings for using defaultSettings for using default DVI Transmitter operation modeDVI Transmitter operation mode

• not programmable - with no I2C involvenot programmable - with no I2C involve• samples one-half pixel )12 bit( at everysamples one-half pixel )12 bit( at every

latch falling and rising edge of the clocklatch falling and rising edge of the clock

Settings for using one pixel per clockSettings for using one pixel per clock DVI Receiver operation modeDVI Receiver operation mode

• not programmable - with no I2C involvenot programmable - with no I2C involve• 24-bit pixel data for one pixel per clock24-bit pixel data for one pixel per clock



process(odck_rx)process(odck_rx)beginbegin

case odck_rx iscase odck_rx iswhen '0' => when '0' =>

data_tx <= qe_rx ( 23 DOWNTO data_tx <= qe_rx ( 23 DOWNTO 12);12);

when '1' =>when '1' =>data_tx <= qe_rx ( 11 DOWNTO data_tx <= qe_rx ( 11 DOWNTO

0); 0); end case;end case;

end process;end process;

Setting the data for the Setting the data for the transmittertransmitter



System System Block Diagram Block Diagram and Portsand Ports



System ClocksSystem Clocks

clk0,clk1:clk0,clk1: the the GiDELGiDEL, , PROCStar IIPROCStar II™ ™ main clk that was set, enters 2 PLLs main clk that was set, enters 2 PLLs as follows:as follows:

• clk0clk0: : enters to pll4ddrII_a_1, reserved pll, which produces 2 differential enters to pll4ddrII_a_1, reserved pll, which produces 2 differential clocks to clocks to the external memory DDR2 SDRAM 64MB banks: ck_a and the external memory DDR2 SDRAM 64MB banks: ck_a and ck_b for DDR2 ck_b for DDR2 bank A and B, respectfully. bank A and B, respectfully. • clk1clk1: : enters to the user PLL, and produces 3 output clocks. clk, clk_plus, enters to the user PLL, and produces 3 output clocks. clk, clk_plus,

clk_minus have the same frequency desired by the user, which can be clk_minus have the same frequency desired by the user, which can be chosen as an integer multiple of the main frequency – with respect to chosen as an integer multiple of the main frequency – with respect to

the the the maximum value allowed 300Mhz. clk, clk_plus, clk_minus have the maximum value allowed 300Mhz. clk, clk_plus, clk_minus have phase phase shifting of 0 deg, +127 deg, -127 deg, respectfully.shifting of 0 deg, +127 deg, -127 deg, respectfully.

The The GiDELGiDEL, , PROCStar IIPROCStar II™ ™ main clk (clk0,clk1) ranges from 30Mhz up to main clk (clk0,clk1) ranges from 30Mhz up to 200Mhz, and can be defined as desired. clk1 arrives ~200ps before clk0. 200Mhz, and can be defined as desired. clk1 arrives ~200ps before clk0. In the example above main clk was set to 200Mhz.In the example above main clk was set to 200Mhz.



System CLOCKsSystem CLOCKs

lclklclk:: This is the Local Bus Clock, working at 33Mhz.This is the Local Bus Clock, working at 33Mhz.

clk2clk2:: The The GiDELGiDEL, , PROCStar IIPROCStar II™ ™ external or internal slower clk. external or internal slower clk. If internal then can be chosen as one of the following values:If internal then can be chosen as one of the following values:Main clock * (1/2, 1/4, 1/6, 1/8, 1/10, 1/12, 1/14, 1/16, 1/18, 1/20, 1/22, Main clock * (1/2, 1/4, 1/6, 1/8, 1/10, 1/12, 1/14, 1/16, 1/18, 1/20, 1/22,

1/24, 1/26, 1/28, 1/30, 1/32). 1/24, 1/26, 1/28, 1/30, 1/32).For example when the main clock is 100Mhz then clk2 can be set as: For example when the main clock is 100Mhz then clk2 can be set as: (50, 25, 16.667, 12.5, 10, 8.3333, 7.1429, 6.25, 5.5556, 5, 4.5455, (50, 25, 16.667, 12.5, 10, 8.3333, 7.1429, 6.25, 5.5556, 5, 4.5455,

4.1667, 4.1667, 3.8462, 3.5714, 3.3333, 3.125) [Mhz ]. 3.8462, 3.5714, 3.3333, 3.125) [Mhz ].The The GiDELGiDEL, , PROCStar IIPROCStar II™ ™ uses the defult of Main clock * 1/8.uses the defult of Main clock * 1/8.

DVI_interface_rx2tx portsDVI_interface_rx2tx portsTechnion – Israel Institute Of TechnologyTechnion – Israel Institute Of Technology


ENTITY DVI_interface_rx2tx ISENTITY DVI_interface_rx2tx IS PORTPORT((--======================================================================--======================================================================--= --= DVI Transmitter connections DVI Transmitter connections ((on PSDB_DVIon PSDB_DVI) =) =--======================================================================--======================================================================

data_tx data_tx : : OUT STD_LOGIC_VECTOROUT STD_LOGIC_VECTOR( ( 11 DOWNTO 011 DOWNTO 0 ) ); ; -- -- Transitter data outputTransitter data outputmsen_tx msen_tx : : IN STD_LOGIC; IN STD_LOGIC; -- -- Monitor SenseMonitor Sensepd_tx pd_tx : : OUT STD_LOGIC; OUT STD_LOGIC; -- -- Power Down Power Down ((Active LowActive Low))de_tx de_tx : : OUT STD_LOGIC; OUT STD_LOGIC; -- -- Data EnableData Enablehsync_tx hsync_tx : : OUT STD_LOGIC; OUT STD_LOGIC; -- -- Horizontal SyncHorizontal Syncvsync_tx vsync_tx : : OUT STD_LOGIC; OUT STD_LOGIC; -- -- Vertical SyncVertical Syncscl_tx scl_tx : : INOUT STD_LOGIC; INOUT STD_LOGIC; -- -- I2C ClockI2C Clocksda_tx sda_tx : : INOUT STD_LOGIC; INOUT STD_LOGIC; -- -- I2C DataI2C Dataidck_tx idck_tx : : OUT STD_LOGIC; OUT STD_LOGIC; -- -- Transmitter data clockTransmitter data clockisel_rst_tx isel_rst_tx : : OUT STD_LOGIC; OUT STD_LOGIC; -- -- I2C Interface SelectI2C Interface Selectctl3_tx ctl3_tx : : OUT STD_LOGIC; OUT STD_LOGIC; -- -- Transmitter Control SignalTransmitter Control Signal

--======================================================================--======================================================================--= --= DVI Receiver connections DVI Receiver connections ((on PSDB_DVIon PSDB_DVI) =) =--======================================================================--======================================================================

qe_rx qe_rx : : IN STD_LOGIC_VECTORIN STD_LOGIC_VECTOR( ( 23 DOWNTO 023 DOWNTO 0 ) ); ; -- -- Receiver even data inputReceiver even data inputqo_rx qo_rx : : IN STD_LOGIC_VECTORIN STD_LOGIC_VECTOR( ( 23 DOWNTO 023 DOWNTO 0 ) ); ; -- -- Receiver odd data inputReceiver odd data inputodck_rx odck_rx : : IN STD_LOGIC; IN STD_LOGIC; -- -- Receiver data clockReceiver data clockscdt_rx scdt_rx : : IN STD_LOGIC; IN STD_LOGIC; -- -- Sync detectSync detectctl1_rx ctl1_rx : : IN STD_LOGIC; IN STD_LOGIC; -- -- Receiver control signalReceiver control signalctl2_rx ctl2_rx : : IN STD_LOGIC; IN STD_LOGIC; -- -- Receiver control signalReceiver control signalctl3_rx ctl3_rx : : IN STD_LOGIC; IN STD_LOGIC; -- -- Receiver control signalReceiver control signalstag_out_rx stag_out_rx : : OUT STD_LOGIC; OUT STD_LOGIC; -- -- Staggered OutputStaggered Outputpixs_rx pixs_rx : : OUT STD_LOGIC; OUT STD_LOGIC; -- -- Pixel SelectPixel Selectst_sda_rx st_sda_rx : : INOUT STD_LOGIC; INOUT STD_LOGIC; -- -- I2C Data I2C Data / / Output DriveOutput Drivepd_rx pd_rx : : OUT STD_LOGIC; OUT STD_LOGIC; -- -- Power DownPower Downhs_djtr_rx hs_djtr_rx : : OUT STD_LOGIC; OUT STD_LOGIC; -- -- Horisontal Sync DeHorisontal Sync De--jitterjitterock_inv_scl_rx ock_inv_scl_rx : : INOUT STD_LOGIC; INOUT STD_LOGIC; -- -- ODCK Polarity ODCK Polarity / / I2C ClockI2C Clockmode_rx mode_rx : : OUT STD_LOGIC; OUT STD_LOGIC; -- -- Mode SelectMode Selecthsync_rx hsync_rx : : IN STD_LOGIC; IN STD_LOGIC; -- -- Horizontal SyncHorizontal Syncvsync_rx vsync_rx : : IN STD_LOGIC; IN STD_LOGIC; -- -- Vertical SyncVertical Syncde_rx de_rx : : IN STD_LOGIC; IN STD_LOGIC; -- -- Data EnableData Enablepdo_rx pdo_rx : : OUT STD_LOGIC; OUT STD_LOGIC; -- -- Output driver power downOutput driver power downhpd_rx hpd_rx : : IN STD_LOGIC IN STD_LOGIC -- -- Hot Plug detection signalHot Plug detection signal

));;END DVI_interface_rx2tx;END DVI_interface_rx2tx;




ENTITY block1 ISENTITY block1 IS PORTPORT((--======================================================================--======================================================================--= --= block1 Inputs block1 Inputs ==--======================================================================--======================================================================

clk clk : : IN STD_LOGIC; IN STD_LOGIC; -- -- main clock from odck_rxmain clock from odck_rxdata_in data_in : : IN STD_LOGIC_VECTORIN STD_LOGIC_VECTOR( ( 23 DOWNTO 023 DOWNTO 0 ) ); ; -- -- data inputdata inputde_in de_in : : IN STD_LOGIC; IN STD_LOGIC; -- -- Data Enable inputData Enable inputhsync_in hsync_in : : IN STD_LOGIC; IN STD_LOGIC; -- -- Horizontal Sync inputHorizontal Sync inputvsync_in vsync_in : : IN STD_LOGIC; IN STD_LOGIC; -- -- Vertical Sync inputVertical Sync input

--======================================================================--======================================================================--= --= block1 Outputs block1 Outputs ==--======================================================================--======================================================================

-- -- ?????? clk_out clk_out : : OUT STD_LOGIC; OUT STD_LOGIC; -- -- main clock outmain clock out ??????data_out data_out : : OUT STD_LOGIC_VECTOROUT STD_LOGIC_VECTOR( ( 23 DOWNTO 023 DOWNTO 0 ) ); ; -- -- data outputdata outputde_out de_out : : OUT STD_LOGIC; OUT STD_LOGIC; -- -- Data Enable outputData Enable outputhsync_out hsync_out : : OUT STD_LOGIC; OUT STD_LOGIC; -- -- Horizontal Sync outputHorizontal Sync outputvsync_out vsync_out : : OUT STD_LOGICOUT STD_LOGIC----; ; -- -- Vertical Sync outputVertical Sync output

));;END block1;END block1; ARCHITECTURE arc_block1_In2Out OF block1 ISARCHITECTURE arc_block1_In2Out OF block1 IS BEGINBEGIN

-- -- ??? clk_out ??? clk_out <<== clk;clk; data_out data_out <<== data_in;data_in; de_outde_out <<= = de_in; de_in; hsync_outhsync_out <<== hsync_in; hsync_in; vsync_outvsync_out <<== vsync_in;vsync_in;

END arc_block1_In2Out;END arc_block1_In2Out;

mid semester a project presentation instructor: mr. almog assaf real time image processing presented...

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