mid semester 2012 tid203

7/30/2019 Mid Semester 2012 TID203

1/17

Department of Electrical and Computer Engineering

300539 Transmission and Interface Design 203

Mid-Semester Test 2012

Name _________________________________________________________

Student ID _________________________________________________________


2/17

Question 1 (5 Marks)

A hypothetical logic family has the following specifications.

OH IH

OL IL

OH IH

OL IL

V 4.6 V V 4.0 V

V 0.5 V V 1.0 V

I 1 mA I 50 A

I 8 mA I 0.6 mA

m

= =

= =

= - =

= = -

(a) What are the noise margins?

(b) What is the fan-out capability? That is, suppose all gates are chosen from the same

logic family, how many gates can an output gate reliably drive?


3/17


A digital synchronous sequential circuit is shown below.

Suppose the flip-flops are 74HC74A devices and the NOR gates are 74HC02 devices.

Determine the maximum clock frequency at which the circuit can operate reliably when

the logic devices are powered with a supply voltage of CCV 5V= .

Q

D

Q

inD

CLK

Q

D

Q

Q

D

Q


4/17


In the RLC circuit shown below, 100R = W , 1 H=L , and 100 Fm=C , Determine

the waveform of the current, ( )i t , coming from the voltage source, if

(a) The voltage source is a DC supply of 10 V.

(b) The voltage source has waveform ( ) 10 cos(100 ) V=v t t .

CRv (t)

i (t) L

.


5/17


6/17

MM74HC74A

DualD-TypeFlip-Flopwith

PresetandClear

1983 Fairchild Semiconductor Corporation www.fairchildsemi.comMM74HC74A Rev. 1.3.0

February 2008

MM74HC74A

Dual D-Type Flip-Flop with Preset and Clear

Features

Typical propagation delay: 20ns

Wide power supply range: 2V6V

Low quiescent current: 40A maximum (74HC Series)

Low input current: 1A maximum

Fanout of 10 LS-TTL loads

General Description

The MM74HC74A utilizes advanced silicon-gate CMOStechnology to achieve operating speeds similar to theequivalent LS-TTL part. It possesses the high noiseimmunity and low power consumption of standardCMOS integrated circuits, along with the ability to drive10 LS-TTL loads.

This flip-flop has independent data, preset, clear, andclock inputs and Q and Q outputs. The logic levelpresent at the data input is transferred to the output dur-

ing the positive-going transition of the clock pulse. Pre-set and clear are independent of the clock andaccomplished by a low level at the appropriate input.

The 74HC logic family is functionally and pinout compat-ible with the standard 74LS logic family. All inputs areprotected from damage due to static discharge by inter-nal diode clamps to V

CC

and ground.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order NumberPackageNumber Package Description

MM74HC74AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"Narrow

MM74HC74ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC74AMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,4.4mm Wide

MM74HC74AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide


7/17

1983 Fairchild Semiconductor Corporation www.fairchildsemi.comMM74HC74A Rev. 1.3.0 2

MM74HC74A


PresetandClear

Connection Diagram

Pin Assignments for DIP, SOIC, SOP and TSSOP

Top View

Truth Table

Note:

Q0 =

the level of Q before the indicated input conditionswere established.

1. This configuration is nonstable; that is, it will not persistwhen preset and clear inputs return to their inactive(HIGH) level.

Logic Diagram

Inputs Outputs

PR CLR CLK D Q Q

L H X X H L

H L X X L H

L L X X H

(1)

H

(1)

H H

H H L

H H

L L H

H H L X Q0 Q0


8/17


MM74HC74A


PresetandClear

Absolute Maximum Ratings

(2)

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or beoperable above the recommended operating conditions and stressing the parts to these levels is not recommended.In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.The absolute maximum ratings are stress ratings only.

Notes:

2. Unless otherwise specified all voltages are referenced to ground.

3. Power Dissipation temperature derating plastic N package: 12mW/C from 65C to 85C.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommendedoperating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does notrecommend exceeding them or designing to absolute maximum ratings.

Symbol Parameter Rating

V

CC

Supply Voltage 0.5 to +7.0V

V

IN

DC Input Voltage 1.5 to V

CC

+1.5V

V

OUT

DC Output Voltage 0.5 to V

CC

+0.5V

I

IK

, I

OK

Clamp Diode Current 20mA

I

OUT

DC Output Current, per pin 25mA

I

CC

DC V

CC

or GND Current, per pin 50mA

T

STG

Storage Temperature Range 65C to +150C

P

D

Power Dissipation

Note 3 600mW

S.O. Package only 500mW

T

L

Lead Temperature (Soldering 10 seconds) 260C

Symbol Parameter Min. Max. Units

V

CC

Supply Voltage 2 6 V

V

IN

, V

OUT

DC Input or Output Voltage 0 V

CC

V

T

A

Operating Temperature Range 40 +85 C

t

r

, t

f

Input Rise or Fall Times

V

CC =

2.0V 1000 ns

V

CC =

4.5V 500 ns

V

CC =

6.0V 400 ns


9/17


MM74HC74A


PresetandClear

DC Electrical Characteristics

(4)

Note:

4. For a power supply of 5V 10% the worst case output voltages (V

OH

, and V

OL

) occur for HC at 4.5V. Thus the 4.5Vvalues should be used when designing with this supply. Worst case V

IH

and V

IL

occur at V

CC =

5.5V and 4.5Vrespectively. (The V

IH

value at 5.5V is 3.85V.) The worst case leakage current (I

IN

, I

CC

, and I

OZ

) occur for CMOS atthe higher voltage and so the 6.0V values should be used.

Symbol Parameter V

CC

(V) Conditions

T

A =

25C

T

A

=

40C

to 85C

T

A =

55C

to 125C

UnitsTyp. Guaranteed Limits

V

IH

Minimum HIGH

Level InputVoltage

2.0 1.5 1.5 1.5 V

4.5 3.15 3.15 3.15

6.0 4.2 4.2 4.2

V

IL

Maximum LOWLevel InputVoltage

2.0 0.5 0.5 0.5 V

4.5 1.35 1.35 1.35

6.0 1.8 1.8 1.8

V

OH

Minimum HIGHLevel OutputVoltage

2.0 V

IN =

V

IH

or V

IL

,

|I

OUT

|

20A

2.0 1.9 1.9 1.9 V

4.5 4.5 4.4 4.4 4.4

6.0 6.0 5.9 5.9 5.9

4.5 V

IN =

V

IH

or V

IL

,

|I

OUT

|

4.0mA

4.3 3.98 3.84 3.7

6.0 V

IN=

V

IH

or V

IL

,|I

OUT

|

5.2mA 5.2 5.48 5.34 5.2

V

OL

Maximum LOWLevel OutputVoltage

2.0 V

IN =

V

IH

or V

IL

,

|I

OUT

|

20A

0 0.1 0.1 0.1 V

4.5 0 0.1 0.1 0.1

6.0 0 0.1 0.1 0.1

4.5 V

IN =

V

IH

or V

IL

,

|I

OUT

|

4.0mA

0.2 0.26 0.33 0.4

6.0 |V

IN =

V

IH

or V

IL

,

I

OUT

|

5.2mA

0.2 0.26 0.33 0.4

I

IN

Maximum Input

Current

6.0 V

IN =

V

CC

or GND 0.1 1.0 1.0 A

I

CC

MaximumQuiescent

Supply Current

6.0 V

I N=

V

CC

or GND,I

OUT =

0A 4.0 40 80 A


10/17


MM74HC74A


PresetandClear

AC Electrical Characteristics

V

CC =

5V, T

A

=

25C, C

L

=

15pF, t

r=

t

f=

6ns

Symbol Parameter Conditions Typ.

Guaranteed

Limit Units

f

MAX

Maximum Operating Frequency 72 30 MHz

t

PHL

, t

PLH

Maximum Propagation,Delay Clock to Q or Q

10 30 ns

t

PHL, tPLH Maximum Propagation,

Delay Preset or Clear to Q or Q

17 40 ns

tREM Minimum Removal Time,

Preset or Clear to Clock

6 5 ns

ts Minimum Setup Time, Data to Clock 10 20 ns

tH Minimum Hold Time, Clock to Data 0 0 ns

tW Minimum Pulse Width Clock, Preset or Clear 8 16 ns


11/17


MM74HC74A


PresetandClear

AC Electrical CharacteristicsCL = 50 pF, tr= tf= 6ns (unless otherwise specified)

Note:5. CPD determines the no load dynamic power consumption, PD = CPD VCC

2 f + ICC VCC, and the no load dynamiccurrent consumption, IS = CPD VCC f + ICC.

Symbol Parameter Conditions VCC (V)

TA = 25C

TA=40C

to 85C

TA = 55C

to 125C


fMAX Maximum OperatingFrequency

2.0 22 6 5 4 MHz4.5 72 30 24 20

6.0 94 35 28 24

tPHL, tPLH Maximum Propagation

Delay Clock to Q or Q

2.0 34 110 140 165 ns

4.5 12 22 28 33

6.0 10 19 24 28

tPHL, tPLH Maximum Propagation

Delay Preset or Clear

to Q or Q

2.0 66 150 190 225 ns

4.5 20 30 38 45

6.0 16 26 33 38

tREM Minimum RemovalTime, Preset or Clear

to Clock

2.0 20 50 65 75 ns

4.5 6 10 13 156.0 5 9 11 13

ts Minimum Setup Time

Data to Clock

2.0 35 80 100 120 ns

4.5 10 16 20 24

6.0 8 14 17 20

tH Minimum Hold Time

Clock to Data

2.0 0 0 0 ns

4.5 0 0 0

6.0 0 0 0

tW Minimum, Pulse Width

Clock, Preset or Clear

2.0 30 80 101 119 ns

4.5 9 16 20 24

6.0 8 14 17 20

tTLH, tTHL Maximum Output

Rise and Fall Time

2.0 25 75 95 110 ns

4.5V 7 15 19 22

6.0V 6 13 16 19

tr, tf Maximum Input Rise

and Fall Time

2.0 1000 1000 1000 ns

4.5 500 500 500

6.0 400 400 400

CPD Power Dissipation

Capacitance(5)(per flip-flop) 80 pF

CIN Maximum Input

Capacitance

5 10 10 10 pF


12/17

MM74HC02

Quad2-InputNORGate

1983 Fairchild Semiconductor Corporation www.fairchildsemi.comMM74HC02 Rev. 1.3.0

February 2008

MM74HC02

Quad 2-Input NOR Gate

Features

Typical propagation delay: 8ns

Wide power supply range: 2V6V

Low quiescent supply current: 20A maximum(74HC Series)

Low input current: 1A maximum

High output current: 4mA minimum

General Description

The MM74HC02 NOR gates utilize advanced silicon-gate CMOS technology to achieve operating speedssimilar to LS-TTL gates with the low power consumptionof standard CMOS integrated circuits. All gates havebuffered outputs, providing high noise immunity and theability to drive 10 LS-TTL loads. The 74HC logic family isfunctionally as well as pin-out compatible with the stan-dard 74LS logic family. All inputs are protected fromdamage due to static discharge by internal diode clamps

to V

CC

and ground.

Ordering Information

Device also available in Tape and Reel except for N14A. Specify by appending suffix letter X to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Connection Diagram

Pin Assignment for DIP, SOIC, SOP and TSSOP

Top View

Logic Diagram

Order Number

Package

Number Package Description

MM74HC02M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

MM74HC02SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC02MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HC02N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide


13/17

1983 Fairchild Semiconductor Corporation www.fairchildsemi.comMM74HC02 Rev. 1.3.0 2

MM74HC02

Quad2-InputNORGate

Absolute Maximum Ratings

(1)

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or beoperable above the recommended operating conditions and stressing the parts to these levels is not recommended.In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.The absolute maximum ratings are stress ratings only.

Notes:

1. Unless otherwise specified all voltages are referenced to ground.

2. Power Dissipation temperature derating plastic N package: 12mW/C from 65C to 85C.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommendedoperating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does notrecommend exceeding them or designing to absolute maximum ratings.

Symbol Parameter Rating

V

CC

Supply Voltage 0.5 to +7.0V

V

IN

DC Input Voltage 1.5 to V

CC

+1.5V

V

OUT

DC Output Voltage 0.5 to V

CC

+0.5V

I

IK

, I

OK

Clamp Diode Current 20mA

I

OUT

DC Output Current, per pin 25mA

I

CC

DC V

CC

or GND Current, per pin 50mA

T

STG

Storage Temperature Range 65C to +150C

P

D

Power Dissipation

Note 2 600mW

S.O. Package only 500mW

T

L

Lead Temperature (Soldering 10 seconds) 260C

Symbol Parameter Min. Max. Units

V

CC

Supply Voltage 2 6 V

V

IN

, V

OUT

DC Input or Output Voltage 0 V

CC

V

T

A

Operating Temperature Range 40 +85 C

t

r

, t

f

Input Rise or Fall Times

V

CC =

2.0V 1000 ns

V

CC =

4.5V 500 ns

V

CC =

6.0V 400 ns


14/17


MM74HC02

Quad2-InputNORGate

DC Electrical Characteristics

(3)

Note:

3. For a power supply of 5V 10% the worst case output voltages (V

OH

, and V

OL

) occur for HC at 4.5V. Thus the 4.5Vvalues should be used when designing with this supply. Worst case V

IH

and V

IL

occur at V

CC =

5.5V and 4.5Vrespectively. (The V

IH

value at 5.5V is 3.85V.) The worst case leakage current (I

IN

, I

CC

, and I

OZ

) occur for CMOS atthe higher voltage and so the 6.0V values should be used.

Symbol Parameter V

CC (V) Conditions

T

A =

25C

T

A=

40C

to 85C

T

A =

55C

to 125C


V

IH

Minimum HIGH Level

Input Voltage

2.0 1.5 1.5 1.5 V

4.5 3.15 3.15 3.15

6.0 4.2 4.2 4.2

V

IL

Maximum LOW LevelInput Voltage

2.0 0.5 0.5 0.5 V

4.5 1.35 1.35 1.35

6.0 1.8 1.8 1.8

V

OH

Minimum HIGH LevelOutput Voltage

2.0 V

IN =

V

IL

,|I

OUT

|

20A2.0 1.9 1.9 1.9 V

4.5 4.5 4.4 4.4 4.4

6.0 6.0 5.9 5.9 5.9

4.5 V

IN =

V

IL

,|I

OUT

|

4.0mA4.2 3.98 3.84 3.7

6.0 V

IN=

V

IL

,|I

OUT

|

5.2mA5.7 5.48 5.34 5.2

V

OL

Maximum LOW LevelOutput Voltage

2.0 V

IN =

V

IH

or V

IL

,|I

OUT

|

20A0 0.1 0.1 0.1 V

4.5 0 0.1 0.1 0.1

6.0 0 0.1 0.1 0.1

4.5 V

IN =

V

IH

or V

IL

,|I

OUT

|

4.0mA0.2 0.26 0.33 0.4

6.0 V

IN =

V

IH

or V

IL

,|I

OUT

|

5.2mA0.2 0.26 0.33 0.4

I

IN

Maximum InputCurrent

6.0 V

IN =

V

CC

or GND 0.1 1.0 1.0 A

I

CC

Maximum Quiescent

Supply Current

6.0 V

IN =

V

CC

or GND,

I

OUT =

0A

2.0 20 40 A


15/17


MM74HC02

Quad2-InputNORGate

AC Electrical CharacteristicsV

CC

=

5V, T

A

=

25C, C

L

=

15pF, t

r

=

t

f

=

6ns

AC Electrical CharacteristicsV

CC

=

2.0V to 6.0V, C

L

=

50pF, t

r

=

t

f

=

6ns (unless otherwise specified)

Note:

4. C

PD

determines the no load dynamic power consumption, P

D =

C

PD

V

CC2

f + I

CC VCC, and the no load dynamiccurrent consumption, IS = CPD VCC f + ICC.

Symbol Parameter Conditions Typ.

Guaranteed

Limit Units

tPHL, tPLH Maximum Propagation Delay 8 15 ns

Symbol Parameter VCC (V) Conditions

TA = 25C

TA = 40C

to 85C

TA = 55C

to 125C


tPHL, tPLH Maximum

Propagation Delay

2.0 45 90 113 134 ns

4.5 9 18 23 27

6.0 8 15 19 23

tTLH, tTHL Maximum OutputRise and Fall Time 2.0 30 75 95 110 ns4.5 8 15 19 22

6.0 7 13 16 19

CPD Power DissipationCapacitance(4)

(per gate) 20 pF

CIN Maximum Input

Capacitance

5 10 10 10 pF


16/17

Solutions

Question 1

(a) Noise margins areOH IH

V V 0.6 V- = andIL OL

V V 0.5 V- = .

(b) Suppose gate output is 1. It then follows the fan-out is

3OH

6IH

I 1 10I 50 10

20-

--

= =

If gate output is 0, then fan-out is

3OL

3IL

I 8 10I 0.6 10

13.33-

-

- = =

The fan-out of the family is, therefore, 13.33 rounded down to 13.

Question 2

The Q output of the leftmost flip-flop goes through two NOR gates before it reaches

the D input of the rightmost flip-flop. The clock period of the circuit must satisfy,

therefore,

PHL PLH PHL PLH SUD-F/F NOR D-F/Fmax ( , ) 2 max ( , )T t t t t t > + +

i.e 30 2 15 20 80 nsT > + + =

Or in other words, the clock frequency must satisfy

1 112.5 MHz

80 nsf

T= < =

Observe that f is lower than the maximum operating frequency of the flip-flop

(30 MHz). The maximum clock frequency at which the circuit can operate reliably is

thus 12.5 MHz.

Question 3

(a) In DC analysis, an inductor is essentially a short circuit and a capacitor an open

circuit. The required current is given, therefore, by

( ) 10

( ) 0.1 A100= = =

v t

i t R


17/17

(b) In phasor notation, let 010 V= jv e and Aji Ie f= such that

vi

Z=

where Z is the impedence of the circuit as seen by the voltage source.

Now,

1

1

2

2

2 2

2 6

6 2 6 2

1

1

(1 )

( ) 1

( ) 1 ( ) 1

100 100 100 10

(100 100 100 10 ) 1 (100 100 100 10 ) 1100 1

50 50

w

ww

w

w

w

w w

w w

w

w

w

-

- -

+

+

-

+

+ +

+ +

= + = +

= +

= +

= + -

= + -

= +

j C

j C

R

j C R

Rj RC

R j RC

RC

R CRRC RC

Z j L R j L

j L

j L

j L

j

j

Therefore, the current phasor is

4510 0.141450 50

- = = =+

jvi eZ j

and the input current waveform is

( ) 0.1414cos(100 45 ) A= - i t t

mid semester 2012 tid203

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