microprocessor history1

7/29/2019 Microprocessor History1

1/40

Microprocessor History


2/40

PMOS technology slow and awkward to

interface with TTL family

4 bit processor

Instructions were executed in about 20 s.

Intel 4004 the first MP. 4K nibbles address

space.

Intel 8008- can manipulate a whole byte. 16Kbytes address space

50,000 operations/second.

Early microprocessors


3/40

N-channel MOSFET

1970.

Faster than P-MOS.

Work with +ve supply; easy to interface with

TTL. 1973 Intel 8080 MP.

500,000 operations/second.

64K bytes memory.

Upward software compatible with 8008.

Other brands are MC6800, Fairchilds F-8 etc.


4/40

Basic types of MP

Two types

Single component microprocessors

Bit sliced microprocessors

Can be cascaded to allow functioning systems with

word size from 4 bits to 200 bits.


5/40

Single component M Computer

Composed of

A processor

read only memory (for program storage)

Read/Write memory (for data storage)

Input/output connections for interfacing

Timer as event counter

Intel 8048, Motorola 6805R2.

Oven, washing machine, dish washer etc.


6/40

Modern MP

8, 16, 32, 64 bits are available.

Intel 8085, Motorola 6800 8 bit word 16 bitaddress.

Intel 8088, 8086, Motorola 68000 16 bits word,20 bits address.

80186 never used.

286 real mode and protected mode; 16MB

memory 386 paging, 4GB memory, 32 bits word

486 math coprocessor, L1 cache


7/40

Modern MP

Pentium 64 bits i/o off the chip but process 32bits word, exception floating

point processed 64 bits, cache doubled, instruction pipelining.

Pentium Pro L2 cache, Improved pipelining

Pentium MMX Multi-Media extensions, 57 new inter instruc mostly used for

multimedia programming

Pentium II, III, IV Pentium pro with MMX tech, increased L2 cache, full 64 bit

operation RISC

Reduced instruction set processor, uniform length instruc, fasterin operation, cannot perform may different thing as CISC.


8/40

Basic MP architecture

Fetch, decode,

execute.

PC increment.

First instruction

is a fetch

0000H for 8085

FFFF0H for

8086, 8088

RegisterA

rray

control

Instruction

RegisterA

LU

Data Bus

Address Bus

Control

Bus

AF,

BC,

DE,HL,

SP,

PC

many

more


9/40

Memory Interfacing and IOdecoding


10/40

Interfacing needs bus

Isolation and separation of signals from

different devices connected to MP.

Unidirectional

Bidirectional

LS373, 244


11/40

Memory map

Pictorial representation of the whole range

of memory address space.

Defines which memory system is where, their

sizes etc.

Address space or range.

8086 has 1M address space in minimum

mode.

8085 has 64K address sspace.


12/40

Address Decoding

Address decoder is a digital ckt that indicates

that a particular area of memory is being

addressed, or pointed to, by the MP.

Absolute address decoding Decode an address to one single output

Decode 10110 so that u can get a signal from the

decoder when it receives exactly that bit pattern.

Partial address decoding

Some bits are used as dont care so that decoder

gives a signal for a range of consecutive bit patterns.


13/40

1 0 1 1 0 10

11

0

a b c d e

a b c d e

Can use decoder IC with gates to

achieve exact decoded o/p

Logic 1

8 input NAND gate implementation

Active low o/p signal

Absolute decoding

3to8linedcd

10

1

0

7

o/p


14/40

Partial decoding

When a range of addresses are deconded then it is called partial

decoding. For example, if we need to generate a control signal for

an address generated by the MP within the range FFF0 FFFF,

then it is called partial decoding.

Decoder, multiplexer can be used for address decoding

1 1 1 1 1 1 1 1 1 1 1 1 x x x x

A15

A14

A4


15/40

Internal architecture of 8085

ALU


16/40

Flag register

S Z AC P CY 1. S : after the execution of an

arithmetic operation, if bit 7 of

the result is 1, then sign flag is

set.

2. Z : bit is set if ALU operation

results a zero in the Acc orregisters.

3. AC: bit is set, when a carry is

generated by bit 3 and passed

on bit 4.

4. P: parity bit is set when the

result has even number of 1s.5. CY = carry is set when result

generates a carry. Also a

borrow flag.


17/40

Accumulator

Hold data for manipulation (arithmetic, logical).

Whenever the operation combines two words,either arithmetically or logically, the accumulator

contains one word (say A) and the otherword(say B) may be contained in a register or inmemory location. After the operation the result isplaced in the Acc replacing the word A.

Major working register. MP can directly work onAcc.

Programmed data tranfer.


18/40

General purpose registers

Six registers.

B, C, D, E, H and L can store 8 bit data.

They can be combined to perform some

16 bit operation.


19/40

ALU

Arithmetic logic unit.

Two input ports, one output port.

Perform AND, OR, ExOR, Add, subtract,

complement, Increment, Decrement, shift left,shift right.

ALUs two temporary registers are connected to

MPs internal bus from which it can take datafrom any registers. It can place data directly to

data bus through its single output port.


20/40

Program counter

Its job is to keep track of what instruction is

being used and what the next instruction will be.

For 8085 it is 16 bit long.

Can get data from internal bus as well asmemory location.

PC automatically increments to point to the next

memory during the execution of the presentinstruction.

PC value can be changed by some instructions.


21/40

Stack pointer

16 bit register acts as memory pointer.

Can save the value of the program counter

for later use.

points to a region of memory which is

called stack. follows LIFO algorithm.

After every stack operation SP points tonext available location of the stack.

Usually decrements.


22/40

Memory address register

PC sends address to MAR. MAR points to the

location of the memory where the content is to

be fetched from.

PC increments but MAR does not. If the content is an instruction, IR decodes it.

During execution if it is required to fetch another

word from memory, PC is loaded with the value

PC again sends it to the MAR and fetch

operation starts.


23/40

Instruction register

Holds instruction the micro is currently

being executed.

8 bit long.


24/40

others

Instruction decoder.

Control logic.

Internal data bus.


25/40

8085

40 pin DIP.

+5V

3 - 5MHz ADD BUS DATA BUS

CONTROL STATUS

POWER SUPPLY AND

FREQ

EXTERNALLY INITIATED

SIGNALS

SERIAL I/O PORTS

21 28HIGH ORDER

ADD BUS

5V GND

30 ALE

29 S0

33 S1

34 IO/M

32 RD

31 WR

CLK OUTRESET OUT

HLDA 38

INTA 11

RESET IN 36

HOLD 39

READY 35

INTR 10

RST5.5 9

RST6.5 8RST7.5 7

TRAP 6

SOD 4

SID 5

12 19

MUX ADD/DATA BUS

2040

X1 X2

3 37


26/40

Address bus 16 bits

A8 to A15 unidirectional. Higher 8 bit

AD0 to AD7 multiplexed with data. This pins

are bidirectional when used as data bus.

Data bus 8 bit long: AD0 to AD7

ADD/DATA bus

Data bus

D

G

Q

OC

AD7AD6AD

5

AD0

ALE

GND

Address bus.

Lower 8 bit

Address bus.

higher 8 bit

A8

A15


27/40

Control signals

ALE active high output

used to latch the lower 8

address bits.

RD, WR - active low

output signals.

IO/M output signal to

differentiate memory and

IO operation.

S1 and S0 status output

signal. Identify various

operations.

Machine

cycle

IO/M S1 S0 Control

signals

Opcode

fetch

0 1 1 RD=0

Memory

read

0 1 0 RD=0

Memorywrite

0 0 1 WR=0

I/O read 1 1 0 RD=0

I/O write 1 0 1 WR=0

Interrupt

Ackn

1 1 1 INTA=0

Halt Z 0 0 RD,

WR =Z

and

INTA=1

Hold Z X X

Reset Z X X


28/40

External control signals

INTR interrupt request. Input signal

INTA interrupt acknowledge. o/p signal.

RST7.5,RST 6.5, RST5.5 restart interrupts.

Vectored interrupts. Higher priority. TRAP - Nonmaskable interrupt. Highest priority.

Hold request for the control of buses. O/Psignal

HLDA Hold Acknowledge. I/P signal READY I/P signal. When low Mp waits for

integral number of clock cycles until it goes high.


29/40

Bus control signals

8085

IO/M

RD

WR

MEMR

MEMWR

IOWR

IOWR


30/40

8080 functional block diagram

W

Temp Reg (8)

Z

Temp Reg (8)

H

(8)

L

(8)

B

(8)

C

(8)

D

(8)

E

(8)

Stack pointer

(16)

Program counter (16)

Incrementer/decrementer

Latch (16)

RegSelect

MUX

Address buffer (8) Data/Add buffer (8)

Instru

Register (8)

Instru

DecoderFlags

Accumu Temp Reg

Timing & control

Interrupt control Serial I/O control


31/40

Timing diaga. of Memory cycle

CLK

A15-A8

AD7-AD0

IO/M

RD

MEMRD

A7-A0 A7-A0Data from

MPU

Data from

memory

WR

MEMWR

T1 T2 T3

ALE

T1 T2 T3

READ CycleWRITE Cycle


32/40

Interfacing A Memory Chip

Memory

Chip

3 to 8

decoder

E1 E2 E3

A15A14IO/M

A13

A12

A11Q1

CEA10

A9

A0

D7

D0

D6

RD

WR

A15A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

2K Byte memory

Memory address space of the chip:

8800H to 8FFFH

1 0 0 0 1 X X X X X X X X X X X

MEMSEL

8 8 - F 0 - F 0 - F


33/40

MVI A,32H Instruction2000H 3EH ;MVI A, 32H

2001H 32H

00H; low-

order Add3E; opcode

T1 T2 T3 T4 T1 T2 T3

20H; high-order address

01H; low-

order Add32H; Data

Unspecified 20H; High-order address

Status IO/M=0,S1=1,S0=1; opcode fetch Status IO/M=0,S1=1,S0=0; data read

RD

ALE

AD7-AD0

A15-A8

M1 (Opcode-fetch) M2 (Memory Read)


34/40

OUT/IN instruction

port address: 50H

2050 D3

2051 50 Let input port address is 30H

2150 DB

2151 30

OUT 50H sends acc content to I/O address 50H

IN 30H reads content from I/O address 30H and

stores the value in accum


35/40

IN 30H instruction

50H DB frommemory

21H Port add 30H

Data fromAccumula

T1 T2 T3 T4 T1 T2 T3 T1 T2 T3

21Hunspec

ified

Port addre30H

51H Port add30H

IO/M

M1 M2 M3

RD

MEMRD

IORD

ALE

AD7-AD0

A15-A8

CLK


36/40

T1 T2 T3 T4 T1 T2 T3 T1 T2 T3

20H Port add, 50H20Hunspec

ified

IO/M

OUT 50H instruction

M1 M2 M3

50H Port addre50H Data fromAccumula51H Port add50HOpcodeD3

RD

MEMRD

IORD

ALE

AD7-AD0

A15-A8

CLK

IOWR


37/40

Device selection & Data Transfer

Decode the IO address. Combine it with control

the signal to generate a

unique IO select pulse

that is generated onlywhen both signals are

asserted.

Use it to activate the IO

port

Address decoding can

be absolute or partial

Decoder

A

ddresslines

Enable

Databus

IOR or IOW

NOR

To

Peripherals

Latch

Or

Tri-state

Buffer


38/40

Interfacing LED for display

Given port add: FFH

Use octal latch as o/p port.

Steps for IO select pulse: Decode FF

Use IO/M to make the port output only

Use WR signal to write data to the port


39/40

IO/M

A7

A0 Q7

A10

A9

A0

+5 V

WR

IOSEL

A1

G

OE

D FF

MVI A, data

OUT FFH

HLT

* To interface a 7-segment display

you need to decide about the type of

7-segment: common anode orcommon cathode

* Power supply connection to the LED

segments will be opposite.

* For common cathode a 0 is sent to

the respective pin to lit it up.


40/40

Interfacing DIP switches

Let port address: 07H

00H

Partial decoding

Must use pull-upresistors.

IN 07H instruction reads

a byte into accumulator

from port 07H

3 to 8

decoder

E1 E2 E3

IO/M

A7

A5

Q0

D0

+5 V

RD

IOSELA6

OE

A4 A3

D1

D7

microprocessor history1

Documents