microprocessor evolution and architecture · pdf fileintel 8088 processor 16k memory 5...
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Prof. Fayez F. M. El-Sousy 1
Prof. Fayez F. M. ElProf. Fayez F. M. El--SousySousy
Department of Electrical EngineeringDepartment of Electrical Engineering
College of EngineeringCollege of Engineering
SalmanSalman bin bin AbdulazizAbdulaziz UniversityUniversity
AlAl--KharjKharj, Saudi Arabia, Saudi Arabia
Microprocessor Evolution Microprocessor Evolution
and Aand Architecturerchitecture
Prof. Fayez F. M. El-Sousy 2
Year name Data memory #instructions
size size
1971 4004 4 4096 4-bit 45 first microprocessor
1973 8008 8 16K bytes 48 1st 8-bit µµµµP
1973 8080 8 64K bytes 10 times faster than 8008
1973 MC6800 8 64K bytes 1st Motorola µµµµP
1977 8085 8 64K bytes 246 Intel’s most successful 8-bit
general- purpose µµµµP due to its
low cost Zilog’s Z808
most successful microprocessor
1978 8086 8,16 1M bytes >20,000 1st 16-bit µµµµP
1979 8088 8,16 1M bytes prefetch instruction using cache
1981 IBM decided to use 8088 in its personal computer
1983 80286 8,16 16M
1986 80386 8,16,32 4G
1989 80486 8,16,32 4G
1993 Pentium 8,16,32 4G
1995 Pentium Pro 64 64G
1997 Pentium II 64 64G
1999 Pentium III
2000 Pentium 4
Prof. Fayez F. M. El-Sousy 3
MicroprocessorMicroprocessor--Based Computer SystemBased Computer System
µµµµP
Read-Only
Memory
(ROM)
Keyboard
Address bus
Data bus
IOWC
MWTC
IORC
MRDC
Read-Write
Memory
(RAM)
Printer
Prof. Fayez F. M. El-Sousy 4
Microprocessors: CPU on a ChipMicroprocessors: CPU on a Chip
� 1968: INTEL (Integrated Electronics)
� Founded by Robert Noyce and Gordon Moore (Fairchild).
� Original goals: semiconductor memory market
� 1969: customized IC’s for Busicom for calculator.
� Ted Hoff and Stan Mazor: proposed 4-bit CPU on a single chip, plus ROM, RAM chips.
Prof. Fayez F. M. El-Sousy 5
� 1971: 4000 Family
� By Fredrico Faggin
� 4001: 2K ROM with 4-bit I/O port
� 4002: 320-bit RAM, 4-bit output port
� 4003: 10-bit serial-in parallel-out shift register
� 4004: 4-bit processor
�Processor-on-a-chip: Micro-processor
Microprocessors: CPU on a ChipMicroprocessors: CPU on a Chip
Prof. Fayez F. M. El-Sousy 6
� 1972: 8008, 8-bit
� 1974: 8080, an improved version
Microprocessors: CPU on a ChipMicroprocessors: CPU on a Chip
Prof. Fayez F. M. El-Sousy 7
Microprocessors: CPU on a ChipMicroprocessors: CPU on a Chip
� 8-bit CPUs
� 16-bit address (64K)
�MC6800: Motorola
�6502: MOS Technology (spin-off from Motorola)
o Apple-II, Apple DOS
�Z-80: Zilog (spin-off from Intel)
o Z-80 cards on Apple-II, CP/M
Prof. Fayez F. M. El-Sousy 8
� 16-bit CPUs (Late 1970s)
�8086, 80186, 80286: Intel
• PC, PC-DOS, MS-DOS, SCO-Unix
�MC68000: Motorola
• 16-bit instructions
o Hardware multiply and divide
o 20-bit address buses (1MB)
o Workstations: Sun3
Microprocessors: CPU on a ChipMicroprocessors: CPU on a Chip
Prof. Fayez F. M. El-Sousy 9
Microprocessors: CPU on a ChipMicroprocessors: CPU on a Chip
� 32-bit CPUs
� 80386, 80486: Intel
� MC68020, 68030: Motorola
� 64-bit CPUs
� Pentium, Pentium Pro (64-bit external data bus, 32-bit internal registers, not recognized as 64-bit CPUs in terms of internal register word length)
Prof. Fayez F. M. El-Sousy 10
Computers Based on MicroprocessorsComputers Based on Microprocessors
� 1975: MITS Altair 8800 (Kit)
� $399, i8080, programmed by depositing 1s/0s via front panel switches
� Other Computers boom
� 8080: MITS, …
� 6800: SWTPC 6800, …
� Z-80: TRS-80, …
� 6502: Apple I, 8K, programmed with BASIC
� Steve Jobs & Steve Wozniak, millionaires from PC COM’s …
Prof. Fayez F. M. El-Sousy 11
Personal Computers:Personal Computers:
� 1982: IBM PC
� A system board (mother board)
� Intel 8088 processor
� 16K memory
� 5 expansion slots
� Third-party vendors to supply various IO adapter cards
� Open architecture
� Computer with interchangeable components
Prof. Fayez F. M. El-Sousy 12
MicroMicro--controllers: Microcomputers controllers: Microcomputers
on a Chipon a Chip
� Microcontroller: a computer on a chip
� Microprocessor, plus
� On-chip memory, plus
� Input/output ports
� 1995: microcontrollers out sold microprocessors 10:1
� embedded on various equipments:
� Thermostat, machine tools, communication, automotive, …
� Evolution: getting greater IO capabilities
� Intel: MCS-51, MCS-96, …
Prof. Fayez F. M. El-Sousy 13
Summary of Processor HistorySummary of Processor History
� 1940s: Vacuum tube, large and consuming large power
� 1950s: Transistor (1948-)
� 1959: First IC (second industrial revolution)
� 1960s: IC was popular to build CPU’s.
� 1971: Intel 4004 microprocessor (2300 transistors)
� Starts of the microprocessor age
� Late 1970’s: 8080/85
Prof. Fayez F. M. El-Sousy 14
Summary of Processor HistorySummary of Processor History
� 1980: RISC (reduced instruction set computer)
� CISC (complicated instruction set computer) vs. RISC
� CISC family: Intel 80x86, Pentium; Motorola 68000 series
� All others are RISC series.
Prof. Fayez F. M. El-Sousy 16
Program DevelopmentProgram Development
ProgramProgram
AssemblerAssembler LinkerLinker
Symbol
Converter
Symbol
Converter ICEICE
TargetTarget
.ASM .OBJ.HEX
.SYM
.SDT
(X8051) (Link)
(CVTSYM)
EditorEditor
Prof. Fayez F. M. El-Sousy 17
The 8086 and 8088The 8086 and 8088
� Processor Model
� Programming Model
Prof. Fayez F. M. El-Sousy 18
8086/8088 Processor Model:8086/8088 Processor Model:
� Became available in 1978
� 16-bit data bus
� 20-bit address bus (was 16-bit for 8080)
� memory organization: 16 segments of 64KB (1 MB limit)
� Re-organize CPU into BIU (bus interface unit) and EU (execution unit)
� Allow fetch and execution simultaneously
� Internal register expanded to 16-bit
� Allow access of low/high byte separately
Prof. Fayez F. M. El-Sousy 19
8086/8088 Processor Model :8086/8088 Processor Model :
� Became available in 1979, almost identical to 8086
� 8-bit data bus: for hardware compatibility with 8080
� 16-bit internal registers and data bus (same as 8086)
� 20-bit address bus (was 16-bit for 8080)
�BIU re-designed
� memory organization: 16 segments of 64KB (1 MB limit)
�Two memory accesses for 16-bit data (less efficient)
�But less cost
� 8088: used by IBM PC (1982), 16K-64K, 4.77MHz
Prof. Fayez F. M. El-Sousy 20
8086/8088 Processor Model :8086/8088 Processor Model :
BH BLAH AL
DH DLCH CL
BPDISISP
ALU
Flags
CSESSSDSIP
ΣΣΣΣ
Address Generation
and Bus ControlIn
structio
n Q
ueu
eEU BIU
BH BLAH AL
DH DLCH CL
BPDISISP
BH BLAH AL
DH DLCH CLBH BLBH BLAH ALAH AL
DH DLDH DLCH CLCH CL
BPDISISP
ALUALU
Flags
CSESSSDSIP
CSESSSDSIP
ΣΣΣΣΣΣΣΣ
Address Generation
and Bus ControlIn
structio
n Q
ueu
eEU BIU
Prof. Fayez F. M. El-Sousy 21
8086/8088 Processor Model :8086/8088 Processor Model :
�Both 8086/80888086/8088 employ parallel processing
�Both 8086/80888086/8088 contain two processing units
�BIU: bus interface unit
�EU: execution unit
�Both units operate at the same time
�This parallel processing make the fetch and execution of instruction independent operation
Prof. Fayez F. M. El-Sousy 22
8086/8088 Processor Model :8086/8088 Processor Model :
Functions of the BIUFunctions of the BIU
� Interface to the external world
� Responsible for all external bus operations such as:
�Instruction fetch
�Memory Read/Write operations
�I/O Read/Write operations
�Instruction queuing and address generation
Prof. Fayez F. M. El-Sousy 23
8086/8088 Processor Model :8086/8088 Processor Model :
Inside the BIUInside the BIU
�� BIU Contains:BIU Contains:
� Segment registers (CS,DS,SS,ES )
� Instruction pointer (IP)
� Address generation adder
� Bus control logic
� 6 bytes Instruction Queue (FIFO)
Prof. Fayez F. M. El-Sousy 24
8086/8088 Processor Model :8086/8088 Processor Model :
Inside the EUInside the EU
�� EU Contains:EU Contains:
� ALU
� Status and control flags
� General purpose registers
� Temporary operand registers
Prof. Fayez F. M. El-Sousy 25
8086/8088 Processor Model :8086/8088 Processor Model :
Basic FunctionsBasic Functions of the EUof the EU
� Responsible for decoding and executing instructions
� Gets instructions from the output end of the Queue
� Accesses Data from general purpose Registers
� Check & update control flags
� Generate operand addresses if necessary
� Commands BIU for memory & I/O operations
Prof. Fayez F. M. El-Sousy 26
8086/8088 Processor Model: BIU+EU8086/8088 Processor Model: BIU+EU
��BIUBIU
�Memory & I/O address generation
��EUEU
�Receive codes and data from BIU
•Not connected to system buses
�Execute instructions
�Save results in registers, or pass to BIU, to memory and I/O
Prof. Fayez F. M. El-Sousy 27
8086/8088 Processor Model: 8086/8088 Processor Model: RegistersRegisters
Flag16Flag
IP16Instruction
CS, DS, SS, ES16Segment
SI, DI16Index
SP, BP16Pointer
AH, AL, BH, BL, CH, CL, DH, DL8
AX, BX, CX, DX16General
Register NamesRegister NamesBitsBitsCategoryCategory
Prof. Fayez F. M. El-Sousy 28
8086/8088 Processor Model: 8086/8088 Processor Model: RegistersRegisters
Extra Segment
64 k Byte
Stack segment
64 k Byte
Data Segment
64 K Byte
Code segment
64 k byte
External Memory Address Space
IP
SPBPSIDI
CSDSSSES
AH ALBHCHDH
BLCLDL
SR
Input / output Address space
00000
FFFFF
0000
FFFF
Prof. Fayez F. M. El-Sousy 29
8086/8088 Processor Model: 8086/8088 Processor Model: SegmentsSegments
� includes up to 64k bytes.
�starts on an address evenly divided by 16.
�each segment must be assigned a Base Address that identifies its starting point.
A segment is an area of memory that:A segment is an area of memory that:
Prof. Fayez F. M. El-Sousy 30
8086/8088 Processor Model: 8086/8088 Processor Model: SegmentsSegments
�Code Segment: contains the assembly instructions.
�Data Segment: used to store data that needs to be processed.
�Stack Segment: used for temp storage of data.
An assembly program consists of three An assembly program consists of three
segments:segments:
Prof. Fayez F. M. El-Sousy 31
8086/8088 Processor Model: 8086/8088 Processor Model: SegmentsSegments
�Memory is segmented into 64 KB segments.
�Only 4 of these segments can be activated at a time.
� The Code Segment
� The Stack Segment
� The Data Segment
� The Extra Segment
Segment Registers & Memory Segmentation:Segment Registers & Memory Segmentation:
Prof. Fayez F. M. El-Sousy 32
8086/8088 Processor Model: 8086/8088 Processor Model: SegmentsSegments
�The location of each segment is held by a register in the BIU.
� CS register holds Code Segment Address
� SS register holds Stack Segment Address
� DS register holds Data Segment Address
� ES register holds Extra Segment Address
Base Address for a Memory Segment:Base Address for a Memory Segment:
Prof. Fayez F. M. El-Sousy 33
8086/8088 Processor Model: 8086/8088 Processor Model: MemoryMemory
�Since only 4 segments can be activated at a time, then the total memory can be activated each time is:
� 4x64 = 256 KB
How much memory can be activated at a time?How much memory can be activated at a time?
Prof. Fayez F. M. El-Sousy 34
8086/8088 Processor Model: 8086/8088 Processor Model: MemoryMemory
� Three types of addresses:
� Physical address: 20 bit actually put on
the address lines.
� offset address: a location within a 64 KB
segment range.
� logical address: consists of a segment
value & an offset.
Logical & Physical Address:Logical & Physical Address:
Prof. Fayez F. M. El-Sousy 35
8086/8088 Processor Model: 8086/8088 Processor Model: MemoryMemory
Logical & Physical Address:Logical & Physical Address:
CS
ES
SS
DS
DataSegment
StackSegment
ExtraSegment
CodeSegment
Segment
Registers
System
Memory
• Segment Registers:
– Point to Base Address
• Index Registers:
– Contain Offset Value
• Notation (Segmented Address):
– CS:IP
– DS:SI
– ES:DI
– SS:BP
– SS:SP
00000 H
FFFFF H
Prof. Fayez F. M. El-Sousy 36
8086/8088 Processor Model: 8086/8088 Processor Model:
Memory SMemory Storage Organizationtorage Organization
• Organized as SEGMENTS
– Maximum segment size = 64KB
– (Since 16 bit offsets: 216 = 65,535 = 64KB)
• Maximum Memory Size:
– 220 = 1,048,576 = 1MB
• Newer Processors (386+) Can Utilize More Memory
– Wider address registers 32 bits
– 232 = 4,294,967,296 = 4GB
Prof. Fayez F. M. El-Sousy 37
8086/8088 Processor Model: 8086/8088 Processor Model: MemoryMemory
Logical & Physical Address:Logical & Physical Address:
CS
ES
SS
DS
DataSegment
StackSegment
ExtraSegment
CodeSegment
Segment
Registers
System
Memory00000 H
FFFFF H
• Logical, Segmented Address:
0FE6:012Bh
• Offset, Index Address:
012Bh
• Physical Address:
0FE60h → 65120
+ 012Bh → 299
0FF8Bh → 65149
Prof. Fayez F. M. El-Sousy 38
8086/8088 Processor Model: 8086/8088 Processor Model: MemoryMemory
Logical & Physical Address:Logical & Physical Address:
• Logical, Segmented Address 1:
DS:SI = 1234:4321
• Physical Address:
12340h → 74560
+ 4321h → 17185
16661h → 91745 • Logical, Segmented Address 2:
ES:DI = 1665:0011
• Physical Address:
16650h → 91728
+ 0011h → 00017
16661h → 91745
Prof. Fayez F. M. El-Sousy 39
8086/8088 Processor Model: 8086/8088 Processor Model: MemoryMemory
� In the code segment CS & IP hold the logical address for the instruction to be executed.
� The format is CS:IP
Logical & Physical Address in Code Segment:Logical & Physical Address in Code Segment:
physical address A0-A19=2E5F3IP=95F3
CS=2500 0Adder
Shift left CS one digit
Prof. Fayez F. M. El-Sousy 40
8086/8088 Processor Model: 8086/8088 Processor Model: MemoryMemory
� If CS =2567 and IP=2341
� The logical address 2567:2341
� The offset address :2341
� The physical address 279B1
Logical & Physical Address in Code Segment:Logical & Physical Address in Code Segment:
Prof. Fayez F. M. El-Sousy 41
8086/8088 Processor Model: 8086/8088 Processor Model: MemoryMemory
Logical & Physical Address in Stack Segment:Logical & Physical Address in Stack Segment:
physical address A0-A19=2E5F3SP=95F3
SS=2500 0Adder
Shift left SS one digit
� In the stack segment SS & SP hold the logical address to access the stack.
� The format is SS:SP
Prof. Fayez F. M. El-Sousy 42
CS
DS
SS
ES
AH
BH
CH
DH
AL
BL
CL
DL
IP
SP
BP
SI
DI
07
015
07
015
Accumulator
Base
Counter
Data
Code Segment
Data Segment
Stack Segment
Extra Segment
Instruction Pointer
Stack Pointer
Base Pointer
Source Index
Destination Index
}
}}
AX
BX
CX
DX
8086/8088 Programming Model8086/8088 Programming Model
Prof. Fayez F. M. El-Sousy 43
8086/8088 Programming Model8086/8088 Programming Model
General Purpose RegistersGeneral Purpose Registers
AH
BH
CH
DH
AL
BL
CL
DL
07 07
Accumulator
Base
Counter
Data
AX
BX
CX
DX
Prof. Fayez F. M. El-Sousy 44
8086/8088 Programming Model8086/8088 Programming Model
� Can Be Used Separately as 1-byte Registers
• AX = AH:AL
� Temporary Storage to Avoid Memory Access
�Faster Execution
�Avoids Memory Access
� Some Special uses for Certain Instructions
Prof. Fayez F. M. El-Sousy 45
8086/8088 Programming Model8086/8088 Programming Model
AX, AccumulatorAX, Accumulator
Main Register for Performing Arithmetic
MUL/DIV must use AH, AL
“accumulator” Means Register with Simple ALU
BX, BaseBX, Base
Point to Translation Table in Memory
Holds Memory Offsets; Function Calls
CX, CounterCX, Counter
Index Counter for Loop Control
DX, DataDX, Data
After Integer Division Execution - Holds Remainder
Prof. Fayez F. M. El-Sousy 46
CS
DS
SS
ES
IP
SP
BP
SI
DI
015
015
Code Segment
Data Segment
Stack Segment
Extra Segment
Instruction Pointer
Stack Pointer
Base Pointer
Source Index
Destination Index
}
}}
8086/8088 Programming Model8086/8088 Programming Model
CS, DS, ES, SS CS, DS, ES, SS -- Segment RegistersSegment Registers
IP, SP, BP, SI, DI IP, SP, BP, SI, DI -- Offset RegistersOffset Registers
Prof. Fayez F. M. El-Sousy 47
8086/8088 Programming Model8086/8088 Programming Model
CS, DS, ES, SS CS, DS, ES, SS -- Segment RegistersSegment Registers
Contains “Base ValueBase Value” for Memory Address
CS, Code SegmentCS, Code Segment
Used to “point” to Instructions
Determines a Memory Address (along with IP)
Segmented Address written as CS:IP
DS, Data SegmentDS, Data Segment
Used to “point” to Data
Determines Memory Address (along with other registers)
ES, Extra Segment allows 2 Data Address Registers
SS, Stack SegmentSS, Stack Segment
Used to “point” to Data in Stack Structure (LIFO)
Used with SP or BP
SS:SP or SS:BP are valid Segmented Addresses
Prof. Fayez F. M. El-Sousy 48
8086/8088 Programming Model8086/8088 Programming Model
IP, SP, BP, SI, DI IP, SP, BP, SI, DI -- Offset RegistersOffset Registers
Contains “Index ValueIndex Value” for Memory Address
IP, Instruction PointerIP, Instruction Pointer
Used to “point” to Instructions
Determines a Memory Address (along with CS)
Segmented Address written as CS:IP
SI, Source Index;SI, Source Index; DI, Destination IndexDI, Destination Index
Used to “point” to Data
Determines Memory Address (along with other registers)
DS, ES commonly used
SP, Stack Pointer;SP, Stack Pointer; BP, Base PointerBP, Base Pointer
Used to “point” to Data in Stack Structure (LIFO)
Used with SS
SS:SP or SS:BP are valid Segmented Addresses
Prof. Fayez F. M. El-Sousy 49
8086/8088 Programming Model8086/8088 Programming Model
x x x x OF DF IF TF SF ZF x AF x PF x CF
015
�Status and Control Bits Maintained in Flags Register Generally Set and Tested Individually.
� 9 1-bit flags in 8086; 7 are unused
Flags RegisterFlags Register
Prof. Fayez F. M. El-Sousy 50
8086/8088 Programming Model8086/8088 Programming Model
�� Flags (Status) RegisterFlags (Status) Register
�� Nine of its bits are implemented. Six of these Nine of its bits are implemented. Six of these
represent status flags: the carry flag (represent status flags: the carry flag (CFCF), parity ), parity
flag (flag (PFPF), auxiliary flag (), auxiliary flag (AFAF), zero flag (), zero flag (ZFZF), sign ), sign
flag (flag (SFSF), and overflow (), and overflow (OFOF). The logic state of ). The logic state of
these flags indicates conditions that are these flags indicates conditions that are
produced as the result of executing an produced as the result of executing an
instruction. instruction.
�� The summary of operation of these flags is given The summary of operation of these flags is given
below:below:
Prof. Fayez F. M. El-Sousy 51
8086/8088 Programming Model8086/8088 Programming Model
�� Flags (Status) RegisterFlags (Status) Register
�� Nine of its bits are implemented. Six of these Nine of its bits are implemented. Six of these
represent status flags: the carry flag (represent status flags: the carry flag (CFCF), parity ), parity
flag (flag (PFPF), auxiliary flag (), auxiliary flag (AFAF), zero flag (), zero flag (ZFZF), sign ), sign
flag (flag (SFSF), and overflow (), and overflow (OFOF). The logic state of ). The logic state of
these flags indicates conditions that are these flags indicates conditions that are
produced as the result of executing an produced as the result of executing an
instruction. instruction.
�� The summary of operation of these flags is given The summary of operation of these flags is given
below:below:
Prof. Fayez F. M. El-Sousy 52
8086/8088 Programming Model8086/8088 Programming Model
�� Flags (Status) RegisterFlags (Status) Register
�� Nine of its bits are implemented. Six of these Nine of its bits are implemented. Six of these
represent status flags: the carry flag (represent status flags: the carry flag (CFCF), parity ), parity
flag (flag (PFPF), auxiliary flag (), auxiliary flag (AFAF), zero flag (), zero flag (ZFZF), sign ), sign
flag (flag (SFSF), and overflow (), and overflow (OFOF). The logic state of ). The logic state of
these flags indicates conditions that are these flags indicates conditions that are
produced as the result of executing an produced as the result of executing an
instruction. instruction.
�� The summary of operation of these flags is given The summary of operation of these flags is given
below:below:
Prof. Fayez F. M. El-Sousy 53
8086/8088 Programming Model8086/8088 Programming Model
Flags RegisterFlags Register
� CF Carry Flag Arithmetic Carry/Borrow
� OF Overflow Flag Arithmetic Overflow
� ZF Zero Flag Zero Result; Equal Compare
� SF Sign Flag Negative Result; Non-Equal
Compare
� PF Parity Flag Even Number of “1” bits
� AF Auxiliary Carry Used with BCD Arithmetic
� DF Direction Flag Auto-Increment/Decrement
� IF Interrupt Flag Enables Interrupts
� TF Trap Flag Allows Single-Step
Prof. Fayez F. M. El-Sousy 54
8086/8088 Programming Model8086/8088 Programming Model
Flags RegisterFlags Register
Status FlagsStatus FlagsControl FlagsControl Flags
IFIFDFDFTFTF CFCFPFPFAFAFZFZFSFSFOFOF
Trap
Direction
Interrupt Enable
Overflow
Sign
ZeroAuxiliary CarryParity
Carry
Prof. Fayez F. M. El-Sousy 55
8086/8088 Programming Model8086/8088 Programming Model
Flags RegisterFlags Register
IFIFDFDFTFTF CFCFPFPFAFAFZFZFSFSFOFOF
Set whenever there is a carry out either from D7 or from D15
Prof. Fayez F. M. El-Sousy 56
8086/8088 Programming Model8086/8088 Programming Model
Flags RegisterFlags Register
IFIFDFDFTFTF CFCFPFPFAFAFZFZFSFSFOFOF
For some operations ,set if the lowFor some operations ,set if the low--
order byte of the result has an EVEN order byte of the result has an EVEN
NUMBER of onesNUMBER of ones
Prof. Fayez F. M. El-Sousy 57
8086/8088 Programming Model8086/8088 Programming Model
Flags RegisterFlags Register
IFIFDFDFTFTF CFCFPFPFAFAFZFZFSFSFOFOF
set if there is a carry from D3 to D4set if there is a carry from D3 to D4
Prof. Fayez F. M. El-Sousy 58
8086/8088 Programming Model8086/8088 Programming Model
Flags RegisterFlags Register
IFIFDFDFTFTF CFCFPFPFAFAFZFZFSFSFOFOF
set if the result of arithmetic or logic set if the result of arithmetic or logic
operation is zerooperation is zero
Prof. Fayez F. M. El-Sousy 59
8086/8088 Programming Model8086/8088 Programming Model
Flags RegisterFlags Register
IFIFDFDFTFTF CFCFPFPFAFAFZFZFSFSFOFOF
after arithmetic or logic operations ,the status after arithmetic or logic operations ,the status
of the sign bit is copied in to the SFof the sign bit is copied in to the SF
Prof. Fayez F. M. El-Sousy 60
8086/8088 Programming Model8086/8088 Programming Model
Flags RegisterFlags Register
IFIFDFDFTFTF CFCFPFPFAFAFZFZFSFSFOFOF
Set when ever the result of a signed number Set when ever the result of a signed number
operation is too large; overflow in to the sign operation is too large; overflow in to the sign
bitbit
Prof. Fayez F. M. El-Sousy 61
8086/8088 Programming Model8086/8088 Programming Model
Flags RegisterFlags Register
IFIFDFDFTFTF CFCFPFPFAFAFZFZFSFSFOFOF
When set , it allows the program to single stepWhen set , it allows the program to single step
IFIFDFDFTFTF CFCFPFPFAFAFZFZFSFSFOFOF
Enable (when set) the external Enable (when set) the external maskablemaskable interruptsinterrupts
Prof. Fayez F. M. El-Sousy 62
8086/8088 Programming Model8086/8088 Programming Model
Flags RegisterFlags Register
IFIFDFDFTFTF CFCFPFPFAFAFZFZFSFSFOFOF
Enable (when set) the external Enable (when set) the external maskablemaskable interruptsinterrupts
Prof. Fayez F. M. El-Sousy 63
8086/8088 Programming Model8086/8088 Programming Model
Flags RegisterFlags Register
IFDFTF CFCFPFPFAFAFZFZFSFSFOFOF
To control the direction of string operationsTo control the direction of string operations
When set , pointers are decremented automaticallyWhen set , pointers are decremented automatically