micron technology: i.mx 8 microprocessors driving

©2017 Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject to

change without notice. All information is provided on an “AS IS” basis without warranties of any kind.

Statements regarding products, including regarding their features, availability, functionality, or compatibility,

are provided for informational purposes only and do not modify the warranty, if any, applicable to any

product. Drawings may not be to scale. Micron, the Micron logo, and all other Micron trademarks are the

property of Micron Technology, Inc. All other trademarks are the property of their respective owners.

Micron Technology: i.MX 8 Microprocessors

Driving Automotive Applications with

Micron Memory

Brian Zachrel, Micron FAE

August 16 2017

© 2017 Micron Technology, Inc.

Micron’s 25+ Year Commitment to Automotive

4

Quality First• Designed for automotive

• Automotive flow

Operational Excellence• 8D for non-conformities

• Continuous improvement

Automotive Compliance• ISO 26262 – ASIL

• TS 16949/AEC-Q100

• Long term product support


$800

Micron

$250

Cypress

$183

Samsung

$155 ISSI

$134

Toshiba

$480 Other

Automotive Memory Providers

CY2016Source: Gartner 2017

Automotive Market Overview

Increasing memory footprint by application

Increasing memory consumption by OEM

5

Trends

2015

Infotainment & Connectivity

ADAS & Autonomous

Power Train & Other

2020 2025

1B$

2B$

3B$

4B$

5B$

6B$

Source: Micron Marketing


ADAS/Autonomous Memory Bandwidth DriversL2 TO L5

*Source: IDC

Memory Bandwidth

50 to ~720GB/s

Memory Bandwidth

10 to ~300GB/s

Sense Perceive Act


In Vehicle Experience (IVE) Cluster & Virtual Cockpit MEMORY BANDWIDTH DRIVERS

*Source: IDC

2025 Virtual Cockpit

9 - 11 X 4K Screens

~ 35 GB/s ~ 140 GB/s ~ 300 GB/s

2017 IVE3 x 1080p Screens

2020 IVE + Cluster3 X 4K Screens

2025 Virtual Cockpit9 - 11 X 4K Screens

Compatibility Guides

https://www.micron.com/solutions/micron-valued-partner-program/chipset-partner/nxp


DRAM Market / Technical Details


Automotive DRAM

DRAM Market Trends

– Increasing DRAM Usage

– Increasing DDR3 adoption at higher densities 2+Gb

DRAM Requirements

– Zero Defect Target Approach

Burn in required to lower DPM rate

Material selection for Auto grade devices

– Extended Operating Temperatures

From -40°C up to 125°C for next gen devices

– Formal Product Longevity Program (PLP)

11


0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

CY15 CY16 CY17 CY18 CY19 CY20

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

Auto DRAM Market Trends

12 | August 23, 2017

Source: Micron Marketing (March’17)

% i

n 1

Gb

eq

uiv

ale

nts

DDR4

DDR3

LPDDR5

GDDR

DDR2

LPDDR2

Legacy LPDRAM LPDDR4 8Gb

Legacy Std DRAM

Densities represent die (vs. package)

General Market

Automotive

General Market:

• DDR4 dominant interface for devices w/out batteries

• Increased LPDRAM adoption outside of mobile handsets

driven by Tablets & other Client apps

• LPDRAM shipments >50% of total market by the end of CY16

• DDR5/LPDDR5 adoption projected to start in late CY’19

Automotive:

• Continued need for legacy support

• DDR3 is the primary choice for current gen low cost

Infotainment and Cluster applications

• LPDDR4 will be the primary choice for next gen ADAS and

high-end Infotainment applications

% i

n 1

Gb

eq

uiv

ale

nts

Other

LPDDR4/xLPDDR3

DDR5


Standard DRAM & LPDRAM Trade Offs

Standard DRAM LPDRAM

Form Factor Center bond pads for highest performance and lowest costEdge bond pads allow for stacked die for MCP and PoP packaging,

enabling compact form factors

Performance x4, x8, x16 is lower cost and supports higher density

configurations

x32 allows system to support high bandwidth

in point-to-point applications

DRAM powerIDD specifications are geared towards moderate stand-by power,

providing the highest yields and lowest cost

Ultra low standby power enabled by on-die power management and

long refresh rates

System powerAdditional Delay Locked Loop (DLL) circuitry required for high

performance which inhibits system power savings

Lack of DLL circuitry allows for improved system power management;

System can enter/exit power-down modes

as well as throttle or stop the clock

Key Takeaway Optimized for cost and performance;

cost is primary feature

Optimized for battery life and portability;

low power & smallest possible footprint

are primary features

LPDDR4 is a higher bandwidth solution vs. DDR4

• LPDDR4: Peak BW 34GB/s (2 x32 package)

• DDR4: Peak BW 25.6GB/s (4 x16 packages)

LPD

DR

4 S

pe

cifi

c In

foG

en

era

l LP

vs.

DD

R C

om

par

iso

n

LPDRAM offers additional value over standard DRAM

13


LPDDR1/2/3/4/5 and DDR3/4/5 Feature Comparison

14 | August 23, 2017CQ1'15

LPDDR1 LPDDR2 LPDDR3 LPDDR4/4X LPDDR5 DDR3/DDR3L DDR4 DDR5Die Density Up to 8Gb Up to 16Gb Up to 32Gb Up to 32Gb Up to 32Gb Up to 8Gb Up to 16Gb (128Gb 8H) 16Gb +

Prefetch Size 2n 2n, 4n 8n 16n 16n/32n 8n 8n 16n

Core Voltage (Vdd) 1.81.35V (S4A) 1.2V 1.1V 1.05V/0.9V

1.5V/1.35V1.2V 1.1V

1.2V (S4B) 1.8V WL supply req. 1.8V WL supply req. 1.8V VccP Separate WL supply 2.5V 1.8V Vpp

I/O Voltage 1.8V, 1.2V 1.2V 1.2V 1.1V/0.6V 0.3V - 0.5V Same as VDD Same as VDD 1.1V

Max Clock Freq. /Data rate 200Mhz 533MHz/DDR1066 800MHz/DDR1600 2133MHz/DDR4267 10 - 800MHz/20-6.4Gbps 1066MHz/DDR2100 1600MHz+/DDR3200+ 3.2Gb/s-6.4Gb/s

Burst Lengths 2, 4, 8, 16 4, 8, 16 8 16, 32 16, 32 BC4, 8 BC4, 8 BC8/B16

Package Configuration x16, x32 x16, x32, x64 x32, x64 2Ch x16, 4Ch x16 1Ch x16 x4, x8, x16 x4, x8, x16 x4, x8, x16

Address/ Command Signals 22 pins

14 pins 14 pins 10 pins per channel 7 Pins

27 pins

29 pins 14 Pins

(Mux’d command

address)(Mux’d command address) (Mux’d command address) (Mux’d command address) (partial mux’d)

(Mux’d command

address)

On Die Temperature SensorSDR (rising edge

of clock only)

Double (both rising

and falling edges of

clock)

Yes Yes Yes Optional/RS Yes Yes

PASRfull, half, quarter-

arrayfull, half, quarter-array

individual bank and segment

masking for partial-bank

modes

individual bank and segment

masking for partial-bank

modes

Yes

optional feature only -

full, ¾, half, ¼, 1/8 array,

if supported

Removed by JEDEC(Partial-array self refresh)

optional partial-

bank modes forwith individual bank

and segment masking

for partial-bank modes

Segment masking only No

eighth and

sixteenth-array

Drive Strength

25-ohm (full)

37-ohm (3/4)*

55-ohm (half)

80-ohm (quarter)*

*JEDEC optional

34-ohm

40-ohm

48-ohm

60-ohm

80-ohm

120-ohm

ZQ cal for +/-10%

accuracy

34-ohm

40-ohm

48-ohm

ZQ calibration for +/-10%

accuracy

Low-voltage swing

terminated logic (LVSTL)

VSSQ terminated

LVSTL, VSSQ-terminated

40-ohm

48-ohm

60-ohm

80-ohm

120-ohm

240-ohm

34-ohm

40-ohm

ZQ calibration for +/-10%

accuracy

34-ohm

40-ohm

TBD-ohm

ZQ calibration for

+/-10% accuracy

TBD

ZQ calibration for

Per Bank Refresh NoYes

YesYes, with directed per-bank

refreshYes No

Fine Granularity Refresh

(1x, 2x, 4x)

Fine Granularity Refresh

(1x, 2x, 4x)(8-bank devices only)

Output Driver LVCMOS_18 HSUL_12 HSUL_12 LVSTL_11/LVSTL_10 “SSTL_15” POD_12 POD_1.1

DPD (Deep power-down

mode)Yes Yes Yes No No No No No

DLL/ODT No/No No/No No/Yes No/Yes No/Yes Yes/Yes Yes/Yes Yes/Yes

Alert Pin No No No No No No No Yes

Package OptionsKGD, BGA, POP,

MCPKGD, BGA, POP, MCP KGD, BGA, POP, MCP KGD, BGA, POP, MCP KGD, BGA, POP, MCP BGA BGA BGA

Temperature Grades WT, IT, AT WT, IT, AT, UT WT, XT only WT, XT, IT, AT, UT WT, IT, AT, UT CT,IT,AT CT,IT,AT CT,IT,AT

Updated: March’17


DRAM Performance Improvements Over Time (IO x16)

15

0

5

10

15

20

25

30

35

40

45

50

55

2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017

Gb/s

DDR2

DDR2-5338.5 Gb/s

DDR2-66710.6 Gb/s

DDR2-80012.8 Gb/s

DDR3-106617 Gb/s

DDR3-133321.3 Gb/s

DDR3-160025.6 Gb/s

DDR3-186630 Gb/s

DDR4-213334 Gb/s

DDR4-240038.4 Gb/s

DDR4-266642.7 Gb/s

DDR4-320051.2 Gb/s

DDR3

DDR4

© 2017 Micron Technology, Inc.16

0

20

40

60

80

100

120

140

160

2010 2011 2012 2013 2014 2015 2016 2017 2018

LPDDR2-80025.6 Gb/s

LPDDR2-106634.11 Gb/s

LPDDR2LPDDR3-1600

51.2 Gb/s

LPDDR3-1866 59.712 Gb/s

LPDDR3

LPDDR4-3733119.4 Gb/s

LPDDR4-4266136.51 Gb/s

LPDDR4

LPDDR4-3200102.4 Gb/s

Gb/s

LPDDR4-3200102.4 Gb/s

LPDDR4 is

supported

by i.MX8

LPDDR Performance Improvements Over Time (IO x32)

Non-Volatile Details


Non-Volatile Flash Memory Solutions

18

Comprehensive selection of

Densities, Technologies, and Product

Integration

Non-volatile solutions for code, application

data storage, and data logging

A leading manufacturer of NAND/NOR/MCPSerial/Parallel NOR

Managed NAND

(e.MMC & Cards)Multi-Chip Package

(MCP & PoP)

SLC/MLC/TLC NAND

Micron quality, Technical support

and Product Longevity


D

S

G

D

S

G

D

S

G

D

S

G

Direct to read circuitry

NOR and NAND Feature Comparison

Xccela NOR Flash/ Serial NOR/Parallel NOR SLC/MLC/TLC NAND / Managed NAND

Lower density, low pin count (serial)

Ease-of-use

Reliable code and data storage

Fast read and random access times

Higher endurance and data retention

Higher density, low pin count

Requires controller management (SLC, MLC)

Mostly data-focused

Fast writes and erases

Focused on reliability and performance (SLC),

cost/GB(MLC), and reduce time-to-market (managed

NAND)

NVM architectures

NOR

– Each memory cell can be accessed

independent of the others

– Physical "contact" to each memory

location

NAND

– Memory cells are grouped in stacks

called “strings”

– Physical “contacts” to the cells are

reduced resulting in better cell

efficiency

D

S

G

D

S

G

Direct to read circuitry

"bitline"


Automotive NOR Flash Applications

– Instant on/fast boot

– Execute-in-place (XiP)

SNOR Benefits

– x8 DDR serial protocol

Non-proprietary interface

Low 11 pin-count

– Industry leading: 400MB/s (200Mhz DDR)

– Automotive grade (-40 to 125C operation)

PNOR Benefits

– Performance

– High Density up to 2Gb

– Reliability

100PE cycles, Auto quality and support.

Automotive grade (-40 to 105C operation)


Serial NOR Flash

Ideal for code storage and execution

– Fast XiP performance, fast random access times, and ultra-fast sequential byte access times

– An entire 1-Gbit of memory can be read in a mere 0.3 seconds!

– Program/Erase Suspend and Resume to aid in concurrent read-while-write operations

Ideal for data storage

– Byte/page program and 4KB Block Erase architecture for flexible data manipulation

Advanced sector protection

– Protect critical boot/program code from erroneous or malicious writes

– Protect critical configuration data and user data

Low pin-count solution to reduce SoC pin-counts, simplify PCB routing, and save board

space

21


Xccela™ Flash: Best of Parallel and Serial NOR Flash

22

512Mb

Quad-SPI

MT25Q

512Mb

Twin-Quad

MT25T

512Mb

Xccela Flash

MT35X

Bandwidth90MB/s

(90MHz, DDR mode)

180MB/s

(90MHz, DDR mode)

400MB/s

(200MHz, DDR mode)

Initial Word

Access Time

139ns (1.8V, 4-bit)

157ns (1.8V, 16-bits)

139ns (1.8V, 8-bit)

145ns (1.8V, 16-bit)

85ns (1.8V, 8-bit)

87.5ns (1.8V, 16-bit)

Subsequent

Word Access

6ns (4-bits)

24ns (16-bits)

6ns (8-bits)

12ns (16-bits)

2.5ns (8-bits)

5ns (16-bits)

Package and Pins24-BGA (6x8mm)

6 Active Pins

24-BGA (6x8mm)

11 Active Pins

24-BGA (6x8mm)

11 Active Pins

Energy Per Bit 41 pJ/bit 41 pJ/bit 28 pJ/bit

Xccela™ Flash(MT35X)

Parallel NOR FlashHigh performance

Fast bootReliability

Serial NOR FlashReduced pin countsSimple PCB design

ReliabilityNeed more

performance with same package

Want reduced pin count/package size

Xccela is

supported

by i.MX8


Micron Embedded NOR Solutions RECOMMENDED FOR NEW DESIGNS

(INCLUDING FUTURE PRODUCTS THROUGH 2018)

23 | | August 23, 2017

* Some densities are DDP and QDP configurations.

128Mb 256Mb 512Mb 1Gb 2Gb

Xccela™ Flash

Xccela™ Flash

Octal 3V

Xccela™ Flash

Octal 1.8V

Serial (SPI)

Twin-Quad Serial

3V

Twin-Quad Serial

1.8V

Quad-Serial

3V

Quad-Serial

1.8V

ParallelParallel

3V

MT25Q

MT28EW

MT25Q

MT35X

MT35X

MT25T

MT25T


Faster than any other Flash solution for direct XiP code execution

MT35X leaves other Flash behind the more you sequentially read from it

Micron’s MT35X Has the Ultimate Performance

24

XiP

Bytes Per Fetch

MT35X

Tra

nsf

er

Rate

(M

B/s

ec)

Random Read Performance vs. Data Access Size


Simplify System Design and Save Valuable Board SpaceSMALL FOOT PRINT 4X FEWER PINS & 2X SMALLER PACKAGE THAN OTHER FLASH MEMORY

25 | August 23, 2017

(50 active pins) (25 to 50 active pins) (11 active pins)

FBGA-64 (13x11mm)

TSOP-56 (14x20mm)

TBGA-64 (8x10mm)

TBGA-24 (6x8mm, 5x5 array)

MT28EW MT28G (G18) Xccela™ Flash (MT35X)


Automotive SLC NAND Flash

Trends

– Infotainment/cluster fusion

– Smart car systems—Advanced Driver Assistance Systems

(ADAS)

NAND Flash Requirements

– Cost-effective for higher-density code storage

– Simplified architecture reduces controller cost and pin count

– 105C support, 100K P/E @85C, 60K P/E @105C

– 10Yr DR @85C (uncycled)

– Security features, On-Die ECC

– Streamlined PCB design with low pin-count and BGA packages

16-Pin SOP

24-Ball BGA

| August 23, 201726

| Micron Confidential


25nm M78A/M79A SLC NAND Flash

Wide Applications: Consumer, DTV, Wearables, Set-top-

box, Automotive Infotainment

Complete Portfolio: SPI, Parallel, 1.8V, 3.3V, IT and Auto

grade

Reliability : 100K PE and 10 year uncycled data retention

High Performance: Faster Read with 133Mhz (3V, 1-1-4

mode) Faster Write Performance

Ease of use: SPI enables simpler system design with less

overhead

27

Features Micron SLC

NAND Flash

On-die ECC

Parallel & SPI interface

1.8V & 3.3V support

Wide temperature

offerings

Security features

High Performance

Ease of Use

Low/mid density offerings

August 23, 2017


SPI NAND Flash BenefitsSIMPLE AND SMALL FOR MID-DENSITY NEEDS

SPI

NOR

Parallel

NAND

Flash

SPI

NAND

Flash

e.MMC

Unit Price

Pin count 8 23 8 15

Package

size

48mm2 240mm2 48mm2 149.5m

m2

DFN 6x8mm

(8 active pins)

48mm2240mm2

|| August 23, 201728

• Competitive SPI NAND pricing

•Ease of use due to simple design

•Small form factor and serial packages


Automotive e.MMC

Market Trends

– Managed NAND for code and data storage

– Simplified management: No need for complicated

external NAND controller

– High speed

– Boot option for code execution

e.MMC Requirements

– Quality Approach

Automotive methodology flow

AEC-Q Grade 2 and AEC-Q Grade 3

– Extended Operating Temperatures


• Eliminates company

specific NAND

customization

• Boot functionality

managed within e.MMC

Linux/Android support

• Utilizes industry

standard MMC bus

• Compatible with

previous e.MMC

versions

• Standard packages

• ECC, Wear leveling,

Block management

• Performance optimized

within e.MMC

controller

Internal

NAND Management

Simplified

Hardware

Design

Simplified

Software

Design

Standardized

Interface

Decreased

Time to

Market

e.MMC Advantage

Designers of next-generation embedded processors must meet the increasingly complex

ECC & data management requirements of future MLC NAND Flash devices

MANAGED NAND DEVICES OVERCOME THESE CHALLENGES

30


Raw NAND for application “expert” with NAND data

management and ready to support ECC needs.

eMMC interface for application that want to offload by any

NAND data management with a standard interface.

Serial NAND for application requiring high density with

Serial protocol.

ECC NAND for application that do not want to change the

ECC with the NAND litho shrink.

NAND system solutions for Industry

Raw NAND

Host Controller I

NAND Interface

LLDECCFTLNAND BUS

ECC NANDHost Controller II

NAND Interface

LLDFTLNAND BUS ECC

eMMC

NANDECC

FTL

Host Controller IV

eMMC Interface

LLD

MMC BUS

SPI

ECC

Host Controller III

SPI Interface

LLD

SPI BUS

FTL

eUSB interface for application that want to offload by any

NAND data management with a standard interface.

eUSB NAND

ECC

FTL

Host Controller V

eUSB Interface

LLD

USB BUS

LLD = Low Level Driver ECC = Error Correction Code FTL = NAND Scheduling Logical Mapping, Bad Block Management, Wear Leveling


Raw NANDECC NAND

(On-Die ECC)

Fully Managed

(eMMC)

Complexity of Customer

Development (NAND Management by Host)

High Med Low

New Product

Qualification (Complexity & Effort)

High Med Low

Relative Cost Low Med Med +

Level of Management by NAND Solution

Level of Management by NAND solutionsTRADE OFFS BETWEEN COMPLEXITY, QUALIFICATION EFFORT & COST


e.MMC Fully Managed NANDPROVIDES REDUCED DESIGN EFFORT FOR MINIMAL COST

33

NAND

Wear leveling

ECC

Driver

NAND Controller

Raw NAND

ONFI NAND

bus

Command/Block

Management

Low-level Driver

NAND Controller

Fully Managed NAND (e.MMC)

MMC , SATA

or USB bus

NAND

Wear leveling,

CMD/Block

Mgmt, NAND

Error Mgmt

Controller

e.MMC, e.USB

SATA, & CF

Cost

& Price

Ease of design

& Validation


Performance consideration for system solutionsRAW NAND, ECC NAND AND EMMC REQUIRE DIFFERENT MANAGEMENT SOFTWARE

THE CORRECT PERFORMANCE EVALUATION IS AT SYSTEM


Device Throughput

Raw NAND

eMMC

ECC

FTL

On-Die ECC

NAND

ECC

Host Controller I

NAND Interface

FTL ECC LLD

Host Controller II

NAND Interface

FTL LLD

Host Controller III

eMMC Interface

LLD

NAND BUS

NAND BUS

eMMC BUS


Performance consideration for system solutionsRAW NAND, THE EVOLUTION OF EMMC 5.0 (400MT/S PHY) IMPROVES PERFORMANCE

CAPABILITIES


Device Throughput

Raw NAND

eMMC

ECC

FTL

On-Die ECC

NAND

ECC

Host Controller I

NAND Interface

FTL ECC LLD

Host Controller II

NAND Interface

FTL LLD

Host Controller III

eMMC Interface

LLD

NAND BUS

NAND BUS

eMMC BUS


Automotive SSD Market Trends

Applications

– Infotainment systems

– Self Driving Cars

– Data recording

SSDs are ideal for local storage

of important software and data

in self-driving cars

Differentiating performance

Scalable to larger capacities

Low power consumption

Higher reliability and robustness across

automotive temperature range


Transition from HDD to SSD is Economically Justifiable

$0

$50

$100

$150

$200

$250

$300

$350

$400

$450

$500

1 2 3 4 5 6 7

Enterprise Client Industrial Total cache SSD Average

AVERAGE HDD ASPS ARE ESTIMATED TO INCREASE AT A 5.7% CAGR OVER 2016-2021

37 || August 23, 2017

SSD ASP ($) by Application

$0.00

$20.00

$40.00

$60.00

$80.00

$100.00

$120.00

$140.00

$160.00

1 2 3 4 5 6 7

Enterprise Client Nontraditional/CE Total

HDD ASP ($) by Application

Source: IHS Q1 2017 SSD and HDD Storage Market Tracker


SSD Form Factors

Parameter 2.5” mSATA M.2 (PCIe) µSSD (PCIe)

Capacities (GB) 60/120/240 60/120/240 256/512/1024 128/256/512

Specification EIA-720 MO-300B,

variation A

PCIe M.2 Spec.

Rev. 1.1

PCIe M.2 Spec.

Rev. 1.1*

Dimensions (L) 100.45 mm

(W) 69.85 mm

(H) 7 mm

(L) 50.80 mm

(W) 29.85 mm

(H) 3.75 mm

(L) 30 mm

(W) 22 mm

(H) 1.5 mm

(L) 20 mm

(W) 16 mm

(H) 1.5 mm

Weight < 70g < 10g < 10 g < 10 g

EXISTING AND FUTURE DIRECTIONS

38 || August 23, 2017

Form Factors

– 2.5”, mSATA, M.2, µSSD (BGA)

Interfaces

– SATA III

– PCIe

Product Longevity

Yearly firmware updates

*Type 1620 ball-out


Why Micron?TRUSTED PARTNER OF THE WHOLE AUTOMOTIVE ECOSYSTEM

Automotive Mindset• 25+ years of auto

commitment

• Global Customer Labs

• Dedicated technical

team

• No competition with

our customers

High Quality Solution• Optimized for

automotive quality

• One stop shop - full

suite of volatile and

non volatile memories

• Continuous

improvement

Leading Edge Products• High-bandwidth DRAM

solutions

• Comprehensive storage

solutions

• Fast boot FLASH

memory

Long Term Support• Formal product

longevity program

• Extended product

change transition

phases


DRAM Products

RLDRAM – Ultra low latency for high-speed networking

• RLDRAM3 in production

• RLDRAM2 long term support in place (no planned

EOL)

HMC – Massive Parallelism and Bandwidth enables high-

speed packet buffering

• Customer designs underway for 2015 launch

DDR3/DDR4 – Cost effective high volume solutions

• Highest speed DDR3s – NOW

• DDR4 sampling NOW

DDR2/DDR/SDR – Long-term support assured to match

customer’s long product life cycle (no planned EOLs)

RLDRAM

HMC

DDR3/4

DDR2/DDR/SDR

41


DRAM Modules

42

(ECC) SODIMM

VLP RDIMM

FBDIMM/LRDIMM

(ECC) UDIMM

RDIMM

Mini-DIMM

Long-term product support & supply consistency with modules

direct from leading DRAM manufacturer

(>60% of Micron DRAM shipped in the last 3 years was on

modules)

Industry’s most comprehensive module portfolio (including DDR2

and DDR3) with focus on Networking preferred form factors

Original, superior-grade DRAM components with extensive

qualification testing

(including IT grade components)

Micron quality and technical support including dedicated resources

for module design and system compatibility testing

Global manufacturing and operations to maximize flexibility and

responsiveness


| Micron Confidential

-IT -AIT/-AAT

QU

ALIT

Y &

RELIA

BIL

ITY

Temperature Range -40 to +85°C

AIT: -40 to +85°C

AAT: -40 to +105°C

Qualification Spec Reference JESD47 AECQ100

Zero Defect Approach No

Yes, according to AEC-

Q100

(SYA, PAT,CHAR …)

Material Selection for Eligibility to Automotive No Yes

PPM Quality Agreement No Can be negotiated

ISO/TS-Certified Fab and Assembly Location Not guaranteed Yes

SER

VIC

E &

SU

PP

OR

T

8D for Failure analysis (including 5Whys)

response

Not guaranteed

standard report

Yes, according to 1-2-10

rule

PPAP Submission No Yes

Supply Prioritization No Yes

Buffer Stock/CMI/VMI No Can be negotiated

Documentation Support (Questionnaire)

Submission of Micron‘s Internal

Qualification and Reliability Report

under NDA

Full Questionnaire

Support

Fab and Assembly Audit Support ISO 9001 (limited) ISO/TS-16949 (full)

Xccela™ Flash Satisfies Auto Reliability and TemperatureOpen Standard

Ultra Fast NVM

Small Pin Count/ SPI

Compatible

Lowest Energy Per BitRich Security Features

Auto Quality


Single Level Cell vs. Multi-Level Cell

SLC

– 1 physical bit = 1 data bit

– Cell either programmed or erased

– Higher performance

– SLC NAND more reliable than MLC NAND

MLC

– 1 physical bit = 2 data bits

– 3 bit per cell technology for some NAND

– Cells partially programmed

– Lower performance

– Higher density and lower cost per MB


NAND technology challenges

How to manage the ECC requirements?

– NAND controllers with high ECC capability

– ECC NAND managed solutions

on-die ECC

– Fully managed solutions

eMMC, eUSB, others

How to manage lower Endurance?

Understand the application and usage model

– How does the file system work?

– How often are you programming?

– How big is the data file/s?

– What is the PLC of your system?

INTERSECTING YOUR PROJECT AND THE MEMORY TECHNOLOGY IS KEY TO SUCCESS!

Determines PE Cycles and Density Required


Broad Market e.MMCINTERFACE SIGNALS

August 23, 2017

CLK

CMD

DAT[7:0]

VCC

VSS

VCCQ

VSSQ

RST_n

NAND (ONFI)

ALE

CLE

CE#

RE#

WE#

WP#

I/O[7:0]

R/B#

VCC

VSS

15 signals

+

2 power lines

10 signals

+

4 power lines

+

HW reset

e.MMC


CPU or Chipset

NAND

Flash

DQ

7:0

Co

ntro

l Pin

s

R/B

#

DQ

15

:8

x1

6

x8

& x

16

AD

V

CPU or Chipset

eMMC 5.0

DQ

15

:0

A M

ax

:0

Co

ntro

l Pin

s

WA

IT

W#

/Vp

p

CPU or Chipset

Serial

NOR x1

Ho

ld#

DO DI

DQ

2

CPU or Chipset

Serial

NOR x4

DQ

3

DQ

1

DQ

0

X8 X16

14 22

Interface X1

# of pins 6

X4

6

Interface Speeds (Max)

250MB/s 50-100MB/s 13MB/s 66MB/s

X8

15

Flash Architectures – Component LevelALL ARCHITECTURES HAVE THEIR ADVANTAGES

TREND IN THE INDUSTRY MOVING TOWARD THE LOWER PIN COUNT ARCHITECTURES


Density Needs for Boot Memory


©2014 Micron Technology, Inc. | 49

DRAM product attributes

• Many different types

• Fast read performance

• Fast writes

• Leading edge requires many conversions

Discrete

• Common standards

• Common packages

• Many levels in a single system

Module

• Higher density reach

• Easier conversions/migrations

• Standards and custom options

• ECC management enabled


Freq. Range

(MHz)

Bus Width (per

device)

Max.

Bandwidth

(burst rate)

Transfer rate per pin Density Row Cycle

Time (tRC)

Max Power

SDRAM 100-200 x4, x8, x16, x32 400 MB/s 100-200Mb/s 64Mb - 512Mb 66ns 1W

DDR1 100-200 x4, x8, x16 800 MB/s 200-400Mb/s 128Mb-1Gb 60ns 1W

DDR2 200-400 x4, x8, x16 1.6 GB/s 400-800Mb/s 256Mb-2Gb 55ns 700mW

DDR3 400-1066 x4, x8, x16 3.2 GB/s 800-1600Mb/s 1Gb, 2Gb 48ns 500mW

DDR3L 400-800 x4, x8, x16 3.2 GB/s 800-1600Mb/s 1Gb, 2Gb 48ns 440mW

DDR4 667-1600 x4, x8, x16, x32 12.8 GB/s 1333-3200Mb/s 4-8Gb TBD<45ns TBD-330mW

LPDDR 100-167 X16, x32 667 MB/s 200-333Mb/s 128-512Mb 45-50ns 150-230mW

LPDDR2 333-400 X16, x32 2.1 GB/s 667-1066Mb/s 2-8Gb 55ns 200mW

• Technology migration (SDRDDRDDR2DDR3DDR4) has improved on power/Bandwidth/density

• LPDRAM can offer better system standby power, but requires a price trade-off consideration

DRAM Active Power

August 23, 2017

Compatibility Guides




Automotive

micron technology: i.mx 8 microprocessors driving

Documents