Micron Technology ClinicMicron Technology Clinic

Effect of Transistor Number and Effect of Transistor Number and Hierarchy on Simulation SpeedHierarchy on Simulation Speed

Presented by: Jason OneidaPresented by: Jason Oneida

Advisor: Dr. Ken StevensAdvisor: Dr. Ken Stevens

OverviewOverview►Advantages of Two-Phase Analysis?Advantages of Two-Phase Analysis?

Simulation speedSimulation speed Accurate abstractionAccurate abstraction Hierarchy in simulationHierarchy in simulation

►Experiment: Cascading multipliersExperiment: Cascading multipliers Test importance of hierarchy in designTest importance of hierarchy in design Scaling hierarchical mesh of 16-bit multipliersScaling hierarchical mesh of 16-bit multipliers Implementation notes: Galois LFSRImplementation notes: Galois LFSR

►Data comparisonData comparison HSimPlus and HSPICEHSimPlus and HSPICE Conclusions regarding Two-Phase AnalysisConclusions regarding Two-Phase Analysis

Experimental Setup►Hypothesis:

Hierarchy in execution will result in faster run-time Two-Phase Analysis

and hierarchy Micron single-layer

package model

►Metric for comparison Number of

transistors vs. simulation time

[1] “Central Processing Unit,” schools-wikipedia.org, Jan. 2008 – Jan. 2009. [Online]. Available: http://schools-wikipedia.org/wp/c/Central_processing_unit.htm[Accessed: March 29, 2010]

Circuit DesignCircuit Design

►Cascaded multipliers Hierarchy: divergent data path Non-ideal modeling

►Pseudo-random input Linear feedback shift register (LFSR)Linear feedback shift register (LFSR)►Galois LFSRGalois LFSR

[2] “Linear Feedback Shift Register,” absoluteastronomy.com, Jan, 2010. [Online]. Available: http://www.absoluteastronomy.com/topics/Linear_feedback_shift_register [Accessed: March 29, 2010]

Multiplier Block DiagramMultiplier Block Diagram

HSimPlus ResultsHSimPlus Results

►Plot featuresPlot features VariablesVariables ScaleScale

►Data PointsData Points Eight totalEight total

► Curve FitCurve Fit Initial regionInitial region Linear PortionLinear Portion

HSPICE ResultsHSPICE Results

►AxesAxes UnitsUnits

►Simulation timeSimulation time 10,000 sec. per 10,000 sec. per

every 100,000 every 100,000 transistorstransistors

►Curve ShapeCurve Shape SlopeSlope Fit trendFit trend

Combined Results

►Data point discrepancy – 8 vs. 6Data point discrepancy – 8 vs. 6

►Speed differenceSpeed difference

Sample Multiplier OutputSample Multiplier Output

►HSimPlus settingsHSimPlus settings

►Values: approximately 5% errorValues: approximately 5% error

Conclusions►Experiment to show benefit of hierarchy

on run-time using two phase models►Validated with a scalable design

Hierarchical grids of multipliers Pseudo-random number generators for data

►Hypothesis confirmed HSimPlus scaled at about 1,000 sec. per

100,000 transistors HSPICE scaled at about 10,000 sec per 100,000

transistors Output accuracy within 5%