E L S E V I E R Microelectronic Engineering 30 (1996) 523-526

MICROELECTRONIC ENGINEERING

M I C R O M A C H I N E D F I E L D E M I S S I O N D E V I C E S

Wolfgang Hofmann, Liang-Yuh Chen, John H. Das and Noel C. MacDonald

School of Electrical Engineering and the Cornell Nanofabrication Facility (CNF), Cornell University, Ithaca, NY 14853-5401

We present the application of micromachining technology to silicon-based field emission devices. Silicide formation on the emitter is shown to lead to lower voltage emission. Integration of series resistors and heaters is achieved by silicon bulk-micromachining. Multiple levels of tungsten electrodes are integrated by surface micromachining. This allows the integration of an entire micromachined electron gun array (MEGA) on a single silicon substrate. We review simulation results to illustrate the electron-optical properties of MEGA and show fabrication results and emission data.

1. INTRODUCTION

The work of Spindt [1] ushered the era of micro- fabricated field emitters and field emitter arrays more than twenty years ago. Spindt cathodes still are commonly used today, but more recent work has focused on silicon to draw on the advances in silicon processing technology driven by the integrated circuit industry [2-4]. In this paper we present our efforts to expand on this work by incorporating micromachining technology originally developed for the fabrication of micro- electro-mechanical systems (MEMS): Silicon bulk- micromachining in the form of the Single Crystal React ive Etching And M etallization (SCREAM) process [5,6] has been used to incorporate series resistors, and heaters in combination with a tip silicide formation process. Surface micromachining in the form of an adaptat ion of the Selective Tungsten Multiple-level Planar Process (STUMPP) [7] has been used to integrate suspended planar electrodes. This allows the fabrication of entire micromachined electron gun arrays (MEGA) and other complex field emission devices on a single silicon substrate. In the fol lowing sections we briefly review the design issues of MEGA and the improvements made to silicon field emitters. Then we discuss in more detail the integration of additional electrodes and some of the field emission devices fabricated in this manner.

2. M I C R O M A C H I N E D E L E C T R O N GUN ARRAYS (MEGA)

The goal of our work is the fabrication of silicon- based M E G A for applications such as massively-

parallel electron beam li thography [8]. Figure 1 shows a typical MEG design. It consists of a sharp silicon or silicide emitter (tip radius < 20 nm), a self-aligned planar tungsten gate electrode with a submicron aperture diameter (< 500 nm) and several suspended tungsten apertures (1-4 ~m diameter) which form an electrostatic lens. Micro-electro- mechanica l (MEM) stages and actuators are integrated with the suspended apertures to allow for misalignment (typically < 250 nm) correction. The electron-optical properties of MEGs have been studied using the numerical simulation software packages SOURCE and EMECH from Munro ' s Electron Beam Software Ltd. In agreement with previous studies [9,10] two aperture immersion lenses require high voltages ratios (>20) to form a real image, exceeding the dielectric breakdown limit in a MEG. Three and four-electrode einzellens designs form real images over a wide range of working distances for beam energies as low as 100 eV [11]. The e lec t ron-e lec t ron interact ions have been investigated using Monte Carlo simulations. Both beam broadening and displacement due to electron- electron interactions in a multiple beam array have

I I m l

Figure 1: Diagram of a micromachined electron gun

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524 W. Hofmann et al. / Microelectronic Engineering 30 (1996) 523-526

0.02

i 0.01

suspended silicon microstructures using the SCREAM process [5,6]: the silicon in the beam connecting the emitter tip to the substrate forms the

0.s d" series resistor. A combination of the SCREAM and i silicide processes has been used to integrate a heater

on the suspended silicon structure (Fig. 3). This allows the study of tip cleaning and forming

0.4 processes.

4. FABRICATION OF I N T E G R A T E D ELECTROSTATIC LENSES

20 30 40 50 60 70 a~l# val~j# ¢41

Figure 2: Emitted current vs. gate voltage for a single NiSi emitter and a 9-tip array

been studied. The simulation results indicate that at a minimum beam spacing of 100 gm and beam currents of 10 nA the beam interaction in a MEGA is indiscernible even at low beam energies [12].

3. I M P R O V E M E N T S TO S I L I C O N F I E L D EMITTERS

A number of steps have been undertaken to improve the performance (lifetime, stability) of the silicon field emitters and the uniformity over emitter arrays. The basic tip fabrication process has been extended to include the formation of a silicide (NiSi2) on the emitter surface. The higher electron density and lower work function of the silicide lead to a decrease of the turn-on voltages for the field emitter from >100V for silicon emitters to typically 60V (best case 30V) for NiSi field emitters (Fig. 2). In order to stabilize the emission current series resistors are integrated with the emitters as current feedback elements. The emitters are fabricated on

The integration of electrostatic lenses requires the integration of several aperture (or cylinder) electrodes on top of the emitter-gate structure. First emitters with self-aligned planar gate apertures are fabricated using a novel selective tungsten CVD- based process [13]. Then multiple levels of suspended planar tungsten aperture electrodes are fabricated by repeating an identical sequence of steps for each level. This is demonstrated using STUMPP surface micromachining technology [7]. The fabrication sequence is shown in Figure 4. Annular ("donut") patterns are defined by photolithography and transferred to a dielectric stack (Si02/Si3N4/SiOa) using a vertical CHF 3 reactive ion etch (RIE) (Fig. 4a). The top SiO 2 layer serves as an etch mask in the subsequent undercut etch of the silicon substrate by SF 6 RIE (Fig. 4b). The silicon tip emitters are then formed by thermal oxidation of the tapered silicon pillars (Fig. 4c). A shallow silicon ion implant is followed by a strip of the Si3N 4 implantation mask in hot phosphoric acid. This results in a silicon rich surface of the SiO 2 film

(a) ( e ) ~

(e) ~ ( g ) ~ (~> [] []

( k > ~ [] m[

Figure 3: NiSi emitter on a suspended heater Figure 4: Process flow for the fabrication of a MEG consisting of a gated Si emitter and two additional

suspended planar tungsten electrodes

W. Hofmann et al. / Microelectronic Engineering 30 (1996) 523-526 525

at the bottom of the etched features (Fig. 4d) which acts as the seed-layer for the ensuing selective tungsten CVD; the tungsten only deposits on the exposed silicon or itself and fills the etched trenches to form the self-aligned gate electrode (Fig. 4e). The CVD tungsten has smooth sidewalls but its top surface shows some roughness due to large grain size. Mechanica l micro pol i sh ing is used to completely planarize the surface (Fig. 4f). For the next tungsten level, first a thick (several microns) low-temperature oxide (LTO) film and a 150 nm layer of Si3N 4 are deposited on top of the gated emitters which are embedded in the substrate (Fig. 4g). Patterns are defined by photolithography and etched vertically into the underlying Si 3 N 4 and SiO 2 films using magnetron ion etching (MIE) (Fig. 4h). The etch depth determines the height of the tungsten structures and the remaining SiO z thickness becomes the tungsten to substrate spacing. A shallow silicon implan t , followed by a strip of the Si3N 4 implantat ion mask generates sil icon rich surfaces at the bottom of the etched trenches (Fig. 4i). Selective CVD of tungsten fills these trenches (Fig 4j) and the surface is again planarized using mechanical micro polishing (Fig. 4k). The identical sequence of steps (Figs. 4g - 4k) is repeated for each addit ional level of tungsten microstructures. After all the tungsten levels have been fabricated (Fig. 41), the sacrificial SiO 2 is removed by MIE (Fig 4m) and then wet etch (Fig. 4n) to release the suspended electrodes and expose the emitter tip.

5. RESULTS AND DISCUSSION

The process sequence described above has been used to fabricate a variety of integrated field emission devices. The gated emitter structures have tip radii below 20 nm and gate apertures of less than 500 nm diameter. The tip radius of the silicon emitters is independent of the oxidation time: the tip formation is self-limiting and longer oxidations only increase the thickness of the oxide layer covering the tip and the vertical distance between tip and self-aligned gate aperture. The dependence of oxidation rates on crystal orientation furthermore leads to narrowing of the shank of the emitter. The gate aperture diameter is determined by the combinat ion of SF 6 undercut etch and thermal oxidation. It is equal to the narrowest part of the

Figure 5: Suspended 1 ].tm-aperture in a 10xl0 ]xm plate on a MEM stage above a gated emitter

oxidized tapered silicon pillar (cf. Fig. 4c). This diameter can be reduced by thinning the SiO 2 film covering the tip, but as this film also forms the dielectric spacer between tip and gate electrode etch stop control is critical. Figure 5 shows a 1 btm aperture at the center of a 10 x 10 [.tm plate suspended above a gated emitter. The four beams connect the plate to MEM actuators for accurate x-y posi t ioning. Figure 6 shows an addressable 2x2 electron source array. The lower (upper) apertures are 0.5 ~tm (4 ].tm) in diameter, with a vertical spacing of 2 ~m and lateral tip-to-tip spacing of 40 btm. The number and geometry of the suspended tungsten electrodes are limited by the overall structure height and the minimum feature sizes (e.g. apertures) that can be fabricated using STUMPP. The overall structure height is limited to approx. 12 I.tm by the stress in the LTO films that serve as sacrificial layers for the selective tungsten CVD. The aspect ratio of individual electrodes is limited by etch selectivity of resist to SiO 2 in the patterning of the trenches (Fig. 4i). Aspect ratios of 4:1 have been achieved and suspended electrodes with apertures down to 1 ~tm have been fabricated for an electrode thickness of 2 ].tm. An upper l imit on electrode thickness is imposed by a deterioration of selectivity in long tungsten depositions. The maximum electrode thickness fabricated to date is 6 ~m.

526 W. Hofmann et al. / Microelectronic Engineering 30 (1996) 523-526

Figure 6:2x2 addressable electron source array

6. CONCLUSION

We have demonstrated the use of micromachining technology to integrate a number of performance enhancing elements with silicon field emission sources. Silicide formation on the tip leads to lower turn-on voltages, integrated series resistors improve emission stability and emitter lifetime and integrated heaters allow tip cleaning and tip formation processes to be studied. Tungsten Surface micromachining is used to integrate suspended tungsten electrodes. This allows the integration of an entire micromachined electron gun array (MEGA) on a single silicon substrate. A number of other complex field emission devices such as microtriodes and addressable arrays (e.g. for displays) have been fabricated as well. The MEGA architecture and fabrication technology are shown to be suitable for the fabrication of large arrays of electron microsources. Current research is focused on the refining of the fabrication sequence and the experimental determination of the electron- optical characteristics.

7. ACKNOWLEDGEMENTS

This research was supported by grants from ARPA, the SRC and NSF. Microfabrication was performed at the Cornell Nanofabrication Facility which is supported by NSF, Cornell University and industrial affiliates. The assistance of the CNF staff is gratefully acknowledged.

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