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Microfabricated ion trapsMarcus D. Hughes a , Bjoern Lekitsch a , Jiddu A. Broersma a & Winfried K. Hensinger aa Department of Physics and Astronomy, University of Sussex, Brighton BN1 9QH, UK

Available online: 14 Sep 2011

To cite this article: Marcus D. Hughes, Bjoern Lekitsch, Jiddu A. Broersma & Winfried K. Hensinger (2011): Microfabricatedion traps, Contemporary Physics, 52:6, 505-529

To link to this article: http://dx.doi.org/10.1080/00107514.2011.601918

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Microfabricated ion traps

Marcus D. Hughes*, Bjoern Lekitsch, Jiddu A. Broersma and Winfried K. Hensinger

Department of Physics and Astronomy, University of Sussex, Brighton BN1 9QH, UK

(Received 14 January 2011; final version received 20 June 2011)

Ion traps offer the opportunity to study fundamental quantum systems with a high level of accuracy highlydecoupled from the environment. Individual atomic ions can be controlled and manipulated with electric fields,cooled to the ground state of motion with laser cooling and coherently manipulated using optical and microwaveradiation. Microfabricated ion traps hold the advantage of allowing for smaller trap dimensions and betterscalability towards large ion trap arrays also making them a vital ingredient for next generation quantumtechnologies. Here we provide an introduction into the principles and operation of microfabricated ion traps. Weshow an overview of material and electrical considerations which are vital for the design of such trap structures. Weprovide guidance on how to choose the appropriate fabrication design, consider different methods for thefabrication of microfabricated ion traps and discuss previously realised structures. We also discuss the phenomenonof anomalous heating of ions within ion traps, which becomes an important factor in the miniaturisation of iontraps.

Keywords: ion traps; microfabrication; quantum information processing; anomalous heating; laser cooling andtrapping

1. Introduction

Ion trapping was developed by Wolfgang Paul [1] andHans Dehmelt [2] in the 1950s and 1960s and ion trapsbecame an important tool to study important physicalsystems such as ion cavity QED [3,4], quantumsimulators [5–9], determine frequency standards [10–13], as well as the development towards a quantuminformation processor [14–16]. In general, ion trapscompare well to other physical systems with goodisolation from the environment and long coherencetimes. Progress in many of the research areas where iontraps are being used may be aided by the availability ofa new generation of ion traps with the ion–electrodedistance on the order of tens of micrometres. While insome cases, the availability of micrometre scale ion–electrode distance and a particular electrode shape maybe of sole importance, often the availability of versatileand scalable fabrication methods (such as micro-electromechanical systems (MEMS) and other micro-fabrication technologies) may be required in a parti-cular field.

One example of a field which will see step-changinginnovation due to the emergence of microfabricatedion traps is the general area of quantum technologywith trapped ions. In 1995 David DiVincenzo set outcriteria which determine how well a system can be usedfor quantum computing [17]. Most of these criteria

have been demonstrated with an ion trap: qubitinitialisation [18,19], a set of universal quantum gatescreating entanglement between ions [14,20–22], longcoherence times [23], detection of states [24,25] and ascalable architecture to host a large number of qubits[26–29]. An important research area is the developmentof a scalable architecture which can incorporate all ofthe DiVincenzo criteria. A realistic architecture hasbeen proposed consisting of an ion trap arrayincorporating storage and gate regions [30–32] andcould be implemented using microfabricated ion traps.Microfabricated ion traps hold the possibility of smalltrap dimensions on the order of tens of micrometresand more importantly fabrication methods like photo-lithography that allow the fabrication of very largescale arrays. Electrodes with precise shape, size andgeometry can be created through a number of processsteps when fabricating the trap.

In this article we will focus on the design andfabrication of microfabricated radio frequency (rf) iontraps as a promising tool for many applications in iontrapping. Another ion trap type is the Penning trap [33]and advances in their fabrication have been discussedby Castrejon-Pita et al. [34] and will not be discussed inthis article. Radio-frequency ion traps include multi-layer designs where the ion is trapped betweenelectrodes located in two or more planes with the

*Corresponding author. Email: m.d.hughes@sussex.ac.uk

Contemporary Physics

Vol. 52, No. 6, November–December 2011, 505–529

ISSN 0010-7514 print/ISSN 1366-5812 online

� 2011 Taylor & Francis

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electrodes symmetrically surrounding the ion, forexample as the ion trap reported by Stick et al. [26].We will refer to such traps as symmetric ion traps.Geometries where all the electrodes lie in a single planeand the ion is trapped above that plane, for example asthe trap fabricated by Seidelin et al. [27], will bereferred to as asymmetric or surface traps.

There have been many articles discussing ion trapsand related physics, including studies of fundamentalphysics [35–37], spectroscopy [38], and coherent con-trol [15]. This article focuses on the current progressand techniques used for the realisation of microfabri-cated ion traps. First we discuss basic principles of iontraps and their operation in Section 2. Section 3discusses linear ion trap geometries as a foundation ofmost ion trap arrays. The methodology of efficientsimulation of electric fields within ion trap arrays isdiscussed in Section 4. Section 5 discusses somematerial characteristics that have to be consideredwhen designing microfabricated ion traps includingelectric breakdown and rf dissipation. Section 6provides a guide to realising such structures with thedifferent processes outlined together with the capabil-ities and limitations of each one. Finally in Section 7we discuss motional heating of the ion due tofluctuating voltage patches on surfaces and its im-plications for the design and fabrication of micro-fabricated ion traps.

2. Radio-frequency ion traps

Static electric fields alone cannot confine charged parti-cles, this is a consequence of Earnshaw’s theorem [39]which is analogous to Maxwell’s equation r � E ¼ 0.To overcome this Penning traps use a combination ofstatic electric and magnetic fields to confine the ion[33,40]. Radio frequency (rf) Paul traps use a combina-tion of static and oscillating electric fields to achieveconfinement. We begin with an introduction into theoperation of radio-frequency ion traps, highlightingimportant factors when considering the design ofmicrofabricated ion traps.

2.1. Ion trap dynamics

First we consider a quadrupole potential within theradial directions, x- and y-axes, which is created fromhyperbolic electrodes as shown in Figure 1, whilst thereis no confinement within the axial (z) direction. Byconsidering a static voltage V0 applied to two oppositeelectrodes, the resultant electric potential will producea saddle as depicted in Figure 2(a). With the ionpresent within this potential, the ion will feel an inwardforce in one direction and outward force in thedirection perpendicular to the first. Reversing the

polarity of the applied voltage the saddle potential willundergo an inversion as shown in Figure 2(b). As theforce acting on the ion is proportional to the gradient ofthe potential, the magnitude of the force is less when theion is closer to the centre. The initial inward force willmove the ion towards the centre where the resultantoutward force half a cycle later will be smaller. Overone oscillation the ion experiences a greater forcetowards the centre of the trap than outwards resultingin confinement. The effective potential the ion seeswhen in an oscillating electric field is shown in Figure2(c). If the frequency of the oscillating voltage is toosmall then the ion will not be confined long enough inone direction. For the case where a high frequency ischosen then the effective difference between the inwardand outward forces decreases and the resultantpotential is minimal. By selecting the appropriatefrequency OT of this oscillating voltage together withthe amplitude V0 which is dependent on the mass of thecharged particle, confinement of the particle can beachieved within the radial directions.

There are two ways to calculate the dynamics of anion within a Paul trap, firstly a comprehensive treat-ment can be given using the Mathieu equation. TheMathieu equation provides a complete solution for thedynamics of the ion. It also allows for the determina-tion of parameter regions of stability where the ioncan be trapped. These regions of stability aredetermined by trap parameters such as voltageamplitude and rf drive frequency. Here we outlinethe process involved in solving the equation of motionvia the Mathieu equation approach. By applying anoscillating potential together with a static potential,the total potential for the geometry in Figure 1 can beexpressed as [36]

fðx; y; tÞ ¼ ðU0 � V0 cos ðOTtÞÞx2 � y2

2r20

� �; ð1Þ

Figure 1. Hyperbolic electrodes where an rf voltage of V0

cos (OT t) together with a static voltage of U0 is applied totwo opposite electrodes. The polarity of this voltage isreversed and applied to the other set of electrodes.

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where r0 is defined as the ion–electrode distance. This isfrom the centre of the trap to the nearest electrode andOT is the drive frequency of the applied time varyingvoltage. The equations of motion of the ion due to theabove potential are then given by [36]

d2x

dt2¼ � e

m

@fðx; y; tÞ@x

¼ � e

mr20ðU0 � V0 cos OTtÞx;

ð2Þ

d2y

dt2¼ � e

m

@fðx; y; tÞ@y

¼ e

mr20ðU0 � V0 cos OTtÞy; ð3Þ

d2z

dt2¼ 0: ð4Þ

Later it will be shown that the confinement in the z-axis will be produced from the addition of a staticpotential. Making the following substitution

ax ¼ �ay ¼4eU0

mr20O2T

; qx ¼ �qy ¼2eV0

mr20O2T

;

z ¼ OTt=2;

Equations (2) and (3) can be written in the form of theMathieu equation.

d2i

dz2þ ðai � 2qi cos 2zÞi ¼ 0; i ¼ ½x; y�: ð5Þ

The general Mathieu equation given by Equation (5) isperiodic due to the 2qi cos 2z term. The Floquet theorem[41] can be used as a method for obtaining a solution.Stability regions for certain values of the a and q param-eters exist in which the ion motion is stable. By con-sidering the overlap of both the stability regions for thex- and y-axes of the trap [36,37], the parameter regionwhere stable trapping can be accomplished is obtained.For the case when a ¼ 0, q � 1 then the motion of theion in the x-axis can be described as follows,

xðtÞ ¼ x0 cos ðoxtÞ 1þqx2

cos ðOTtÞh i

ð6Þ

with the equation of motion in the y-axis of the sameform. The motion of the ion is composed of secularmotion ox (high amplitude slow frequency) andmicromotion at the drive frequency OT (small ampli-tude high frequency).

The second form to calculate motion is thepseudopotential approximation [2]. This considers thetime averaged force experienced by the ion in aninhomogeneous field. With an rf voltage of V0 cos OT tapplied to the trap a solution for the pseudopotentialapproximation is given by [2]

cðx; y; zÞ ¼ e2

4mO2T

jrVðx; y; zÞj2; ð7Þ

where m is the mass of the ion, rV(x,y,z) is thegradient of the potential. The motion of the ion in a rfpotential can be described just by the secular motion inthe limit where qi/2 : 21/2oi/OT � 1. The secularfrequency of the ion is given by [42]

o2i ðx; y; zÞ ¼

e2

4m2O2T

@2

@x2ðjrVðx; y; zÞj2Þ: ð8Þ

The pseudopotential approximation provides a meansto treat the rf potential in terms of electrostatics only,leading to simpler analysis of electrode geometries.

Micromotion can be divided into intrinsic andextrinsic micromotion. Intrinsic micromotion refers tothe driven motion of the ion when displaced from therf nil position due to the secular oscillation within thetrap. Extrinsic micromotion describes an offset ofthe ion’s position from the rf nil from stray electricfields, this can be due to imperfections of the symmetryin the construction of the trap electrodes or the buildup of charge on dielectric surfaces. Micromotion cancause a problem with the widening of atomic transitionlinewidth, second-order Doppler shifts and reducedlifetimes without cooling [43]. It is therefore importantwhen designing ion traps that compensation of strayelectric fields can occur in all directions of motion.Another important factor is the occurrence of apossible phase difference j between the rf voltages

Figure 2. Principles of confinement with a pseudopotential. (a) A saddle potential created by a static electric field from ahyperbolic electrode geometry. (b) The saddle potential acquiring an inversion from a change in polarity. (c) The effectivepotential the ion sees resulting from the oscillating electric potential.

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on different rf electrodes within the ion trap. This willresult in micromotion that cannot be compensated for.A phase difference of j ¼ 18 can lead to an increase inthe equivalent temperature for the kinetic energy dueto the excess micromotion of 0.41 K [43], well abovethe Doppler limit of a few milli-kelvin.

The trap depth of an ion trap is the potentialdifference between pseudopotential at the minimum ofthe ion trap and the lowest turning point of the poten-tial well. For hyperbolic geometries this is at the surfaceof the electrodes, for linear geometries (see Section 3.1)it can be obtained through electric field simulations.Higher trap depths are preferable as they allow the ionto remain trapped longer without cooling. Typical trapdepths are on the order of a few eV. The speed ofoptical qubit gates for quantum information processing[44] and shuttling within arrays [45] is dependent on thesecular frequency of the ion trap. Secular frequenciesand trap depth are a function of applied voltage, drivefrequency OT, the mass of the ion m and the particulargeometry (particularly the ion–electrode distance).Since the variation of the drive frequency is limited bythe stability parameters, it is important to achieve largemaximal rf voltages for the design of microfabricatedion traps, which is typically limited by bulk breakdownand surface flashover (see Section 5). It is alsoimportant to note that the secular frequency alsoincreases whilst scaling down trap dimensions for agiven applied voltage allowing for large secularfrequencies at relatively small applied voltages.

2.2. Motional and internal states of the ion.

Single ions can be considered to be trapped within athree-dimensional harmonic well with the three direc-tions of motion uncoupled. Considering the motion ofthe ion along one of the axes, the Hamiltoniandescribing this model can be represented as

H ¼ �ho ayaþ 1

2

� �ð9Þ

with o the secular frequency, a{ and a the raising andlowering operators, respectively; these operators havethe following properties: a{jni ¼ (n þ 1)1/2jn þ 1i,ajni ¼ n1/2jn 7 1i. When an ion moves up onemotional level, it is said to have gained one motionalquantum of kinetic energy. For most quantum gateswith trapped ions, the ion must reside within theLambe–Dicke regime. This is where the ion’s wavefunction spread is much less than the optical wave-length of the photons interacting with the ion. Theoriginal proposed gates [30] required the ion to be inthe ground state motional energy level, but morerobust schemes [21] do not have such stringentrequirements anymore.

Another requirement for many quantum technol-ogy application is the availability of a two-level systemfor the qubit to be represented, such that the ion’sinternal states can be used for encoding. The qubit canthen be initialised into the state j1i, j0i or a super-position of both. Typical ion species used are hydro-genic ions, which are left with one orbiting electron inthe outer shell and similar structure to hydrogen onceionised. These have the simplest lower level energydiagrams. Candidates for ions to be used as qubits canbe subdivided into two categories. Hyperfine qubits,171Ybþ, 43Caþ, 9Beþ, 111Cdþ, 25Mgþ use the hyperfinelevels of the ground state and have lifetimes on theorder of thousands of years, whilst optical qubits,40Caþ, 88Srþ, 172Ybþ use a ground state and ametastable state as the two-level system. Thesemetastable states typically have lifetimes on the orderof seconds and are connected via optical transitions tothe other qubit state.

2.3. Laser cooling

For most applications, the ion has to be cooled to astate of sufficiently low motional quanta, which can beachieved via laser cooling. For a two-level system,when a laser field with a frequency equivalent to thespacing between the two energy levels is applied to theion, photons will be absorbed resulting in a momentum‘kick’ onto the ion. The photon is then spontaneouslyemitted which leads to another momentum kick ontothe ion in a completely random direction so the neteffect of many photon emissions averages to zero. Dueto the motion of the ion within the harmonic potentialthe laser frequency will undergo a Doppler shift. Byred detuning (lower frequency) the laser frequency by dfrom resonance, Doppler cooling can be achieved.When the ion moves towards the laser, the ion willexperience a Doppler shift towards the resonanttransition frequency and more scattering events willoccur with the net momentum transfer slowing the iondown. Less scattering events will occur when travellingaway from the Doppler shifted laser creating a netcooling of the ion’s motion. Doppler cooling cantypically only achieve an average motional energy state�n > 1. In order to cool to the ground state of motion,resolved sideband cooling can be utilised. This can beachieved with stimulated Raman transitions [46,47].

For effective cooling of the ion, the k-vector of thelaser needs a component in all three directions of un-coupled motion. These directions depend on the trappotential and they are called the principal axes. For aconvenient choice of directions for the laser beam,principal axes can be rotated by an angle y by appli-cation of appropriate voltages [42,48] or asymmetriesin the geometry about the ion’s position [49–51].

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The angle of rotation of the principal axes can beobtained through the Hessian matrix of the electricfield. This angle describes a linear transformation ofthe electric potential that eliminates any cross-termsbetween the axes creating uncoupled equations ofmotion. The eigenvectors of the matrix signify thedirection of the principal axes.

2.4. Operation of microfabricated ion traps

In order to successfully operate a microfabricated iontrap a certain experimental infrastructure needs to be inplace, from the ultra high vacuum (UHV) system appa-ratus to the radio-frequency source. A description ofexperimental considerations for the operation of micro-fabricated ion traps was given by McLoughlin et al. [52].For long storage times of trapped ions and performinggate operations, the collision with background particlesmust not be a limiting factor. Ion traps are thereforetypically operated under ultra high vacuum (UHV)(pressures of 1079710712 mbar). The materials usedneed to be chosen carefully such that outgassing does notpose a problem. The materials used for different trapdesigns are discussed in more detail within Section 6.

To generate the high rf voltage (*100–1000 V) aresonator [53] is commonly used. Typical resonatordesigns include helical and coaxial resonators. Theadvantage of using a resonator, is that it provides afrequency source with a narrow bandpass, defined bythe quality factorQ of the combined resonator–ion trapcircuit. This provides a means of filtering out frequen-cies that couple to the motion of the ion leading tomotional heating of the trapped ion. A resonator alsofulfills the function of impedance matching thefrequency source to the ion trap. The total resistanceand capacitance of the trap lowers the Q factor. It isimportant to minimise the resistance and capacitance ofthe ion trap array if a high Q value is desired.

To provide electrical connections, ion traps aretypically mounted on a chip carrier with electricalconnections provided by wire bonding individual elec-trodes to an associate connection on the chip carrier.Bond pads on the chip are used to provide a surface onwhich the wire can be connected, see Figure 3. The pinsof the chip carrier are connected to wires which pass toexternal voltage supplies outside the vacuum system.

The loading of atomic ions within Paul traps isperformed utilising a beam of neutral atoms typicallyoriginating from an atomic oven consisting of aresistively heated metallic tube filled with the appro-priate atomic species or its oxide. The atomic flux isdirected to the trapping region where atoms can beionised via electron bombardment or more commonlyby photoionisation, see for example [52,54]. The latterhas the advantage of faster loading rates requiring lower

neutral atom pressures and results in less charge buildup resulting from electron bombardment. For asym-metric traps in which all the electrodes lie in the sameplane, see Figure 4, a hole within the electrode structurecan be used for the atomic flux to pass through the trapstructure, this is defined as backside loading [49]. Themotivation behind this method is to reduce the coatingof the electrodes and more importantly reduce coatingof the notches between the electrodes from the atomicbeam reducing charge build up and the possibility ofshorting between electrodes. However, the atomic fluxcan also be directed parallel to the surface in anasymmetric ion trap due to the low atomic flux requiredfor photoionisation loading.

3. Linear ion traps

The previously mentioned ideal linear hyperbolic traponly provides confinement within the radial directionsand does not allow for optical access. By modifying thegeometry as depicted in Figure 4 linear ion traps arecreated. To create an effective static potential for theconfinement in the axial (z-axis) direction, the associateelectrodes are segmented. This allows for the creationof a saddle potential and when superimposed onto rfpseudopotential provides trapping in three dimensions.By selecting the appropriate amplitudes for the rf andstatic potentials such that the radial secular frequenciesox, oy are significantly larger than the axial frequencyoz, multiple ions will form a linear chain along the z-axis. The motion of the ion near the centre of the trapcan be considered to be harmonic as a very goodapproximation. The radial secular frequency of a lineartrap is on the order of that of a hyperbolic ion trap ofsame ion–electrode distance but different by a geo-metric factor Z [42].

3.1. Linear ion trap geometries

Linear ion trap geometries can be realised in a sym-metric or asymmetric design as depicted in Figure 4.

Figure 3. Wire bonding a microfabrciated chip to a chipcarrier providing external electrical connections.

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In symmetric designs the ions are trapped between theelectrodes, as shown for two- and three-layer designs inFigure 4(a) and (b), respectively. These types of designsoffer higher trap depths and secular frequenciescompared to asymmetric traps of the same trapparameters. Two-layer designs offer the highest secularfrequencies and trap depths whilst three-layer designsoffer more control of the ions position for micromo-tion compensation and shuttling.

The aspect ratio for symmetric designs is defined asthe ratio of the separation between the two sets ofelectrodes w and the separation of the layers d depictedin Figure 5. As the aspect ratio rises, the geometricefficiency factor Z decreases and approaches asympto-tically 1/p for two-layer designs [42]. Another advan-tage of symmetric traps is more freedom of opticallaser access, allowing laser beams to enter the trappingzone in various angles. In asymmetric trap structuresthe laser beams typically have to enter the trappingzone parallel to the trap surface. Asymmetric designsoffer the possibility of simpler fabrication processes.Buried wires [50] and vertical interconnects canprovide electrical connections to electrodes whichcannot be connected via surface pathways. Trapdepths are typically smaller than for symmetric iontraps, therefore higher voltages need to be applied toobtain the same trap depth and secular frequencies ofan equivalent symmetric ion trap. The widths of theindividual electrodes can be optimised to maximisetrap depth [51].

In order to successfully cool ions, Doppler coolingneeds to occur along all three principal axes thereforethe k-vector of the laser needs to have a componentalong all the principal axes. Due to the limitation ofthe laser running parallel to the surface it is importantthat all principal axes have a component along the k-vector of the Doppler cooling laser beam. Five-wiredesigns (Figure 6(b) and (c)) have a static voltageelectrode below the ion position, surrounded by rfelectrodes and additional static voltage electrodes.With the rf electrodes of equal width (Figure 6(b)) one

of the principal axes is perpendicular to the surface ofthe trap. However, it can be rotated via utilising two rfelectrodes of different width (Figure 6(c)) or via

Figure 4. Different linear trap geometries. (a) A two-layer design in which the rf electrodes (yellow) are diagonally opposite andthe dc electrodes (grey) are segmented. (b) A three-layer design in which the rf electrodes are surrounded by the dc electrodes. (c)A five-wire asymmetric design where all the electrodes lie in the same plane.

Figure 5. For two-layer traps the aspect ratio is defined asw/d.

Figure 6. Cross-section in the x7y plane of the differenttypes of asymmetric designs. (a) Four-wire design in whichthe principal axes are naturally non-perpendicular withrespect to the plane of the electrodes. (b) Five-wire designwhere the electrodes are symmetric and one principal axis isperpendicular to the surface. (c) Five-wire design withdifferent widths rf electrodes, this allows the principal axesto be rotated.

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splitting the central electrodes [48]. A four-wire designshown in Figure 6(a) has the principal axes naturallyrotated but the ion is in direct sight of the dielectriclayer below since the ion is located exactly above thetrench separating two electrodes. Deep trenches havebeen implemented [49,55] to reduce the effect ofexposed dielectrics.

3.2. From linear ion traps to arrays

For ions stored in microfabricated ion traps to becomeviable for quantum information processing, thousandsor even millions of ions need to be stored and interactwith each other. This likely requires a number ofindividual trapping regions that is on the same order asthe number of ions and furthermore, the ability for theions to interact with each other so that quantuminformation can be exchanged. This could be achievedvia arrays of trapping zones that are connected viajunctions. To scale up to such an array requiresfabrication methods that are capable of producinglarge scale arrays without requiring an unreasonableoverhead in fabrication difficulty. This makes somefabrication methods more viable for scalability thanother techniques. An overview of different fabricationmethods is discussed in more detail within Section 6.

The transport of ions through junctions was firstdemonstrated within a three-layer symmetric design[28] and later near-adiabatic in a two-layer symmetrictrap array [29], shown in Figure 7(a) and (b). Both iontrap arrays were made from laser machined aluminasubstrates incorporating mechanical alignment. Thenecessity of mechanical alignment and laser machininglimit the opportunity to scale up to much largernumbers of electrodes making other microfabricationmethods more suitable in the long term. Transportthrough an asymmetric ion trap junction (Figure 7(c))was then demonstrated by Amini et al. [50], however,this non-adiabatic transport required continuous laser

cooling. Wesenberg carried out a theoretical study [56]of how one can implement optimal ion trap arrayintersections. Splatt et al. demonstrated reordering ofions within a linear trap [57].

4. Simulating the electric potentials of ion trap arrays

Accurate simulations of the electric potentials areimportant for determining trap depths, secular frequen-cies and to simulate adiabatic transport including theseparation of multiple ions and shuttling throughcorners [45,58]. Various methods can be used indetermining the electric potentials from the trap electro-des, with both analytical and numerical methodsavailable. Numerical simulations using the finite elementmethod (FEM) and the boundary element method(BEM) [45,59] provide means to obtain the full 3Dpotential of the trap array. FEM works by dividing theregion of interest into a mesh of nodes and vertices, aniterative process then finds a solution which connects thenodes whilst satisfying the boundary conditions and apotential can be found for each node. BEM starts withthe integral equation formulation of Laplace’s equationresulting in only surface integrals being non-zero in anempty ion trap. Due to BEM solving surface integrals,this is a dimensional order less than FEM thus providinga more efficient numerical solution than FEM [45]. Toobtain the total potential the basis function method isused [45]. A basis function for a particular electrode isobtained by applying 1 V to one particular electrodewhilst holding the other electrodes at ground. Bysumming all the basis functions (with each basis functionmultiplied by the actual voltage for the particularelectrode) the total trapping potential can be obtained.

For the case of asymmetric ion traps, analyticalmethods provide means to calculate the trappingpotential significantly faster allowing for optimisationof the electrode structures. A Biot-Savart-like law [60]can be used and is related to the Biot-Savart law for

Figure 7. Junctions that have been used to successfully shuttle ions. The yellow parts represent the rf electrodes. Nosegmentation of the static voltage electrodes (grey) is shown. (a) T-junction design [28] where corner shuttling and swapping oftwo ions were demonstrated for the first time. While the transport was reliable the ion gained a significant amount of kineticenergy during a corner-turning operation. (b) A two-layer X-junction [29] was used to demonstrate highly reliable transportthrough a junction with a kinetic energy gain of only a few motional quanta. (c) A Y-junction [50] was used to demonstratetransport through an asymmetric junction design, however, requiring continuous laser cooling during the shuttling process.

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magnetic fields in which the magnetic field at a point ofinterest is obtained by solving the line integral of anelectrical current around a closed loop. This analogy isthen applied to electric fields in the case of asymmetricion traps [61]. One limitation for these analyticalmethods is the fact that all the electrodes must lie in asingle plane, with no gaps, which is referred to as thegapless plane approximation. House [62] has obtainedanalytical solutions to the electrostatic potential ofasymmetric ion trap geometries with the electrodeslocated on a single plane within a gapless planeapproximation. Microfabrication typically requiresgaps of a few micrometres [49] which need to becreated to allow for different voltages on neighbouringelectrodes. The approximation is suggested to bereasonable for gaps much smaller than the electrodewidths and studies into the effect of gapped and finiteelectrodes have been conducted [63]. However, withinthe junction region where electrodes can be very smalland high accuracy is required, the gapless planeapproximation may not necessarily be sufficient.

5. Electrical characteristics

5.1. Voltage breakdown and surface flashover

Miniaturisation of ion traps is not only limited by theincreasing motional heating of the ion (see Section 7),but also by the maximum applied voltages allowed bythe dielectrics and gaps separating the electrodes. Bothsecular frequency and trap depth depend on theapplied voltage. Therefore, it is important to highlightimportant aspects involved in electrical breakdown.Breakdown can occur either through the bulk material,a vacuum gap between electrodes, or across aninsulator surface (surface flashover). There are manyfactors which contribute to the breakdown of a trap,from the specific dielectric material used and itsdeposition process, residues on insulating materials tothe geometry of the electrodes itself and the frequencyof the applied voltage.

Bulk breakdown describes the process of break-down via the dielectric layer between two independentelectrodes. An important variable which has beenmodelled and measured is the dielectric strength. Thisis the maximum field that can be applied beforebreakdown occurs. The breakdown voltage Vc isrelated to the dielectric strength for an ideal capacitorby Vc ¼ dEc, where d is the thickness of the dielectric.There have been many studies into dielectric strengthsshowing an inverse power law relation Ec / d7n [64–70]. The results show a typical range of values (0.5 – 1)for the scaling parameter n. Although decreasing thethickness will increase the dielectric strength this willnot increase the breakdown voltage if the scalingparameter lies below one.

Surface flashover occurs over the surface of thedielectric material between two adjacent electrodes.The topic has been reviewed [71] with studies showinga similar trend with a distance dependency on thebreakdown voltage with Vb / d a where a � 0.5 [70,72].Surface flashover usually starts from electron emissionfrom the interface of the electrode, dielectric andvacuum known as the triple point. Imperfections atthis point increase the electric field locally and willreduce the breakdown voltage. The electric fieldstrength for surface breakdown has been measured tobe a factor of 2.5 less than that for bulk breakdown ofthe same material, dimensions and deposition process[70], with thicknesses of 1–3.9 mm for substratebreakdown and lengths of 5–600 mm considered.

The range of parameters that can affect breakdownfrom the difference between rf and applied staticvoltages [26,72,73] includes the dielectric material,deposition process and the geometry of the electrodes[71]. Therefore, it is most advisable to carry outexperimental tests on a particular ion trap fabricationdesign to determine reliable breakdown parameters. Ina particular design it is very important to avoid sharpcorners or similar features as they will give rise to largelocal electric fields at a given applied voltage.

5.2. Power dissipation and loss tangent

When scaling to large trap arrays the finite resistance Rand capacitance C of the electrodes as well as thedielectric materials within the trap structure result inlosses and therefore have to be taken into account whendesigning an ion trap. The power dissipation, which re-sults from rf losses, is highly dependent on the materialsused and the dimensions of the trap structure and canresult in heating and destruction of trap structures. Tocalculate the power dissipated in a trap a simple lumpedcircuit model, as shown in Figure 8, can be utilised.

The dielectric material insulating the electrodescannot be considered a perfect insulator resulting in acomplex permittivity e, with e ¼ e0 þ ie00. Lossless partsare represented by e0 and lossy parts by e00. Substitutingthis into Ampere’s circuital law and by rearranging oneobtains [74]

r�H ¼ sþ oE00ð Þ � ioE0½ �E: ð10Þ

Figure 8. The rf electrode modelled with resistance R,capacitance C, inductance L and conductance G.

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s is the conductivity of the dielectric for an appliedalternating current, and o is the angular frequency ofthe applied field. The effective conductance is oftenreferred to as s0 ¼ s þ oe00. The ratio of the conduc-tion to displacement current densities is commonlydefined as loss tangent tan d

tan d ¼ sþ oE00

oE0: ð11Þ

For a good dielectric the conductivity s is muchsmaller then oe00 and we can then make the followingapproximation tand ¼ e00/e0. For a parallel platecapacitor the real and imaginary parts of the permit-tivity can be expressed as [75]

e0 ¼ Cd

e0A; e00 ¼ Gd

e0oA: ð12Þ

Substituting this into the approximated loss tangentexpression, the conductance G can be expressed as

G ¼ oC tan d: ð13Þ

Now we can calculate the power dissipated through therf electrodes driven by frequency o ¼ OT, with Irms ¼Vrms /Z. The total impedance for this circuit is

Z ¼ R� ioLþ Gþ ioCG2 þ o2C2

: ð14Þ

The second term of the impedance represents theinductance L of the electrodes, which we approximatewith the inductance of two parallel plates separated bya dielectric with L ¼ ml(d/w) [76]. Assuming a dielectricof thickness d � 10 mm, electrode width w � 100 mm,electrode length l � 1 mm, magnetic permeability ofthe dielectric m � 1076(H/m) [77], the inductance canbe approximated to be L � 10710 H. Comparing theimaginary impedance terms ioL and io[C/(G2 þo2C2)], it becomes clear that the inductance can beneglected. The average power dissipated in a lumpedcircuit is given by Pd ¼ Re(VrmsIrms

* ) [78]. Using theapproximation for the total impedance Z ¼ R þ [(Gþioc)/(G2 þ o2C2)] we obtain

Pd ¼V2

0RðG2 þ C2o2Þ2

2ðC2o2 þ R2ðG2 þ C2o2Þ2Þð15Þ

and using Equation (13) one obtains

Pd ¼V2

0O2TC

2Rð1þ tan2dÞ2

2ð1þ O2TC

2R2ð1þ tan2dÞ2Þ: ð16Þ

In the limit where tand and OTCR � 1, the dissipatedpower can be simplified as Pd ¼ 1

2V20O

2TC

2R. Consider-ing Equation (16), important factors to reduce power

dissipation are an electrode material with low resistiv-ity, a low capacitance of the electrode geometry and adielectric material with low loss tangent at typical drivefrequencies (OT ¼ 10–80 MHz).

Values for loss tangent have been studied in theGHz range for microwave integrated circuit applica-tions [79] and diode structures at kHz range [75,80,81].Generally the loss tangent decreases with increasingfrequency [82,83] and there has been a temperaturedependence shown for specific structures [80]. Valuesat 1 MHz can be obtained but are dependent on thestructures tested; Au/SiO2/n-Si tand*0.05 [75], Au/Si3N4/p-Si tand*0.025 [81], Cr/SiO1.4/Au tand *0.09[84]. The loss tangent will be dependent on the specificstructure and also dependent on the doping levels. It issuggested that the loss tangent for specific materialsbe requested from the manufacturer or measuredfor the appropriate drive frequency. For optimaltrap operation, careful design considerations have tobe made to reduce the overall resistance and capa-citance of the trap structure minimising the dissipatedpower.

6. Fabrication processes

Using the information given in the previous sectionsabout ion trap geometries, materials and electricalcharacteristics, common microfabrication processescan be discussed. One of the main criteria for choiceof fabrication process is the compatibility with a desiredelectrode geometry. Asymmetric and symmetric geo-metries result in different requirements and thereforewe will discuss them separately. First, process designsfor asymmetric traps will be discussed followed bysymmetric ion trap designs and universally compatibleprocesses. The compatibility of a process with discussedmaterials, and geometries will be highlighted. Structur-al characteristics and limitations of a process will beexplained and solutions will then be given. As the exactfabrication steps depend on materials used and avail-able equipment, the process sequences will be discussedas generally possible. However, to give the reader aguideline of possible choices, material and process stepdetails of published ion traps will be given in brackets.The discussion will start with a simple process that canbe performed in a wide variety of laboratories and isoffered by many commercial suppliers.

6.1. Printed circuit board (PCB)

The first discussed fabrication technique used for iontrap microfabrication is the widely available PrintedCircuit Boards (PCB) process. This technology iscommonly used to create electrical circuits for a widevariety of devices and does not require cleanroom

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technology. For ion traps generally a monolithic singleor two layer PCB process is used. Monolithic processesrely on the fabrication of ion trap structures by addingto or subtracting material from one component. Incontrast to this, wafer bonding, mechanical mountingor other assembly techniques are used to fabricatetraps from pre-structured, potentially monolithic partsin a non-monolithic process. When combined withcleanroom fabrication such a process can be used forvery precise and large scale structures, however,mechanical alignment remains an issue.

PCB processes commonly allow for minimalstructure sizes of approximately 100 mm [85] and slotsmilled into the substrate of 500 mm width. This limitsthe uses of this technique for large and complexdesigns but also results in a less complex and easieraccessible process. Smaller features are possible withspecial equipment, which is not widely available. Thefollowing section will give a general introduction intothe PCB processes used to manufacture ion traps.

This process is based on removing material insteadof depositing materials as used in most cleanroomprocesses. Therefore, the actual process sequence startsby selecting a suitable metal coated PCB substrate. Thesubstrate has to exhibit the characteristics needed forion trapping, ultra high vacuum (UHV) compatibility,low rf loss tangent and high breakdown voltage(commercially available high-frequency (hf) Rogers4350B used in [85]). One side of the PCB substrate isgenerally pre-coated with a copper layer by themanufacturer, which is partially removed in the processto form the trap structures as shown in Figure 9(c).Possible techniques to do this are mechanical milling

shown in Figure 9(b) or chemically wet etching using apatterned mask. The mask can either be printed directlyonto the copper layer or photolithography can be usedto pattern photo resist as shown in Figure 9(a). Toreduce exposed dielectrics and prevent shorting frommaterial deposited in the trapping process, slots can bemilled into the substrate underneath the trapping zonesas shown in Figure 9(d).

The fabricated electrodes form one plane and makethe process unusable for symmetric ion traps (SIT). Notonly are the electrodes located in one plane they also sitdirectly on the substrate, which makes a low rf losstangent substrate necessary to minimise energy dissipa-tion from the rf rails into the substrate. As explained inSection 5.2 high power dissipation leads to an increaseof the temperature of the ion trap structure and alsoreduces the quality factor of the loaded resonator. PCBsubstrates intended for hf devices generally exhibit alow rf loss tangent (values of tand ¼ 0.0031 are typical[87]) and many are UHV compatible, therefore can beused for ion traps. Other factors reducing the qualityfactor are the resistances and capacitances of theelectrodes. When slots are milled into the substrateexposed dielectrics underneath the ion can be avoideddespite the electrode structures being formed directlyon the substrate. The otherwise exposed dielectricswould lead to charge built up underneath the ionresulting in stray fields pushing the ion out of the rf niland leading to micromotion. By relying on widelyavailable fabrication equipment this technique enabledthe realisation of several ion trap designs with micro-metre-scale structures, published in [57,85,86,88,89],without the need for cleanroom techniques.

Figure 9. Overview of several PCB fabrication processes. (a) Deposition and exposure of the resist used as a mask in later etchsteps. (b) Removal of the top copper layer using mechanical milling. (c) Removal of the copper layer using a chemical wet etchand later removal of the deposited mask. (d) Mechanical removal of the substrate underneath the trapping zone [86].

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The discussed single layer PCB process can be usedfor electrode geometries including y-junctions and lin-ear sections. More complex topologies with isolatedelectrodes and buried wires require a more complextwo-layer process. To address limitations caused by theminimal structure separations and sizes allowing forion traps with higher electrode and trapping-zonedensities, a process based on common cleanroomtechnology will be discussed next.

6.2. Conductive structures on substrate (CSS)

Common cleanroom fabrication techniques like highresolution photolithography, isotropic and anisotropicetching, deposition, electroplating and epitaxialgrowth allow a very precise fabrication of large scalestructures. The monolithic technique we discuss here isbased on a ‘conductive structures on substrate’ processand was used to fabricate the first microfabricatedasymmetric ion trap (AIT) [27]. Electrode structuresseparated by only 5 mm [48] can be achieved with thisprocess and smaller structures are not limited by theprocess but flashover and bulk breakdown voltage ofthe used materials. The structures are formed by meansof deposition and electroplating of conductive materialonto a substrate instead of removing precoatedmaterial. This makes it possible to use a much widervariety of materials in a low number of process steps.Several variations or additions were published [27,90–93] to adjust the process for optimal results withdesired materials and structures.

First the standard process will be presented, whichstarts by coating the entire substrate (for example,

polished fused quartz as used in [27]) with a metal layerworking as a seed layer (0.1 mm copper), necessary fora following electroplating step. Commonly an adhe-sion layer (0.03 mm titanium) is evaporated first, asmost seed layer materials ([27,92]) have a low adhesionon common substrates, see Figure 10(a). Then apatterned mask (photolithographic structured photoresist) with a negative of the electrode structures isformed on the seed layer. The structures are thenformed by electroplating (6 mm gold) metal onto theseed layer, see Figure 10(b). Afterwards the patternedmask is no longer needed and removed. The seed layer,providing electrical contact between the structuresduring electroplating, also needs to be removed toallow trapping operations. This can be done using theelectroplated electrodes as a mask and an isotropicchemical wet etch process to remove the material, seeFigure 10(c). Then the adhesion layer is removed in asimilar etch process (for example using hydrofluoricacid) and the completed trapping structure is shown inFigure 10(d).

Depending on the available equipment additionalor different steps can be performed, which also allowspecial features to be included on the chip. Onevariation was published in [92] replacing the seed layerwith a thicker metal layer (1 mm silver used in [92]) andforming the patterned mask on top of that, as shown inFigure 11(a). The electrode structures are then formedby using this mask to wet etch through the thick silverlayer (NH3OH: H2O2 silver etch) and the adhesionlayer (hydrofluoric acid) Figure 11(b). To counterpotentially sharp electrode edges resulting from the wetetch process an annealing step (7208C to 7608C for 1 h)

Figure 10. Fabrication sequence of the standard ‘Conductive Structures on Substrate’ process. (a) The sequence starts with thedeposition of an adhesion and seed layer. (b) An electroplating step creating the electrodes using a patterned mask. (c) Removalof the mask followed by a first etch step removing the seed layer. (d) Second etch step removing the adhesion layer.

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was performed to reflux the material and flatten thesharp edges. An ion trap with superconductiveelectrodes was fabricated using a similar process [91].Low temperature superconductors Nb and NbN weregrown onto the substrate in a sputtering step. Then theelectrodes were defined using a mask and an aniso-tropic etch step. An annealing step was not performedafter this etch step. With this variation of the standardprocess electroplating equipment and compatiblematerials are not needed to fabricate an ion trap.

A possible addition to the process was presented in[27] incorporating on-chip meander line resistors onthe trap as part of the static voltage electrode filters.Bringing filters closer to the electrodes can reduce thenoise induced in connecting wires as the filters aretypically located outside the vacuum system or on thechip carrier. On-chip integration of trap features isessential for the future development of very large scaleion trap arrays with controls for thousands ofelectrodes needed for quantum computing.

In order to allow for appropriate resistance valuesfor the resistors, processing of the chip occurs in twostages. Within the first stage only the electrodegeometry is patterned with regions where resistorsare to be fabricated entirely coated in photoresist. Thisstep consists of patterning photo resist on the substrate(for example polished fused quartz [27]) to shape theelectrodes followed by the deposition of the standardadhesion (0.030 mm titanium) and seed layers (0.100mm copper) on the substrate (thicknesses statedcorrespond to the values used by Seidelin et al. [27]).After the electrodes have been patterned, the first mask

is removed. In the next step, only the on-chip resistorsare patterned allowing for different thickness ofconducting layers used for resistors. A second maskis patterned on the substrate parts reserved for the on-chip resistors. Then an adhesion layer (0.013 mmtitanium) and metal layer (0.030 mm gold) is depositedforming the meander lines as shown in Figure 11(c).The mask is removed and the rest of the sequencefollows the standard process steps. This processillustrates one example for on-chip features integratedon the trap. Another process was published in [90],which integrates on-chip magnetic field coils togenerate a magnetic field gradient at the trappingzone. It was fabricated using the standard process anda specific mask to form the electrodes incorporatingthe coils.

Most published variations [27,48,90–95] of thisprocess feature structure sizes much smaller thanachievable with the PCB process but similar to itelectrodes sit directly on the substrate resulting in thesame rf loss tangent requirements. It also makes theprocess incompatible with symmetric ion traps. As aresult of the smaller structure separations, high flash-over and bulk breakdown voltages are also more imp-ortant. Because no slots are milled into the substrateelectric charges can accumulate on the dielectricsbeneath the trapping zones, which can result in strayfields and additional micromotion. To reduce thiseffect a high aspect ratio of electrode height toelectrode–electrode distance is desirable.

Similar to the one-layer PCB process, topologiesincluding junctions are possible but isolated electrodes

Figure 11. Different variations of the standard CSS process are shown. (a) Conductive material is deposited on the entiresubstrate and a resist mask is structured. (b) Structured electrodes after the etch step. (c) On chip resistor meander line, reportedin [27]. (d) Variation without exposed dielectrics underneath the trapping zone with free hanging rf rails [93].

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are prohibited by the lack of buried wires. By movingtowards cleanroom fabrication techniques it is possiblewith this process to reduce the electrode–electrodedistance and increase the trapping zone density. Thescalability is still limited and the exposed dielectrics canlead to unwanted stray fields. To counter the exposeddielectrics another variation and a different processfeaturing ‘patterned silicon on insulator (SOI) layers’can be used and will be explained in Section 6.3.

One variation of this process that prevents exposeddielectrics was fabricated by Sandia National Labora-tory [93] featuring free standing rf rails with a largesection of the substrate underneath the trapping regionbeing removed. Electrodes consist of free standingwires held in place by anchor-like structures fabricatedon the ends of the slot in the substrate as shown inFigure 11(d). To prevent snapping under stress thewires are made from connected circles increasing theflexibility. While no dielectrics are exposed the design’sscalability and compatibility with different electrodegeometries is limited as the rf rails are suspendedbetween the anchors in a straight line.

6.3. Patterned silicon on insulator layers (SOI)

The ‘Patterned Silicon on Insulator Layers’ processmakes use of commercially available silicon-on-insu-lator (SOI) substrates and was first reported by Brittonet al. [49]. Similar to the PCB process this techniqueremoves parts of a substrate instead of adding materialto form the ion trap structures. Using the selective etchcharacteristics of the oxide layer between the twoconductive silicon layers of the substrate, it is also

possible to create an undercut of the dielectric andshield the ion from it, without introducing severalprocess steps. A metal deposition step performed atthe end of the process to lower the electrode resistancedoes not require an additional mask, keeping thenumber of process steps low. Therefore, this processallows for much more advanced trap structures with-out increasing the number of process steps by makingclever use of a substrate.

The substrates are available with insulator thick-nesses of up to 10 mm and different Si doping gradesresulting in different resistances. After a substrate withdesired characteristics (100 mm Si, 3 mm SiO2, 540 mmSi in [49]) is found, the process sequence starts withphotolithographic patterning of a mask on the top SOIsilicon layer as shown in Figure 12(a). The mask isused to etch through the top Si layer, see Figure 12(b),by means of an anisotropic process (Deep Reactive IonEtching (DRIE)). Using a wet etch process the exposedSiO2 layer parts are removed and an undercut isformed to further reduce exposed dielectrics as shownin Figure 12(c). If the doping grade of the top Si layeris high enough the created structure can already beused to trap ions.

To reduce the resistance of the trap electrodesresulting from the use of bare Si a deposition step canbe used to apply an additional metal coating onto theelectrodes. No mask is required for this deposition step,the adhesion layer (chromium or titanium) and metallayer (1 mm gold, in [49]) can be deposited directlyonto the silicon structures as shown in Figure 12(d).This way the electrodes and the exposed parts of thesecond Si layer will be coated. This has the benefit that

Figure 12. Fabrication sequence of the SOI process. (a) Resist mask is directly deposited on the substrate. (b) First silicon layeris etched in an anisotropic step. (c) Isotropic selective wet etch step removing the SiO2 layer and creating an undercut. (d)Exposed Si layers coated with adhesion and conductive layer to reduce overall resistance.

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possible oxidisation of the lower silicon layer is alsoavoided. A slot can be fabricated into the substrateunderneath the trapping zone, which allows backsideloading in these traps [49]. This slot is microfabricatedby means of anisotropic etching using a patterned maskfrom the backside. The benefit of such a slot is that theatom flux needed to ionise atoms in the trapping regioncan be created at the backside and guided perpendi-cular to the trap surface away from the electrodes.Therefore, coating of the electrodes as a result of theatom flux can be minimised.

An ion trap based on the SOI process wasfabricated with shielded dielectrics by Britton et al.[49]. A similar approach is used by Sterling et al. [96] tocreate 2D ion trap arrays. Similar to the standard CSSprocess, discussed in the previous section, y-junctionsand other complex topologies are possible, but buriedwires are prohibited. The process design incorporates alimited material choice for substrate and insulatorlayer. Only the doping grade of the upper and lowerconductive layers can be varied not the material. Theinsulator layer separating the Si layers must becompatible with the SOI fabrication technique andcommercially available materials are SiO2 and Al2O3

(Sapphire). Adjustments of electrical characteristics,like rf loss tangent and electrode capacitances aretherefore limited to the two insulator materials andgeometrical variations.

To further increase the scalability and trappingzone density of ion traps, process techniques shouldincorporate buried wires to allow isolated staticvoltage and rf electrodes. Examples of such monolithicprocesses will be discussed next, first a process

incorporating buried wires but exhibiting exposeddielectrics will be presented followed by a processallowing for buried wires and shielding of dielectrics.

6.4. Conductive structures on insulator with buriedwires (CSW)

The process to be discussed here is a further develop-ment of the CSS process discussed in Section 6.2,which adds two more layers to incorporate buriedwires. With these it is possible to connect isolated staticvoltage and rf electrodes and was used to fabricate anion trap with six junctions arranged in a hexagonalshape [50], see Figure 13(a). The capability of buriedwires is essential for more complex ion trapping arraysthat could be used to trap hundreds or thousands ofions necessary for advanced quantum computing.

The process starts with the deposition of the buriedconductor layer (0.300 mm gold layer [50]) sandwichedbetween two adhesion layers (0.02 mm titanium) on thesubstrate (380 mm quartz) and a patterned mask isdeposited on these layers. Conductor and adhesionlayers are then patterned in an isotropic etch step, seeFigure 13(b) and then buried with an insulator material(1 mm SiO2 deposited by means of chemical vapourdeposition (CVD)). To establish contact betweenelectrodes and the buried conductor, windows areformed in the insulator layer (plasma etching) asshown in Figure 13(c). Then another patterned mask isused to deposit an adhesion and conductor layerforming the electrodes (0.020 mm titanium and 1 mmgold). In this deposition step the windows in theinsulator are also filled and connection between buried

Figure 13. Process sequence for the buried wire process. (a) Hexagonal shaped six junction ion trap array [50]. (b) A structuredresist mask is deposited and the mask is used to form wires in a following wet etch step. (c) The wires are then buried with anoxide layer and windows are formed in the oxide. (d) With another mask the electrodes are deposited on top of the wires andoxide layer.

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conductor and electrodes is established as shown inFigure 13(d). For this ion trap a backside loading slotwas also fabricated using a combination of mechanicaldrilling and focused ion beam milling to achieve aprecise slot in the substrate [50]. As demonstrated byAmini et al. [50] this process allows for large scale iontrap arrays with many electrodes and trapping zones.While the scalability is further increased, this parti-cular process design results in exposed dielectrics. Thenext process improves this further by shielding theelectrodes and the substrate.

6.5. Conductive structures on insulator with groundlayer (CSL)

To achieve buried wires or in this case vertical inter-connect access (vias) and shielding of dielectrics a mono-lithic process including a ground layer and overhangingelectrodes can be carried out. Several structured anddeposited layers are necessary for this process and whileproviding the greatest flexibility of all processes it alsoresults in a complicated process sequence. Therefore,these processes are commonly performed using Very-Large-Scale Integration (VLSI) facilities that are capableof performing many process steps with high reliability.

A process design, which makes use of vias, waspresented by Stick et al. [97]. In this process design thesubstrate (SOI in [97]) is coated with an insulator and astructured conductive ground layer (1 mm Al) as shownin Figure 14(a). This is followed by a thick structuredinsulator (9–14 mm). The trapping electrodes are thenplaced in a plane above the thick insulator. Theelectrodes overhang the thick insulator layer and incombination with the conductive ground layer shieldthe trapping zone from dielectrics. Vias are used toconnect static electrodes to the conductive layerbeneath the thick insulator as shown in Figure 14(b).The process also includes creation of a backsideloading slot.

A variation from the discussed process making useof a ground plate without vias is described byLeibrandt et al. [98] and more detailed process stepsare given in [93].

The described process design [97] combines viaswith shielded dielectrics and also makes the trapstructures independent from the substrate. Therefore,the same level of scalability as the CSW process,discussed in the previous section, can be achieved whiledielectrics are shielded similar to the SOI process,described in Section 6.3. The process uses aluminium toform the electrodes which can lead to oxidisation andunwanted charge build up. To avoid this the electrodescould be coated with gold or other non-oxidisingconductors in an additional step. Easier choice ofsubstrate, isolator and electrode materials combinedwith vias and shielded dielectrics make this process wellsuited for very large scale asymmetric ion traps withhigh trapping zone densities and low stray fields. Withelectrodes in one plane and another conductive layerabove the substrate this structure could also be used tofabricate a symmetric ion trap (SIT).

6.6. Double conductor/insulator structures onsubstrate (DCI)

Symmetric ion traps have electrodes placed in two orthree planes with the ions trapped between the planes.Therefore, electrodes need to be precisely structured inseveral vertically separated layers and cannot befabricated in one plane resulting in different require-ments on the microfabrication processes. In the DCIprocess described here a specifically grown substratewith selective etch capabilities similar to SOI substratelayers is used and all electrodes are structured in oneetch step. The first such microfabricated ion trap wascreated by Stick et al. [26] using this process with MBEgrown AlGaAs, GaAs structures and constitutes thefirst realisation of a monolithic ion trap chip.

Figure 14. Two variations of the CSL process sequence. (a) In the process sequence published in [97] an insulating layer and astructured metal ground layer are deposited on the substrate. (b) Electrodes fabricated in one plane, with outer static voltageelectrodes connected through vias [97].

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The process starts by growing alternating layers(AlGaAs 4 mm, GaAs 2.3 mm) on a substrate using anMBE system as shown in Figure 15(a). The dopinggrades and atomic percentages (70% Al, 30% GaAsAlGaAs layer, GaAs layers highly doped 3 6 1018

cm73) are chosen to achieve low power dissipation in theelectrodes. After the structure is grown a slot is etchedinto the substrate from the backside to allow opticalaccess as shown in Figure 15(b). To provide electricalcontact to both GaAs layers an anisotropic etch processis performed to remove parts of the first AlGaAs andGaAs layers, then metal is deposited onto parts of thetop GaAs and the now exposed lower GaAs layer asshown in Figure 15(c). This is followed by an anisotropicetch step defining all the electrode structures. Afollowing isotropic etch step creates an undercut of theinsulating AlGaAs layer to increase the distance betweentrapping zone and dielectric, see Figure 15(d).

This ion trap chip could only be operated at verylow rf amplitudes of 8 V as a result of the lowbreakdown voltage of the insulating AlGaAs materialand possible residues on the insulator surfaces. Thisproblem can be addressed by choosing a different and/or thicker insulator material.

Removing the insulator material between theelectrode layers can avoid this problem almost entirelyand was used in the design described by Hensingeret al. [99]. This structure is based on depositing layersinstead of using a specifically grown substrate andetching material away. It incorporates a selectivelyetchable oxide layer, which can be completely removed

after electrodes are created on this layer. This sacri-ficial layer allows for cantilever like electrodes withoutany supporting oxide layers. Therefore, breakdowncan only occur over the surfaces and the capacitancebetween electrodes is kept at a minimum.

The process starts with the deposition of aninsulating layer (Si3N4) on an oxidised Si substrate asshown in Figure 16(a). Then a conductor layer(polycrystal silicon [99]) is deposited onto the insulatorand structured using an anisotropic etch process(DRIE) with a mask. Now selectively etchablesacrificial material (polysilicon glass) is deposited onthe conductor structures. With a second mask windowsare etched into the insulator layer allowing verticalconnections to the following upper electrodes, seeFigure 16(b). This is followed by another conductorlayer (polycrystalline silicon) deposited onto thepatterned insulator also filling the previously etchedwindows. Then an anisotropic etch is performed tostructure the top conductor layer as shown in Figure16(c). An etch step using a mask is then performedfrom the backside through the entire substrate creatinga slot in the silicon substrate. With an isotropicselective hydrofluoric etch the sacrificial material usedto support the polycrystal silicon electrodes duringfabrication is completely removed. The electrodes nowform cantilever like structures and the previouslycreated slot in the substrate allows optical access tothe trapping zone, see Figure 16(d).

This design potentially allows for the application ofmuch higher voltages (breakdown for this design

Figure 15. Fabrication process used for the symmetric trap published in [26]. (a) Alternately grown conductive and insulatinglayers on a substrate. (b) Backside wet etch step to allow for optical access of the trapping zone. (c) Structured top GaAs andAlGaAs layers, formed in an etch step using a mask. Metal contacts deposited on both electrode layers. (d) Structured top andbottom electrodes separated by the insulator layers and undercuts are formed by a selective wet etch.

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would occur over an insulator surface rather thanthrough insulator bulk).

Independent of the material, the distance betweenthe two electrode planes is limited by the maximalallowable insulator thickness which is often deter-mined by particular deposition and etch constraints.To keep the ion–electrode distance at a desired levelthe aspect ratio of horizontal and vertical electrode–electrode distances (see Figure 16(d)) has to be muchhigher than one. As described in Section 3.1 this leadsto a low geometric efficiency factor Z and reduces thetrap depths and secular frequencies of these traps. Byforming the electrodes on the upper and lower side ofan oxidised substrate this aspect ratio can be drama-tically decreased. A process technique following thisconsideration will be discussed next.

6.7. Double conductor structures on oxidised siliconsubstrate (DCS)

In this proposed monolithic process [100] an oxidisedsilicon substrate separates the electrode structures,which allows for much higher electrode to electrodedistances. Making use of both sides of the substrateseparates this process from all other described techni-ques. It allows electrode–electrode distances of hun-dreds of micrometres, which would otherwise beimpossible due to maximal thicknesses of deposited orgrown oxide layers. Therefore, a ratio of one for thehorizontal and vertical electrode–electrode distancescan be achieved, resulting in an optimal geometricefficiency factor Z. The trap is fabricated in several

process steps starting with the oxidisation of a siliconwafer. Using an anisotropic etch process and apatterned mask, slots are then formed in the SiO2

layers on both sides exposing the Si wafer and creatingthe future trenches between electrodes as shown inFigure 17(a). Then conductive layers are deposited onboth sides of the wafer forming the two electrode layers.The individual electrodes are then created on both sidesin an anisotropic etch step using a patterned mask asshown in Figure 17(b). This is followed by an isotropicwet etch through the silicon using another maskresulting in an under cut of the electrodes and providingthe optical access as shown in Figure 17(c). The nowexposed dielectric SiO2 layers are then coated in ashadow metal evaporation process and the remainingmask is removed. After all conductor layers aredeposited, the layer thickness is increased by means ofelectroplating resulting in the final structure shown inFigure 17(d) [100]. By using the entire substrate toseparate the electrodes this proposed process sequenceallows for a low aspect ratio of horizontal and verticalelectrode–electrode distance. All electrodes sit on adielectric material increasing the importance of a low rfloss tangent of the insulating SiO2 layers.

6.8. Assembly of precision machined structures(PMS)

Non-monolithic fabrication processes are commonlybased on the assembly of pre-structured parts, usingtechniques like wafer bonding or mechanical clamping.The scalability of non-monolithic processes can be

Figure 16. Process sequence for the trap proposed in [99]. (a) Insulator layer deposited on the substrate. (b) Structured electrodeconductor layer and a second selectively etchable insulator is deposited and structured. (c) The second conductor layer isdeposited, making a vertical electrical connection to the lower conductor layer and is structured using an anisotropic etchprocess. (d) All selectively etchable insulator layers are removed and a backside etch is performed creating a slot in the substrate.

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limited due to this and therefore are commonly used forion traps with only one or a few trapping zones.Systems with thousands of isolated electrodes would bedifficult to realise with a non-monolithic process. Adv-antages of the non-monolithic processes are a greaterchoice of materials used and fabrication techniques,ranging from machined metal structures over lasermachined alumina, to structured Si substrates.

A non-monolithic process can be based on theassembly of precision machined structures commonlydone in workshops and will not be discussed in detail.Two examples for ion traps fabricated with thisprocess are the needle trap with needle tip radius ofapproximately 3 mm reported by Deslauriers et al. [101]and a blade trap used by McLoughlin et al. in [52].More complex ion trap geometries including junctionsand more electrodes can also be realised with

non-monolithic processes and will therefore be dis-cussed next.

6.9. Assembly of laser machined alumina structures(LMA)

Trap structures can be created by precision laser machi-ning and coating of alumina substrates and mechani-cally assembling these using spacers and clamps asshown in Figure 18. The structures are created by lasermachining slots into an alumina substrate resulting incantilevers providing the mechanical stability for theelectrodes, see Figure 18(a). The alumina cantileversare then coated with a conductive layer, commonlymetal, to form the electrodes. To prevent electricalshorting between the electrodes a patterned mask isused during this step. Several structured and coated

Figure 17. Process sequence as used by Brownnutt et al. [100]. (a) A structured insulator layer is deposited on both sides of thesubstrate. (b) Electrode structures are then deposited on this insulator layer. (c) Parts of the insulator are also removed in this stepand a slot is etched into the substrate. The top and bottom structures are then covered with a mask. (d) Shadow evaporation isused to coat exposed dielectrics close to the trapping zone. The mask is removed and the conductor layer thickness increased bymeans of electroplating.

Figure 18. ‘Assembly of Laser Machined Alumina structures’ process sequence. (a) Cantilever like structures are formed in thealumina structures using a laser. (b) Parts of the substrate are coated using a mask forming the electrodes and electricalconnections. Three similar layers are mounted on top of each other to form a three-layer symmetric trap.

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alumina plates are then mechanically assembled toform a two or three layer trap [28,29,102]. Normallyspacers are used to maintain an exact distance betweenthe plates, which are then exactly positioned and held inplace using mechanical pressure, see Figure 18(b).

One of the first ion traps with linear sections usingthis process was reported by Turchette et al. [102].Another example of such a trap was used for the firstdemonstration of corner shuttling of ions within a two-dimensional ion trap array [28]. Other traps fabricatedwith this process include the trap used for near adia-batic shuttling through a junction [29] and the trapsreported in [103,104]. The necessary alumina substratesshow a small loss tangent. A similar non-monolithicprocess based on clean room fabrication techniques,which allows for higher precision and greater choice ofsubstrate material, will be discussed next.

6.10. Wafer bonding of lithographic structuredsemiconductor substrates (WBS)

This process technique is similar to the monolithic SOIsubstrate technique discussed in Section 6.3 creating ahighly doped conductor on an insulator using waferbonding techniques. Much higher insulator thicknessescan be achieved with this process and many types ofinsulator and substrates can be used. This process wasused to fabricate symmetric and asymmetric ion traps.

First a process used for an asymmetric ion trap willbe discussed, starting with a commercially availablesubstrate (Si wafer, resistivity ¼ 500 6 1076 O cm).

Using anisotropic etching with a patterned mask(DRIE) the wafer is structured. All electrodes arephysically connected outside the trapping zone toprovide the necessary stability during the fabrication asshown in Figure 19(a). The structured substrate is thenbonded on another substrate with a sandwiched andstructured insulator layer providing electrical insula-tion and mechanical stability as shown in Figure 19(b).In the insulator layer a gap is formed underneath thetrapping region leaving no exposed dielectrics under-neath the ion. The bonding also provides the neededstructural stability and the physical connectionsbetween the electrodes can then be removed by dicingthe substrate, Figure 19(b). Similar to the SOIsubstrate process a conductive layer can be depositedon top of the structured substrate. A patterned mask isnot necessary and the conductive layer can be directlydeposited. Depending on the material used andsubstrate an adhesion layer has to be added.

Another variation of this process can be used tofabricate symmetric ion traps. Both substrates areidentically structured and wafer bonded. An additionaletch step is introduced to make the substrate thinneradjacent to the trapping zone in order to improveoptical access as shown in Figure 19(c). Similar to theasymmetric trap, the parts are then wafer bondedtogether with a sandwiched insulator layer Figure19(d). When used for asymmetric traps the dielectricsare completely shielded from the trapping zone and forthe case of symmetric traps the dielectrics can be placedfar away from the trapping zone. Possible geometries

Figure 19. Processes used to fabricate symmetric and asymmetric non-monolithic ion traps via waver bonding. (a)Microfabricated structures used for the assembly of an asymmetric trap. The structures are still physically connected within eachlayer. (b) These parts are then waferbonded together and physical connections are removed forming the trap structure. (c)Microfabricated parts used for a symmetric trap. (d) Waferbonded parts creating a symmetric trap.

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for asymmetric ion traps are limited with this techniqueas buried wires and therefore isolated electrodes are notpossible. The fabrication method and choice ofelectrode materials used for this trap can result in avery low surface roughness of less than 1 nm.

7. Anomalous heating

One limiting factor in producing smaller and smaller iontraps is motional heating of trapped ions. While it onlyhas limited impact in larger ion traps it becomes moreimportant when scaling down to very small ion–electrode distances. The most basic constraint is toallow for laser cooling of the ion. If the motionalheating rate is of similar magnitude as the photonscattering rate, laser cooling is no longer possible.Therefore, for most applications, the ion–electrodedistance should be chosen so the expected motionalheating rate is well below the photon scattering rate.Depending on the particular application, there may bemore stringent constraints. For example, in order torealise high fidelity quantum gates that rely on motionalexcitation for entanglement creation of internal states[105,106], motional heating should be negligible on thetime scale of the quantum gate. This timescale istypically related to the secular period 1/om of the ionmotion, however, it can also be faster [107]. Motionalheating of trapped ions in an ion trap is caused byfluctuating electric fields (typically at the secularfrequency of the ion motion). These electric fieldsoriginate from voltage fluctuations on the ion trapelectrodes. One would expect some voltage fluctuationsfrom the electrodes due to the finite impedance of thetrap electrodes, this effect is known as Johnson noise.Resulting heating would have a 1/d 2 scaling [102] whered is the characteristic nearest ion–electrode distance.However, in actual experiments a much larger heatingrate has been observed. In fact, heating measurementstaken for a variety of ions and ion trap materials seemto loosely imply a 1/d 4 dependence of the motionalheating rate _�n. A mechanism beyond Johnson noisemust be responsible for this heating and this mechanismwas termed ‘anomalous heating’. In order to establish amore reliable scaling law, an experiment was carried outwhere the heating rate of an ion trapped between twoneedle electrodes was measured [101]. The experimentalsetup allowed for controlled movement of the needleelectrodes. It was therefore possible to vary the ion–electrode distance and an experimental scaling law wasmeasured _�n � 1=d 3:50:1 [101]. The motional heating ofthe secular motion of the ion can be expressed as [102]

_�n ¼ q2

4m�homSEðomÞ þ

o2m

2O2T

SEðOT omÞ !

: ð17Þ

om is the secular frequency of the mode of interest,typically along the axial direction of the trap, OT isthe drive frequency and the power spectrum of theelectric field noise is defined as SEðoÞ ¼

R1�1hEðtÞ

Eðtþ tÞi exp ðiotÞ dt. The second term represents thecross-coupling between the noise and rf fields and canbe neglected for axial motion in linear traps as theaxial confinement is only produced via static fields[15,102].

A model was suggested to explain the 1/d 4 trendthat considered fluctuating patch potentials; a largenumber of randomly distributed ‘small’ patches on theinside of a sphere, where the ion sits at centre at adistance d [102]. All patches have a power noisespectral density that influence the electric field at theion position, over which is averaged to eventuallydeduce the heating rate. Figure 20 shows a collectionof published motional heating results. Instead ofplotting the actual heating rate, we plot the spectralnoise density SE (om) multiplied with the secularfrequency in order to scale out behaviour fromdifferent ion mass or different secular frequenciesused in individual experiments. We also plot a 1/d4

trend line. We note that previous experiments [52,101]consistently showed SE (om) * 1/om allowing thesecular frequency to be scaled out by plotting SE

(om) 6 om rather than just SE (om). In the experimentby Deslauriers et al. [101], another discovery wasmade. The heating rate was found to be massivelysuppressed by mild cooling of the trap electrodes.Cooling the ion trap from 300 K down to 150 Kreduced the heating by an order of magnitude [101].This suggests the patches are thermally activated.Labaziewicz et al. [92] measured motional heating fortemperatures as low as 7 K and found a multiple-order-of-magnitude reduction of motional heating atlow temperatures. The same group measured a scalinglaw for the temperature dependence of the spectralnoise density for a particular ion trap as SE (T) ¼ 42(1þ (T/46K)4.1) 6 10715 V2 m72 Hz71 [94]. Super-conducting ion traps consisting of niobium andniobium nitride were tested above and below thecritical temperature Tc and showed no significantchange in heating rate between the two states [91].Within the same study, heating rates were reported forgold and silver trap electrodes at the same temperature(6 K) showing no significant difference between the twoand superconducting electrodes. This suggests thatanomalous heating is mainly caused by noise sourceson the surfaces, although the exact cause of anomalousheating is not yet fully understood. From theinformation available, it is likely that surface proper-ties play a critical role, however, other factors such asmaterial bulk properties, oxide layers may also play animportant role and much more work is still needed to

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fully understand and control anomalous heating.While anomalous heating limits our ability to makeextremely small ion traps, it does not prevent the use ofslightly larger microfabricated ion traps. Learning howto mitigate anomalous heating is therefore not aprerequisite for many experiments, however, mitigat-ing it will help to increase experimental fidelities (suchas in quantum gates) and will allow for the use ofsmaller ion traps.

8. Conclusion

Microfabricated ion traps provide the opportunity forsignificant advances in quantum information proces-sing, quantum simulation, cavity QED, quantumhybrid systems, precision measurements and manyother areas of modern physics. We have discussed thebasic principles of microfabricated ion traps andhighlighted important factors when designing suchion traps. We have discussed important electrical andmaterial considerations when scaling down trapdimensions. We presented a detailed overview of avast range of ion trap geometries and showed how theycan be fabricated using different fabrication processesemploying advanced microfabrication methods. Alimiting factor to scaling down trap dimensions evenfurther is motional heating in ion traps and we have

summarised current knowledge of its nature and how itcan be mitigated. The investigation of microfabricatedion traps lies on the interface of atomic physics andstate-of-the-art nanoscience. This is a very youngresearch field with room for many step-changinginnovations. In addition to the development of trapstructures themselves, future research will focus onadvanced on-chip features such as cavities, electro-nics, digital signal processing, fibres, waveguides andother integrated functionalities. Eventually progressin this field will result in on-chip architectures fornext generation quantum technologies allowing forthe implementation of large scale quantum simula-tions and quantum algorithms. The inherent scal-ability of such condensed matter systems coupledwith the provision of atomic qubits which are highlydecoupled from the environment will allow forground-breaking innovations in many areas ofmodern physics.

Acknowledgements

We acknowledge the support by the UK Engineering andPhysical Sciences Research Council (EP/E011136/1, EP/G007276/1), the European Commission’s Sixth FrameworkMarie Curie International Reintegration Programme(MIRG-CT-2007-046432), the Nuffield Foundation and theUniversity of Sussex.

Figure 20. Previously published measurements of motional heating plotted as the product of electric field noise spectral densitySE (o) and the secular frequency o, versus ion–electrode distance d. A 1/d4 trend line is also shown. Each label shows both the ionspecies and the electrode material used and the electrode temperature is also noted if the measurement is performed below roomtemperature. The data point are associated with the following references (Hgþ7Mo [108], Baþ7Be–Cu [109], Caþ7Mo [110],Caþ7Au [48, 104, 111], Ybþ7Mo [112], Ybþ7Au [52], Beþ7 Mo [102], Beþ7Be [102], Beþ7Au [102, 103], Mgþ7Al [113],Mgþ7Au [27, 49, 50, 113, 114], Srþ7Ta [115], Cdþ7GaAs [26], Cdþ7W [101], Cdþ7W 150 K [101], Srþ7Al 6 K [91],Srþ7Ag 6 K [92], Srþ7Nbg 6 K, Srþ7Nb 6 K, Srþ7NbN 6 K [91]).

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Notes on contributors

Marcus Hughes gained his MPhys Physicsat the University of Sussex in 2008 and hascarried on studying for his D.Phil. withinthe Sussex Ion Quantum Technologygroup. His interests include quantuminformation and microfabricated ion traps.

Bjoern Lekitsch is a D.Phil. student at theUniversity of Sussex in the Ion QuantumTechnology group. He completed his Dipl.Ing. degree in Nanostrukturtechnik at thePhysics Department at the University ofWuerzburg, Germany in 2010. His interestsinclude quantum information technology,microfabrication of ion traps and shuttling

of ions trough optimised junctions in large ion traps arrays.

Jiddu Broersma, a University of Sussexgraduate student obtained his MPhys The-oretical Physics in 2010. He completed hisfinal year research project in the Sussex IonQuantum Technology group. His interestsinclude quantum information science, neur-al networks and renewable energies.

Winfried Hensinger is a Reader in Quan-tum, Atomic and Optical Physics andheads the Ion Quantum Technology groupat the University of Sussex. In 2008 he wasawarded an EPSRC Leadership fellowshipfor the development of quantum technol-ogy with nanofabricated ion trap chips. Heobtained his undergraduate degree at the

Ruprechts-Karls University in Heidelberg, Germany and hisPh.D. at the University of Queensland in Brisbane, Australiastudying experimental quantum nonlinear dynamics withultracold atoms. During his Ph.D. candidature he spent anextended period at the National Institute of Standards andTechnology in Gaithersburg, USA where he demonstrateddynamical tunnelling in a Bose–Einstein condensate. Aftercompleting his Ph.D. he spent 3 years as a FOCUS ResearchFellow at the University of Michigan, USA, working onscalable quantum information processing with trapped ions.He developed the first monolithic ion trap chip anddemonstrated the first experimental realisation of a two-dimensional ion trap array where individual ions can beshuttled around corners. His primary research direction is thedevelopment of quantum technologies beyond proof-of-principle.

References

[1] W. Paul, Electromagnetic traps for charged and neutralparticles, Rev. Mod. Phys. 62 (1990), pp. 531–540.

[2] H.G. Dehmelt, Radiofrequency spectroscopy of storedions I: Storage, Adv. At. Mol. Phys. 3 (1967), p. 53.

[3] M. Keller, B. Lange, K. Hayasaka, W. Lange, and H.Walther, Deterministic cavity quantum electrody-namics with trapped ions, J. Phys. B: At. Mol. Opt.Phys. 36 (2003), pp. 613–622.

[4] P.F. Herskind, A. Dantan, J.P. Marler, M. Albert,and M. Drewsen, Realization of collective strongcoupling with ion Coulomb crystals in an optical cavity,Nature Phys. 5 (2009), pp. 494–498.

[5] M. Pons, V. Ahufinger, C. Wunderlich, A. Sanpera, S.Braungardt, A. Sen(De), U. Sen, and M. Lewenstein,Trapped ion chain as a neural network: error resistantquantum computation, Phys. Rev. Lett. 98 (2007),023003.

[6] A. Friedenauer, H. Schmitz, J.T. Glueckert, D.Porras, and T. Schaetz, Simulating a quantum magnetwith trapped ions, Nature Phys. 4 (2008), pp. 757–761.

[7] M. Johanning, A.F. Varon, and C. Wunderlich,Quantum simulations with cold trapped ions, J. Phys.B 42 (2009), 154009.

[8] R.J. Clark, T. Lin, K.R. Brown, and I.L. Chuang, Atwo-dimensional lattice ion trap for quantum simula-tion, J. Appl. Phys. 105 (2009), 013114.

[9] K. Kim, M.S. Chang, S. Korenblit, R. Islam, E.E.Edwards, J.K. Freericks, G.D. Lin, L.M. Duan, and C.Monroe, Quantum simulation of frustrated Ising spinswith trapped ions, Nature 465 (2010), pp. 590–593.

[10] T. Udem, S.A. Diddams, K.R. Vogel, C.W. Oates,E.A. Curtis, W.D. Lee, W.M. Itano, R.E. Drullinger,J.C. Bergquist, and L. Hollberg, Absolute frequencymeasurements of the Hgþ and Ca optical clocktransitions with a femtosecond laser, Phys. Rev. Lett.86 (2001), pp. 4996–4999.

[11] S.A. Webster, P. Taylor, M. Roberts, G.P. Barwood,and P. Gill, Kilohertz-resolution spectroscopy of the2S1/27

2F7/2 electric octupole transition in a single171Ybþ ion, Phys. Rev. A 65 (2002), 052501.

[12] C. Tamm, S. Weyers, B. Lipphardt, and E. Peik,Stray-field-induced quadrupole shift and absolute fre-quency of the 688-THz 171Ybþ single-ion opticalfrequency standard, Phys. Rev. A 80 (2009), 043403.

[13] M. Chwalla, J. Benhelm, K. Kim, G. Kirchmair, T.Monz, M. Riebe, P. Schindler, A.S. Villar, W. Hansel,C.F. Roos, R. Blatt, M. Abgrall, G. Santarelli, G.D.Rovera, and P. Laurent, Absolute frequency measure-ment of the 40Caþ 4s2S1/2 7 3d2D5/2 clock transition,Phys. Rev. Lett. 102 (2009), 023002.

[14] J.I. Cirac and P. Zoller, Quantum computations withcold trapped ions, Phys. Rev. Lett. 74 (1995), pp.4091–4094.

[15] D.J. Wineland, C. Monroe, W.M. Itano, D. Leibfried,B.E. King, and D.M. Meekhof, Experimental issues incoherent quantum-state manipulation of trapped atomicions, J. Res. Nat. Inst. Stand. Tech. 103 (1998), pp.259–328.

[16] H. Haffner, C.F. Roos, and R. Blatt, Quantumcomputing with trapped ions, Phys. Rep. 469 (2008),pp. 155–203.

[17] D.P. DiVincenzo, Quantum computation, Science 270(1995), pp. 255–261.

[18] D. Leibfried, D.M. Meekhof, B.E. King, C.Monroe, W.M. Itano, and D.J. Wineland, Experi-mental determination of the motional quantum stateof a trapped atom, Phys. Rev. Lett. 77 (1996), pp.4281–4285.

[19] D. Leibfried, D.M. Meekhof, B.E. King, C. Monroe,W.M. Itano, and D.J. Wineland, Experimentalpreparation and measurement of quantum states ofmotion of a trapped atom, J. Mod. Opt. 44 (1997), p.2485.

526 M.D. Hughes et al.

Dow

nloa

ded

by [

Uni

vers

ity o

f Su

ssex

Lib

rary

] at

06:

23 0

9 D

ecem

ber

2011

[20] D. Leibfried, B. DeMarco, V. Meyer, D. Lucas, M.Barrett, J. Britton, W.M. Itano, B. Jelenkovic, C.Langer, T. Rosenband, and D.J. Wineland, Experimen-tal demonstration of a robust, high-fidelity geometric twoion-qubit phase gate, Nature 422 (2003), pp. 412–415.

[21] A. Sørensen and K. Mølmer, Quantum computationwith ions in thermal motion, Phys. Rev. Lett. 82 (1999),pp. 1971–1974.

[22] J. Benhelm, G. Kirchmair, C.F. Roos, and R. Blatt,Towards fault-tolerant quantum computing withtrapped ions, Nature Phys. 4 (2008), pp. 463–466.

[23] D.M. Lucas, B.C. Keitch, J.P. Home, G. Imreh, M.J.McDonnell, D.N. Stacey, D.J. Szwer, and A.M.Steane, A long-lived memory qubit on a low-decoher-ence quantum bus, preprint (2007). Available atarXiv:0710.4421v1.

[24] A.H. Myerson, D.J. Szwer, S.C. Webster, D.T.C.Allcock, M.J. Curtis, G. Imreh, J.A. Sherman, D.N.Stacey, A.M. Steane, and D.M. Lucas, High-fidelityreadout of trapped-ion qubits, Phys. Rev. Lett. 100(2008), 200502.

[25] M. Acton, K.A. Brickman, P. Haljan, P. Lee, L.Deslauriers, and C. Monroe, Near-perfect simulta-neous measurement of a qubit register, Quantum Inf.Comp. 6 (2006), pp. 465–482.

[26] D. Stick, W.K. Hensinger, S. Olmschenk, M.J.Madsen, K. Schwab, and C. Monroe, Ion trap in asemiconductor chip, Nature Phys. 2 (2006), pp. 36–39.

[27] S. Seidelin, J. Chiaverini, R. Reichle, J.J. Bollinger, D.Leibfried, J. Britton, J.H. Wesenberg, R.B. Blakestad,R.J. Epstein, D.B. Hume, W.M. Itano, J.D. Jost, C.Langer, R. Ozeri, N. Shiga, and D.J. Wineland,Microfabricated surface-electrode ion trap for scalablequantum information processing, Phys. Rev. Lett. 96(2006), 253003.

[28] W.K. Hensinger, S. Olmschenk, D. Stick, D.H.Hucul, M. Yeo, M. Acton, L. Deslauriers, and C.Monroe, T-junction ion trap array for two-dimensionalion shuttling, storage, and manipulation, Appl. Phys.Lett. 88 (2006), 034101.

[29] R.B. Blakestad, C. Ospelkaus, A.P. VanDevender,J.M. Amini, J. Britton, D. Leibfried, and D.J.Wineland, High-fidelity transport of trapped-ion qubitsthrough an X-junction trap array, Phys. Rev. Lett. 102(2009), 153002.

[30] J.I. Cirac and P. Zoller, A scalable quantum computerwith ions in an array of microtraps, Nature 404 (2000),pp. 579–581.

[31] D. Kielpinski, C. Monroe, and D. Wineland, Archi-tecture for a large-scale ion-trap quantum computer,Nature 417 (2002), pp. 709–711.

[32] A. Steane, The ion trap quantum information proces-sor, Appl. Phys. B 64 (1997), pp. 623–642.

[33] R.C. Thompson, S. Donnellan, D.R. Crick, and D.M.Segal, Applications of laser cooled ions in a Penningtrap, J. Phys. B: At. Mol. Opt. Phys. 42 (2009),154003.

[34] J.R. Castrejon-Pita, H. Ohadi, D.R. Crick, D.F.A.Winters, D.M. Segal, and R.C. Thompson, Noveldesigns for Penning ion traps, J. Mod. Opt. 54 (2007),pp. 1581–1594.

[35] W. Paul, Electromagnetic traps for charged andneutral particles, Rev. Mod. Phys. 62 (1990), pp.531–540.

[36] P.K. Ghosh, Ion Traps, Oxford University Press, NewYork, 1995.

[37] G.Z.K. Horvath, R.C. Thompson, and P.L. Knight,Fundamental physics with trapped ions, Contemp.Phys. 38 (1997), pp. 25–48.

[38] R.C. Thompson, Spectroscopy of trapped ions, Adv.At. Mol. Phys. 31 (1993), pp. 63–136.

[39] D.J. Griffiths, Introduction to Electrodynamics, 3rded., Benjamin Cummings, San Francisco, 1999.

[40] F.M. Penning, Die Glimmentladung bei niedrigemDruck zwischen koaxialen Zylindern in einem axialenMagnetfeld, Physica 3 (1936), pp. 873–894.

[41] M. Abramowitz and I.A. Stegun, Handbook ofMathematical Functions, Dover Publications, NewYork, 1965.

[42] M.J. Madsen, W.K. Hensinger, D. Stick, J.A. Rab-chuk, and C. Monroe, Planar ion trap geometry formicrofabrictaion, Appl. Phys. B (2004), pp. 639–651.

[43] D.J. Berkeland, J.D. Miller, J.C. Bergquist, W.M.Itano, and D.J. Wineland, Minimization of ionmicromotion in a Paul trap, J. Appl. Phys. 83 (1998),pp. 5025–5033.

[44] A. Steane, C.F. Roos, D. Stevens, A. Mundt, D.Leibfried, F. Schmidt-Kaler, and R. Blatt, Speed ofion-trap quantum-information processors, Phys. Rev. A62 (2000), 042305.

[45] D. Hucul, M. Yeo, W.K. Hensinger, J. Rabchuk, S.Olmschenk, and C. Monroe, On the transport ofatomic ions in linear and multidimensional ion traparrays, Quantum Inf. Comput. 8 (2008), pp. 501–578.

[46] C. Monroe, D.M. Meekhof, B.E. King, S.R. Jefferts,W.M. Itano, D.J. Wineland, and P. Gould, Resolved-sideband Raman cooling of a bound atom to the 3D zero-point energy, Phys. Rev. Lett. 75 (1995), pp. 4011–4014.

[47] B.E. King, C.S. Wood, C.J. Myatt, Q.A. Turchette,D. Leibfried, W.M. Itano, C. Monroe, and D.J.Wineland, Cooling the collective motion of trapped ionsto initialize a quantum register, Phys. Rev. Lett. 81(1998), pp. 1525–1528.

[48] D.T.C. Allcock, J.A. Sherman, D.N. Stacey, A.H.Burrell, M.J. Curtis, G. Imreh, N.M. Linke, D.J.Szwer, S.C. Webster, A.M. Steane, and D.M. Lucas,Implementation of a symmetric surface-electrode iontrap with field compensation using a modulated Ramaneffect, New J. Phys. 12 (2010), 053026.

[49] J. Britton, D. Leibfried, J.A. Beall, R.B. Blakestad,J.H. Wesenberg, and D.J. Wineland, Scalable arraysof rf Paul traps in degenerate Si, Appl. Phys. Lett. 95(2009), 173102.

[50] J.M. Amini, H. Uys, J.H. Wesenberg, S. Seidelin, J.Britton, J.J. Bollinger, D. Leibfried, C. Ospelkaus,A.P. VanDevender, and D.J. Wineland, Towardscalable ion traps for quantum information processing,New J. Phys. 12 (2010), 033031.

[51] A.H. Nizamani and W.K. Hensinger, Optimum elec-trode configurations for fast ion separation in micro-fabricated surface ion traps, preprint (2010), to appearin Appl. Phys. B. Available at arXiv:1007.3542v2.

[52] J.J. McLoughlin, A.H. Nizamani, J.D. Siverns, R.C.Sterling, M.D. Hughes, B. Lekitsch, B. Stein, S.Weidt, and W.K. Hensinger, Versatile ytterbium iontrap experiment for operation of scalable ion-trap chipswith motional heating and transition-frequency mea-surements, Phys. Rev. A 83 (2011), 013406.

[53] J.D. Siverns, L.R. Simkins, S. Weidt, and W.K.Hensinger, On the application of radio frequency volta-ges to ion traps via helical resonators, preprint (2011).Available at arXiv:1106.5013v1.

Contemporary Physics 527

Dow

nloa

ded

by [

Uni

vers

ity o

f Su

ssex

Lib

rary

] at

06:

23 0

9 D

ecem

ber

2011

[54] L. Deslauriers, M. Acton, B.B. Blinov, K.A. Brick-man, P.C. Haljan, W.K. Hensinger, D. Hucul, S.Katnik, R.N. Kohn, P.J. Lee, M.J. Madsen, P.Maunz, S. Olmschenk, D.L. Moehring, D. Stick, J.Sterk, M. Yeo, K.C. Younge, and C. Monroe,Efficient photoionization loading of trapped ions withultrafast pulses, Phys. Rev. A 74 (2006), 063421.

[55] J. Britton, D. Leibfried, J.A. Beall, R.B. Blakestad, J.J.Bollinger, J. Chiaverini, R.J. Epstein, J.D. Jost, D.Kielpinski, C. Langer, R. Ozeri, R. Reichle, S. Seidelin,N. Shiga, J.H. Wesenberg, and D.J. Wineland, A micro-fabricated surface-electrode ion trap in silicon, preprint(2008). Available at arXiv:quant-ph/0605170v1.

[56] J.H. Wesenberg, Ideal intersections for radio-frequencytrap networks, Phys. Rev. A 79 (2009), 013416.

[57] F. Splatt, M. Harlander, M. Brownnutt, F.Zaehringer, R. Blatt, and W. Haensel, Deterministicreordering of 40Caþ ions in a linear segmented Paultrap, New J. Phys. 11 (2009), 103008.

[58] R. Reichle, D. Leibfried, R.B. Blakestad, J. Britton,J.D. Jost, E. Knill, C. Langer, R. Ozeri, S. Seidelin,and D.J. Wineland, Transport dynamics of single ionsin segmented microstructured Paul trap arrays,Fortschr. Phys. 54 (2006), pp. 666–685.

[59] K. Singer, U. Poschinger, M. Murphy, P. Ivanov, F.Ziesel, T. Calarco, and F. Schmidt-Kaler, Colloquium:Trapped ions as quantum bits: Essential numericaltools, Rev. Mod. Phys. 82 (2010), pp. 2609–2632.

[60] M.H. Oliveira and J.A. Miranda, Biot-Savart-like lawin electrostatics, Eur. J. Phys. 22 (2001), pp. 31–38.

[61] J.H. Wesenberg, Electrostatics of surface-electrode iontraps, Phys. Rev. A 78 (2008), 063410.

[62] M.G. House, Analytic model for electrostatic fields insurface-electrode ion traps, Phys. Rev. A 78 (2008),033402.

[63] R. Schmied, Electrostatics of gapped and finite surfaceelectrodes, New J. Phys. 12 (2010), 023038.

[64] V.K. Agarwal and V.K. Srivastava, Thickness depen-dence of breakdown field in thin films, Thin Solid Films8 (1971), pp. 377–381.

[65] V.K. Agarwal and V.K. Srivastava, Thickness depen-dent studies of dielectric breakdown in Langmuir thinmolecular films, Solid State Commun. 12 (1973), pp.829–834.

[66] D. Mangalaraj, M. Radhakrishnan, and C. Balasu-bramanian, Electrical conduction and breakdownproperties of silicon nitride films, J. Mater. Sci. 17(1982), pp. 1474–1478.

[67] H.K. Kim and F.G. Shi, Thickness dependent di-electric strength of a low-permittivity dielectric film,IEEE Trans. Dielectrics Electric. Insulat. 8 (2001), pp.248–252.

[68] H. Zhou, F. Shi, and B. Zhao, Thickness dependentdielectric breakdown of PECVD low-k carbon dopedsilicon dioxide dielectric thin films: modeling andexperiments, Microelectron. J. 34 (2003), pp. 259–264.

[69] H. Bartzsch, D. Gloß, B. Bocher, P. Frach, and K.Goedicke, Properties of SiO2 and Al2O3 films forelectrical insulation applications deposited by reactivepulse magnetron sputtering, Surf. Coat. Technol. 174–175 (2003), pp. 774–778.

[70] J. Mueller, D. Pyle, I. Chakraborty, R. Ruiz, W.Tang, and R. Lawton, Feasibility study of MEMS-based accelerator grid systems for micro-ion engines:Electric breakdown characteristics, AIAA J. Propul.Power U.S.A. (1999).

[71] H.C. Miller, Flashover of insulators in vacuum: reviewof the phenomena and techniques to improved holdoffvoltage, IEEE Trans. Electric. Insulat. 28 (1993), pp.512–527.

[72] A.S. Pillai and R. Hackam, Surface flashover of solidinsulators in atmospheric air and in vacuum, J. Appl.Phys. 58 (195), pp. 146–153.

[73] A.S. Pillai and R. Hackam, Surface flashover of soliddielectric in vacuum, J. Appl. Phys. 53 (1982), pp.2983–2987.

[74] J.D. Kraus and D.A. Fleisch, Electromagnetics withApplications, 5th ed., McGraw-Hill Science/Engineer-ing/Math, New York, 1999.

[75] D. _Ilbilge, C. Altindal, and M. Gokcen, Frequencyand gate voltage effects on the dielectric properties ofAu/SiO2/n-Si structures, Microelectron. Eng. 85(2008), pp. 1910–1914.

[76] S.C. Thierauf, High-speed circuit board signal integrityArtech House Publishers, Norwood, MA, 2004.

[77] H. Johnson and M. Graham, High Speed SignalPropagation: Advanced Black Magic Prentice Hall,Upper Saddle River, NJ, 2003.

[78] P. Horowitz and W. Hill, The Art of ElectronicsCambridge University Press, Cambridge, 1989.

[79] J. Krupka, J. Breeze, A. Centeno, N. Alford, T.Claussen, and L. Jensen, Measurements of permittiv-ity, dielectric loss tangent, and resistivity of float-zonesilicon at microwave frequencies, IEEE Trans. Micro-wave Theory Tech. 54 (2006), pp. 3995–4001.

[80] A. Tataro�glu, Electrical and dielectric properties ofMIS Schottky diodes at low temperatures, Microelec-tron. Eng. 83 (2006), pp. 2551–2557.

[81] M.M. Bulbul, Frequency and temperature dependentdielectric properties of Al/Si3N4/p-Si(100) MISstructure, Microelectron. Eng. 84 (2007), pp. 124–128.

[82] S. Karatas, Studies on electrical and the dielectricproperties in MS structures, J. Non-Crystalline Solid.354 (2008), pp. 3606–3611.

[83] A.B. Selcuk, On the dielectric characteristics of Au/SnO2/n 7 Si capacitors, Physica B 396 (2007), pp.181–186.

[84] N. Tomozeiu, Electrical conduction and dielectricrelaxation of a 7 SiOx (0 5 x 5 2) thin filmsdeposited by reactive RF magnetron sputtering, ThinSolid Films 516 (2008), pp. 8199–8204.

[85] K.R. Brown, R.J. Clark, J. Labaziewicz, P. Richerme,D.R. Leibrandt, and I.L. Chuang, Loading andcharacterization of a printed-circuit-board atomic iontrap, Phys. Rev. A 75 (2007), 015401.

[86] C.E. Pearson, D.R. Leibrandt, W.S. Bakr, W.J.Mallard, K.R. Brown, and I.L. Chuang, Experimentalinvestigation of planar ion traps, Phys. Rev. A 73(2006), 032307.

[87] J.S. Chenard, C.Y. Chu, Z. Zilic, and M. Popovic,Design methodology for wireless nodes with printedantennas, Proceedings of the 42nd Design AutomationConference, IEEE, Piscataway, NJ, 2005, pp. 291–296.

[88] M. Harlander, M. Brownnutt, W. Hansel, and R.Blatt, Trapped-ion probing of light-induced chargingeffects on dielectrics, New J. Phys. 12 (2010),093035.

[89] D.R. Leibrandt, R.J. Clark, J. Labaziewicz, P.Antohi, W. Bakr, K.R. Brown, and I.L. Chuang,Laser ablation loading of a surface-electrode ion trap,Phys. Rev. A. 76 (2007), 055403.

528 M.D. Hughes et al.

Dow

nloa

ded

by [

Uni

vers

ity o

f Su

ssex

Lib

rary

] at

06:

23 0

9 D

ecem

ber

2011

[90] S.X. Wang, J. Labaziewicz, Y. Ge, R. Shewmon, andI.L. Chuang, Individual addressing of ions usingmagnetic field gradients in a surface-electrode iontrap, Appl. Phys. Lett. 94 (2009), 094103.

[91] S.X. Wang, Y. Ge, J. Labaziewicz, E. Dauler, K.Berggren, and I.L. Chuang, Superconducting micro-fabricated ion traps, Appl. Phys. Lett. 97 (2010),244102.

[92] J. Labaziewicz, Y. Ge, P. Antohi, D. Leibrandt, K.R.Brown, and I.L. Chuang, Suppression of heating ratesin cryogenic surface-electrode ion traps, Phys. Rev.Lett. 100 (2008), 013001.

[93] D. Stick, Fabrication and characterization ofsemiconductor ion traps for quantum informationprocessing, Ph.D. thesis, University of Michigan,2007.

[94] J. Labaziewicz, Y. Ge, D.R. Leibrandt, S.X. Wang,R. Shewmon, and I.L. Chuang, Temperature depen-dence of electric field noise above gold surfaces, Phys.Rev. Lett. 101 (2008), 180602.

[95] N. Daniilidis, T. Lee, R. Clark, S. Narayanan, and H.Haffner, Wiring up trapped ions to study aspects ofquantum information, J. Phys. B 42 (2009), p. 154012.

[96] R.C. Sterling, H. Rattanasonti, S. Weidt, P. Sriniva-san, K. Lake, A.H. Nizamani, M. Kraft, and W.K.Hensinger, Two-dimensional ion trap arrays usingsilicon-on-insulator technology, in preparation (2011).

[97] D. Stick, K.M. Fortier, R. Haltli, C. Highstrete,D.L. Moehring, C. Tigges, and M.G. Blain, Demon-stration of a microfabricated surface electrode iontrap, preprint (2010). Available at arXiv:1008.0990v2.

[98] D. Leibrandt, J. Labaziewicz, R. Clark, I. Chuang, R.Epstein, C. Ospelkaus, J. Wesenberg, J. Bollinger, D.Leibfried, D. Wineland, D. Stick, J. Stick, C. Monroe,C.S. Pai, Y. Low, R. Frahm, and R. Slusher,Demonstration of a scalable, multiplexed ion trap forquantum information processing, Quantum Inf. Com-put. 9 (2009), pp. 0901–0919.

[99] W.K. Hensinger, D. Stick, J. Sterk, M. Madsen, W.Noonan, M. Pedersen, S. Gross, M. Huff, and C.Monroe, MEMS fabrication of silicon ion trap arrays,Workshop on Trapped Ion Quantum Computing(Boulder, CO), 2006. Available at http://tf.nist.gov/ion/workshop2006/t11.pdf.

[100] M. Brownnutt, G. Wilpers, P. Gill, R.C. Thompson,and A.G. Sinclair, Monolithic microfabricated ion trapchip design for scaleable quantum processors, New. J.Phys. 8 (2006), p. 232.

[101] L. Deslauriers, S. Olmschenk, D. Stick, W.K. Hen-singer, J. Sterk, and C. Monroe, Scaling and suppres-sion of anomalous heating in ion traps, Phys. Rev. Lett.97 (2006), 103007.

[102] Q.A. Turchette, Kielpinski, B.E. King, D. Leibfried,D.M. Meekhof, C.J. Myatt, M.A. Rowe, C.A. Sackett,C.S. Wood, W.M. Itano, C. Monroe, and D.J. Wine-land, Heating of trapped ions from the quantum groundstate, Phys. Rev. A 61 (2000), 063418.

[103] M.A. Rowe, A. Ben-Kish, B. DeMarco, D. Leibfried,V. Meyer, J. Beall, J. Britton, J. Hughes, W.M. Itano,B. Jelenkovic, C. Langer, T. Rosenband, and D.J.Wineland, Transport of quantum states and separationof ions in a dual rf ion trap, Quant. Inf. Comp. 2 (2002),pp. 257–271.

[104] S.A. Schulz, U. Poschinger, F. Ziesel, and F. Schmidt-Kaler, Sideband cooling and coherent dynamics in amicrochip multi-segmented ion trap, New J. Phys. 10(2008), p. 15.

[105] K. Mølmer and A. Sørensen, Multiparticle entangle-ment of hot trapped ions, Phys. Rev. Lett. 82 (1999), pp.1835–1838.

[106] P.J. Lee, K.A. Brickman, L. Deslauriers, P.C. Haljan,L.M. Duan, and C. Monroe, Phase control of trappedion quantum gates, J. Opt. B 7 (2005), pp. S371–S383.

[107] J.J. Garcıa-Ripoll, P. Zoller, and J.I. Cirac, SpeedOptimized Two-qubit gates with laser coherent controltechniques for ion trap quantum computing, Phys. Rev.Lett. 91 (2003), 157901.

[108] F. Diedrich, J.C. Bergquist, W.M. Itano, and D.J.Wineland, Laser cooling to the zero-point energy ofmotion, Phys. Rev. Lett. 62 (1989), pp. 403–406.

[109] R.G. DeVoe and C. Kurtsiefer, Experimental study ofanomalous heating and trap instabilities in a microscopic137Ba ion trap, Phys. Rev. A 65 (2002), 063407.

[110] C. Roos, T. Zeiger, H. Rohde, H.C. Nagerl, J. Eschner,D. Leibfried, F. Schmidt-Kaler, and R. Blatt, Quantumstate engineering on an optical transition and decoher-ence in a paul trap, Phys. Rev. Lett. 83 (1999), pp.4713–4716.

[111] N. Daniilidis, S. Narayanan, S.A. Moller, R. Clark,T.E. Lee, P.J. Leek, A. Wallraff, S. Schulz, F. Schmidt-Kaler, and H. Haffner, Fabrication and heating ratestudy of microscopic surface electrode ion traps, New J.Phys. 13 (2011), p. 17.

[112] C. Tamm, D. Engelke, and V. Buhner, Spectroscopy ofthe electric-quadrupole transition 2S1/2 (F ¼ 0) 72D3/2

(F ¼ 2) in trapped 171Ybþ, Phys. Rev. A 61 (2000),053405.

[113] J. Britton, Microfabrication techniques for trapped ionquantum information processing, Ph.D. thesis, Univer-isty of Colorado, Boulder, 2008, arXiv:1008.2222v1.

[114] R.J. Epstein, S. Seidelin, D. Leibfried, J.H. Wesenberg,J.J. Bollinger, J.M. Amini, R.B. Blakestad, J. Britton,J.P. Home, W.M. Itano, J.D. Jost, E. Knill, C. Langer,R. Ozeri, N. Shiga, and D.J. Wineland, Simplifiedmotional heating rate measurements of trapped ions,Phys. Rev. A 76 (2007), 033411.

[115] V. Letchumanan, G. Wilpers, M. Brownnutt, P. Gill,and A.G. Sinclair, Zero-point cooling and heating-ratemeasurements of a single 88Srþ ion, Phys. Rev. A 75(2007), 063425.

Contemporary Physics 529

Dow

nloa

ded

by [

Uni

vers

ity o

f Su

ssex

Lib

rary

] at

06:

23 0

9 D

ecem

ber

2011