microcontrollers

1/175

MicrocontrollersMicrocontrollers

Specially designed microprocessors– It is small on chip computer

Highly integrated chipincludes all or most parts needed for controller

A typical microcontroller has:– bit manipulation– easy and direct access to I/O– quick and efficient interrupt processing

Microcontroller drastically reduces design cost

2/175

Worldwide Microcontroller shipmentsWorldwide Microcontroller shipments- in millions of dollars -- in millions of dollars -

'95 '96 '97 '98 '99 00

4-bit 1826 1849 1881 1856 1816 1757

8-bit 5634 6553 7529 8423 9219 9715

16-bit 1170 1628 2191 2969 3678 4405

3/175

Worldwide Microcontroller shipmentsWorldwide Microcontroller shipments- in millions -- in millions -

'95 '96 '97 '98 '99 00

4-bit 1100 1100 1096 1064 1025 970

8-bit 1803 2123 2374 2556 2681 2700

16-bit 157 227 313 419 501 585

4/175

ApplicationsApplications

Appliances(microwave oven, refrigerators, television and VCRs, stereos)

Computers and computer equipment(laser printers, modems, disk drives)

Automobiles(engine control, diagnostics, climate control),

Environmental control(greenhouse, factory, home)

Instrumentation

Aerospace

Robotics, etc...

5/175

FlavorsFlavors

4, 8, 16, or 32 bit microcontrollers

specialized processors include features specific for

– communications,

– keyboard handling,

– signal processing,

– video processing, and other tasks.

6/175

Popular MicrocontrollersPopular Microcontrollers

8048 (Intel)

8051 (Intel and others)

80c196 (MCS-96)

80186,80188 (Intel)

80386 EX (Intel)

65C02/W65C816S/W65C134S (Western Design Center)

MC14500 (Motorola)

Part 1Part 1

7/175


68HC05 (Motorola)

68HC11 (Motorola and Toshiba)

683xx (Motorola)

PIC (MicroChip)

COP400 Family (National Semiconductor)

COP800 Family (National Semiconductor)

HPC Family (National Semiconductor)

Project Piranha (National Semiconductor)

Part 2Part 2

8/175


Z8 (Zilog)

HD64180 (Hitachi)

TMS370 (Texas Instruments)

1802 (RCA)

MuP21 (Forth chip)

F21 (Next generation Forth chip)

Part 3Part 3

9/175

Programming LanguagesProgramming Languages

Machine/Assembly language

Interpreters

Compilers

Fuzzy Logic and Neural Networks

Part 1Part 1

10/175

Development ToolsDevelopment Tools

Simulators

Resident Debuggers

Emulators

Java on Embedded Systems

Part 1Part 1

11/175

Choosing microcontollerChoosing microcontoller

Technical support Development tools Documentation Purchasing more devices at one manufacturer

(A/D, memory, etc.)

Additional features(EEPROM, FLASH, LCD driver, etc.)

12/175

MicrocontrollersMicrocontrollers

Basic parts are:– Central Processing Unit– RAM– EPROM/PROM/ROM or

FLASH Memory– I/O serial or/and parallel– timers– interrupt controller

Optional parts are:– Watch Dog Timer– AD Converter– LCD driver– etc.

interruptcontrol

externalinerrupts

CPU

OSC

ROM

buscontrol

4 I/Oports

serialport

RAMtim er 0

tim er 1 counterinputs

P0 P2 P1 P3

address/data

T xD RxD

13/175

Intel 8051Intel 8051

A typical 8051 contains:

– CPU with Boolean processor

– 5 or 6 interrupts:2 external, 2 priority levels

– 2 or 3 16-bit timer/counters

– programmable full-duplex serial port

– 32 I/O lines (four 8-bit ports)

– RAM

– ROM/EPROM in some models

PCH

PCL DPL

DPH P2 LATCH

PORT2

TM P2 TM P1

AALUROM

RAMBUFFER

128x8RAM

RAR

SENSEAM PS

4Kx8ROM

ALU

B

IR

PLA

CONTROLPSW SP

SCONP0 LATCH TCON IE P3 LATCH

PORT0 SBUF(REC)

SBUF(XM IT)

SERIALPORT

TM OD

TL0

TH0

TL1

TH1

IP

INTERRUPTCONTROL

PORT3

TIM ERCONTROL

P2 LATCH

PORT2

P0 LATCH

INT

ER

NA

L B

US

14/175

Intel 8051: Pin DescriptionIntel 8051: Pin Description

VSS - Ground: 0V VCC - Power Supply P0.0-P0.7 - Port 0

– Open drain,bi-directional I/O port

– Pins that have 1s written to them float and can be used as high-impedance inputs

– Multiplexed low-order address and data bus during accesses to external program and data memory

Part 1Part 1

PO

RT

0P

OR

T 1

PO

RT

2

ADDRESS ANDDAT A BUS

ADDRESS BUS

PO

RT

3

RxD

T xD

INT 0

INT 1

T 0

T 1

W R

RD

XT AL1

XT AL2

VCC VSS

SE

CO

ND

AR

Y F

UN

CT

ION

S

RST

PSEN

ALE/PRO G

EA/Vpp

15/175


P2.0-P2.7 - Port 2– Bi-directional I/O port

with internal pull-ups– Pins that have 1s written to

them float and can be used as high-impedance inputs.

– Port 2 emits high-order address byte during accesses to external program and data memory

P3.0-P3.7 - Port 3– Bi-directional I/O port

with internal pull-ups– Pins that have 1s written to

them float and can be used as high-impedance inputs.

Part 2Part 2

Port 3 serves thespecial features:

– RxD - Serial input port– TxD - Serial output port– INT0 - External interrupt– INT1 - External interrupt– T0 - Timer 0 external input– T1 - Timer 1 external input– WR - External data memory

write strobe– RD - External data memory

read strobe

16/175


RST - Reset– A high on this pin

for two machine cycles resets the devices

ALE - Address Latch Enable– Output pulse for latching

the low byte of address during an access to external memory

PSEN - Program Store Enable– Read strobe to external

program memory

Part 3Part 3

EA - External Access Enable – EA must be externally held

low to enable device to fetch code from external memory locations.

XTAL1 - Crystal 1– Input to the inverting

oscillator amplifier and input to internal clock generator circuits

XTAL2 - Crystal 2– Output from the inverting

oscillator amplifier

17/175

Part 1Part 1

Intel 8051: Pin ConfigurationsIntel 8051: Pin Configurations

Dual In-Line Package Plastic Lead Chip Carrier Plastic Quad Flat Pack

2

1

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

39

40

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

RST

RxD/P3.0T xD/P3.1

INT 0/P3.2

INT 1/P3.3

T 0/P3.4

T 1/P3.5

W R/P3.6

RD/P3.7

XT AL2

XT AL1

Vss

Vcc

P0.0/AD0

P0.1/AD1

P0.2/AD2

P0.3/AD3

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.6/AD6

EA

ALE

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P2.0/A8

18/175

Intel 8051: Pin ConfigurationsIntel 8051: Pin Configurations

Part 2Part 2

PQFP

–6 –1 –40

–39

–29

–28–18

–17

–7

–1 NIC–2 P1.0–3 P1.1–4 P1.2–5 P1.3–6 P1.4–7 P1.5–8 P1.6–9 P1.7–10 RST–11 P3.0/RxD–12 NIC–13 P3.1/TxD–14 P3.2/INT0–15 P3.3/INT1

–16 P3.4/T0–17 P3.5/T1–18 P3.6/WR–19 P3.4/RD–20 XTAL2–21 XTAL1–22 VSS–23 NIC–24 P2.0/A8–25 P2.1/A9–26 P2.2/A10–27 P2.3/A11–28 P2.4/A12–29 P2.5/A13–30 P2.6/A14

–31 P2.7/A15–32 PSEN–33 ALE–34 NIC–35 EA–36 P0.7/AD7–37 P0.6/AD6–38 P0.5/AD5–39 P0.4/AD4–40 P0.3/AD3–41 P0.2/AD2–42 P0.1/AD1–43 P0.0/AD0–44 VCC

PLCC

44 34

33

23

2212

11

1

1 P1.52 P1.63 P1.74 RST5 P3.0/RxD6 NIC7 P3.1/TxD8 P3.2/INT09 P3.3/INT110 P3.4/T011 P3.5/T112 P3.6/WR13 P3.4/RD14 XTAL215 XTAL1

16 VSS17 NIC18 P2.0/A819 P2.1/A920 P2.2/A1021 P2.3/A1122 P2.4/A1223 P2.5/A1324 P2.6/A1425 P2.7/A1526 PSEN27 ALE28 NIC29 EA30 P0.7/AD7

31 P0.6/AD632 P0.5/AD533 P0.4/AD434 P0.3/AD335 P0.2/AD236 P0.1/AD137 P0.0/AD038 VCC39 NIC40 P1.041 P1.142 P1.243 P1.344 P1.4

19/175

Intel 8051: CPUIntel 8051: CPU

Primary elements are:– eight bit ALU

with associated registersA, B, PSW and SP

– sixteen-bitProgram Counter (PC)

– Data Pointer registers

Part 1Part 1

PCH

PCL DPL

DPH P2 LATCH

PORT2

TM P2 TM P1

AALUROM

RAMBUFFER

128x8RAM

RAR

SENSEAM PS

4Kx8ROM

ALU

B

IR

PLA

CONTROLPSW SP

SCONP0 LATCH TCON IE P3 LATCH

PORT0 SBUF(REC)

SBUF(XM IT)

SERIALPORT

TM OD

TL0

TH0

TL1

TH1

IP

INTERRUPTCONTROL

PORT3

TIM ERCONTROL

P2 LATCH

PORT2

P0 LATCH

INT

ER

NA

L B

US

20/175


The ALU can manipulate one-bit as well as eight-bit data types– This features makes the 8051 especially well suited

for controller-type applications A total of 51 separated operations

move and manipulate three data types:– Boolean (1-bit)– Byte (8-bit)– Address (16-bit)

Part 2Part 2

21/175


Instruction types:– Arithmetic Operations– Logic Operations for Byte Variables– Data Transfer Instructions– Boolean Variable Manipulation– Program Branching and Machine Control

Part 3Part 3

22/175


There are eleven addressing modes:– seven for data– four for program sequence control

Most operations allow several addressing modes,bringing total number of instructions to 111,encompassing 255 of the 256 possible 8-bit instruction opcodes

8051 instruction set fares well at bothreal-time control and data intensive algorithms

Part 4Part 4

23/175

Part 1Part 1

Intel 8051: Memory OrganizationIntel 8051: Memory Organization

Program memory is separate distinct from data memory– Each memory type has a different addressing mechanism,

different control signals, and a different functions Architecture supports several distinct “physical” address spaces

functionally separated at the hardware level:– On - chip program memory– On - chip data memory– Off - chip program memory– Off - chip data memory– On chip special function registers

24/175

Part 2Part 2


Program (Code) memory– Holds the actual 8051 program that is to be run

– Limited to 64K – may be found on-chip as ROM or EPROM– may be stored completely off-chip in

an external ROM or an external EPROM– Flash RAM is also another popular method of storing a program– Various combinations of these memory types may be used

(e.g. 4 K on-chip and 64 KB off-chip)

25/175

Part 3Part 3


External RAM– External RAM is any random access memory which is found off-chip– External RAM is slower

• To increment an Internal RAM location by 1 requires only 1 instruction and 1 instruction cycle

• To increment a 1-byte value stored in External RAMrequires 4 instructions and 7 instruction cycles

– While Internal RAM is limited to 128 bytes (256 bytes with an 8052),the 8051 supports External RAM up to 64K

26/175

Part 4Part 4


On-chip memory– Two types:

• Internal RAM; and

• Special Function Register (SFR) memory

– Internal RAM is on-chip so it is the fastest RAM available– Internal RAM is volatile, when the 8051 is reset this memory is cleared

– Special Function Registers (SFRs) are areas of memory thatcontrol specific functionality of the 8051 processor

27/175

Part 1Part 1

Intel 8051: Memory AccessIntel 8051: Memory Access

PORT 2 : High byte of addressheld for the duration ofread or write cycle

PORT 0 : time multiplexedlow byte of address with data byte

Signal ALE: used to capture the address byte into an external latch

8051

LATCH

AD0-AD7

PORT2

PORT0

PSENRD

WR

A8-A15

A0-A7

A8-A15

A0-A7

D0-D7

A0-A7

A8-A15

ALECSOE

CSRDWRLE

"0""0"

Sta

tic

RA

M

RO

M

64 Kbytes - Program m em ory (external)64 Kbytes - Data M em ory

EA

28/175

Part 2Part 2

Intel 8051: Memory AccessIntel 8051: Memory Access

ALE

P0

P2A8-A15

A0-A7

A8-A15

datain

P1 P1 P1 P1 P1 P1 P2P2P2P2P2P2

ST AG E 4 ST AG E 5 ST AG E 6 ST AG E 1 ST AG E 2 ST AG E 3

XT AL1

RD

FLO AT FLO AT

P1 P1 P1 P1 P1 P1 P2P2P2P2P2P2

ST AG E 1 ST AG E 2 ST AG E 3 ST AG E 4 ST AG E 5 ST AG E 6

XT AL1

ALE

PSEN

P2A8-A15A8-A15

P0A0-A7 A0-A7

INS.IN

INS.IN

INS.IN

29/175

Part 1Part 1

Intel 8051: Program MemoryIntel 8051: Program Memory

Up to 64K of Program Memory PSEN: read strobe

for all external program fetches PSEN: not activated for

internal program fetches Depending on EA pin

lowest bytes can be eitherin the on-chip ROM or in an external ROM

EA = 0 EA = 1

PSEN

0x0000

EX

TE

RN

AL

EX

TE

RN

AL

0xFFFF

PROGRAM M EM ORY

30/175

Part 2Part 2


Boot address - 0x0000 Each interrupt is assigned

a fixed location in Program Memory If interrupt is not going to used,

its service location is available asgeneral purpose Program Memory

RESET 0x0000

0x0003

0x0008

0x0013

0x0018

0x0023

0x0028

INT ERRPUTLO CAT IO NS

8 BYT ES

LO W ER PART O F PRO G RAM M EM O RY

31/175

Part 3Part 3


Port 0 and Port 2 are dedicatedto bus functions duringexternal Program Memory fetches

8051

LAT CH

AD0-AD7

PO RT 0

PSEN

ERO M

INST R

A0-A7

ALE

O E

LE

EA

PO RT 2 A8-A15

ADDR

32/175

Part 1Part 1

Intel 8051: Data MemoryIntel 8051: Data Memory

Up to 64K Data Memory Access to Data memory use

RD or WR to strobe the memory

0x0000

EX

TE

RN

AL

0xFFFF

INT ERNAL

0xFF

0x00

EX

TE

RN

AL

0xFFFF

RD WR

DAT A M EM O RY

33/175

Part 2Part 2


Internal Memory Addressesare one byte wide - 128 bytes address space(256 - Intel 8052)

Direct addressing higher then 0x7F access one memory space,indirect addressing higher then 0x7F access a different memory space

Upper 128 and SFR spaceoccupying same block of addresses, although they are physically separate entities

INTERNAL

0xFF

0x00

0x7F

ACCESSIBLEBY INDIRECTADDRESSING

ONLY

ACCESSIBLEBY DIRECT

AND INDIRECTADDRESSING

ACCESSIBLEBY DIRECT

ADDRESSINGONLY

SPECIALFUNCTIONREGISTERS

PORTSSTATUS BITSCONTOL BITSTIMER REGISTERSSTACK POINTERACCUMULATOR(ETC.)

LOWER128

UPPER128

34/175

Part 3Part 3


The lowest 32 bytes are groupedinto 4 banks of 8 registers

Program instructions call outthese registers R0 through R7

Two bits in the PSWselects register bank

– Register instructions are shorter The next 16 bytes form a

block of bit-addressable space

LOWER 128 BYTES OFINTERNAL RAM

0x07

0x00

0x0F

0x08

0x17

0x10

0x1F

0x18

0x2F

0x20

0x7F

00

01

10

11

BANK SELECT BITSIN PSW

4 BANKS OF8 REGISTERSR0-R7

BIT ADDRESSABLE SPACE(BIT ADDRESSES 0-7F)

RESET VALUE OFSTACK POINTER

35/175

Part 1Part 1

Intel 8051: SFRIntel 8051: SFR

SFRs are accessed as if they were normal Internal RAM

SFR registers exist in the address range of 80h through FFh

Each SFR has an address and a name

36/175

Part 2Part 2

Intel 8051: SFRIntel 8051: SFR0 1 2 3 4 5 6 7

F8 FFF0 B F7E8 EFE0 ACC E7D8 DFD0 PSW D7C8 CFC0 C7B8 IP BFB0 P3 B7A8 IE AFA0 P2 A798 SCON SBUF 9F90 T1 9788 TCON TMOD TL0 TL1 TH0 TH1 8F80 T0 SP DPL DPH PCON 87

37/175

Part 3Part 3


Accumulator (A)– Accumulator register

B Register (B)– Used during multiply and

divide operations PSW

– Contains program status information

Stack Pointer (SP)– Eight bits wide– Stack may reside anywhere

in on chip RAM

– The Stack Pointer is initialized on 0x07after a reset, and this causes stack to begin at location 0x08

Data Pointer(DPTR) – Consist high byte (DPH) and

low byte (DPL)– It may be manipulated as a

16-bit register or as two independent 8-bit registers

38/175

Part 4Part 4


Ports 0 to 3 (P0, P1, P2, P4)– Latches of Port 0 to 3,

respectively Serial Data Buffer (SDBF)

– It is actually two separated registers: receive and transmit buffer registers

– When data is moved to SBUF it goes to the transmit buffer

– When data is moved from SBUF it comes from the receive buffer

Timer Registers (T1, T0)– (TH1, TL1) (TH0, TL0)

Counting Registers for Timer/Counter 1 and 0

Control Registers– IP: Interrupt priority – IE: Interrupt enable – TMOD Timer/Counter mode– TCON Timer/Counter control– PCON Power control

39/175

Intel 8051: PSWIntel 8051: PSW

Auxiliary Carry flag is used for BCD operations Flag 0 is available to user for general purposes The contest of (RS1, RS2) enable working register banks as follows:

00 - Bank 0 [0x00-0x07], 01 - Bank 1 [0x08-0x0f],10 - Bank 2 [ 0x10-0x17], 11 - Bank 3 [0x18-0x1F]

CY AC F0 RS1 RS0 OV - P

7 6 5 4 3 2 1 0

PSW

Carry flag

Auxiliary Carry flag

Flag 0

Registar BankSelect bit 1

Registar BankSelect bit 1

Overflow flag

Parity flag

40/175

Intel 8051: CPU TimingIntel 8051: CPU Timing

The internal clock generator defines the sequence of states that make up a machine cycle

A machine cycle consists of 6 states, numbered S1 through S6 Each state time lasts for two oscillator periods Each state is then divided into a Phase 1 and Phase 2 half

S5 S6 S1 S2 S3 S4

ALE

S5 S6 S1 S2 S3 S4 S5

P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

41/175

Part 1Part 1

Intel 8051: Port StructuresIntel 8051: Port Structures

Pseudo bi-directional I/O port structure

– On Port0 R2 is disabledexcept during bus operations(open-collector output)

The address latch bit is updated by direct addressing instructions

The value read is “OR-tied” function of Q1 and the external device

To use a pin for input latch must be set

D

Q

QSET

CLR

ENB

ENB

R1 R2

I/OPIN

+5V +5VREAD/MODIFY/WRITE

READ

INPUTBUFFER

Q2

Q1

BUS CYCLETIMING

WRITE PULSE

INTERNAL BUS

42/175

Intel 8051: Port InterfacingIntel 8051: Port Interfacing

The output buffers of Ports 0, 1, 2 and 3can each drive 4 LS TTL inputs

Can be driven by open-collector and open-drain outputs– 0-to-1 transitions will not be fast since

there is little current pulling the pin up Port 0 output buffers can each drive 8 LS TTL inputs

(external bus mode) As port pins PORT 0 requires external pull-ups

to be able to drive any inputs bit

43/175

Intel 8051: Intel 8051: Special Peripheral FunctionsSpecial Peripheral Functions

There are few special needscommon among control-oriented computer systems:

– keeping tracks of elapsed time– maintaining a count of signal transitions– measuring the precise width of input pulses– communicating with other systems

– closely monitoring asynchronous external events

44/175

Intel 8051: Timers/CountersIntel 8051: Timers/Counters

Two 16-bit Timer/Counter registers Timer: Register is incremented every machine cycle

(1 machine cycle = 12 oscillator periods) Counter: Register is incremented in response to

1-to-0 transition at its corresponding external input pin (T0, T1)– External input is sampled at S5P2 of every machine cycle– When the samples show high in one cycle and low in the next,

the count is incremented– The new count value is appears in S3P1

of the following detection cycle – Max count rate is 1/24 of oscillator frequency

TMOD - Timer/Counter mode register TCON - Timer/Counter control register

Part 1Part 1

45/175


GATE: Gating control when set C/T: Counter or Timer Selector M1 M0:

– 00: 8-bit Timer/Counter with 5-bit prescaler– 01: 16-bit Timer/Counter– 10: 8-bit auto reload Timer/Counter– 11: (Timer0)

TL0 is 8-bit Timer/Counter controlled by Timer0 control bitsTH0 is 8-bit timer only controlled by Timer1 control bits

– 11: (Timer1) Timer/Counter is stopped

Part 2Part 2

T IM E R 0

T IM E R 1

GATE

C/T

M1M0

46/175


TF: Overflow flag– Set by hardware on Timer/Counter overflow – Cleared by hardware when processor vectors to interrupt routine

TR: Run control bit– Set/Cleared by software to turn Timer/Counter on/off

IE: Interrupt Edge flag– Set by hardware when external interrupt edge detected– Cleared when interrupt processed

IT: Interrupt Type control bit– Set/Cleared by software to specify

falling edge/low level triggered external interrupts

Part 3Part 3

7 6 5 4 3 2 1 0TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

47/175


Part 4Part 4

O SC 1/12

T L1(5 b its)

T H1(8 b its)

T F1

INT 1 PIN

G AT E

T R1

T 1 PIN

INT ERRUPT

MODE 0

48/175


Part 5Part 5

O SC 1/12

T L1(8 b its)

T H1(8 b its)

T F1

INT 1 PIN

G AT E

T R1

T 1 PIN

INT ERRUPT

MODE 1

C/T =0

C/T =1

49/175


Part 6Part 6

O SC 1/12

T L1(8 b its)

T H1(8 b its)

T F1

INT 1 PIN

G AT E

T R1

T 1 PIN

INT ERRUPT

MODE 2

RELO AD

50/175


Part 7Part 7

O SC 1/12

T L0(8 b its)

T H0(8 b its)

T F0

INT 0 PIN

G AT E

T R0

T 0 PIN

INT ERRUPT

MODE 3

C/T =0

C/T =1

T F1 INT ERRUPT1/12 fosc

T R1

51/175

Intel 8051: Serial Port InterfaceIntel 8051: Serial Port Interface

Full-duplex Serial port receive and transmit registers

are both accessed at Special Function Register SBUF– Writing to SBUF loads the transmit register– Reading from SBUF accesses a physically separated receive register

Four modes of operation– In all four modes transmission is initiated by

any instruction that uses SBUF as destination register– Reception is initiated in Mode 0 by condition RI=0 and REN=1

In other modes by the incoming start bit if REN=1 SCON - Serial Port Control Register

Part 1Part 1

52/175


SM0 SM1:– 00: Mode 0, Shift register, fosc//12

– 01: Mode 1, 8-bit UART, variable

– 10: Mode 2, 9-bit UART, fosc//32 or fosc//64

– 11: Mode 3, 9-bit UART, variable SM2: Enables multiprocessor features in Mode 2 and Mode 3

– When the stop bit is received,the interrupt will be activated only if RB8=1 (9th bit =1)

REN: Enables serial reception– Set/Clear by software

Part 2Part 2

7 6 5 4 3 2 1 0SCON SM0 SM1 SM0 REN TB8 RB8 TI RI

53/175


TB8: 9th data bit that will be transmitted in Mode2 and Mode3– Set/Clear by software

RB8: 9th data bit that was received in Mode2 and Mode3In Mode 1, if SM2=0, is the stop bit that was received

TI: Transmit interrupt flag– Set by hardware. Must be cleared by software

RI: Receive interrupt flag– Set by hardware. Must be cleared by software

Part 3Part 3

7 6 5 4 3 2 1 0SCON SM0 SM1 SM0 REN TB8 RB8 TI RI

54/175


MODE 0:– Serial data enters and exits through RXD– TXD outputs shift clock– 8 bits are transmitted/received: 8 data bits (LSB first)– The baud rate is fixed at 1/12 oscillator frequency

MODE 1:– Serial data enters through RXD, exits through TXD– 10 bits are transmitted/received:

start bit(0), 8 data bits (LSB first), stop bit(1)– On receive the stop bit goes into RB8 in SCON register– The baud rate is variable

Part 4Part 4

55/175


MODE 2:– Serial data enters through RXD, exits through TXD– 11 bits are transmitted/received:

start bit(0), 8 data bits (LSB first), a programmable 9th bit, stop bit(1)– On transmit, the 9th bit is TB8 in SCON register– On receive, the 9th bit goes into RB8 in SCON register– The baud rate is programmable to either

1/32 or 1/64 the oscillator frequency MODE 3:

– Same as MODE 2 in all respects except baud rate– The baud rate is variable

Part 5Part 5

56/175


Mode 0 Baud Rate = Oscillator frequency/12 Mode 2 Baud Rate =[(2SMOD)/64]*Oscillator frequency

– SMOD is bit in Special Function Register PCON Mode 1 and Mode3 baud rate is

determined by Timer 1 overflow rate Mode 1,3 Baud Rate =[(2SMOD)/32]* Timer 1 Overflow Rate

– Timer mode, auto-reload :Timer Overflow Rate=Oscillator frequency/[12*(256-TH1)]

Part 6Part 6

57/175


Part 7Part 7

Timer1BaudRate

fosc SMODC/T Mode

ReloadValue

62.5 K 12 MHz 1 0 2 FF

19.2 K 11.059 MHz 1 0 2 FD

9.6 K 11.059 MHz 0 0 2 FD

4.8 K 11.059 MHz 0 0 2 FA

2.4 K 11.059 MHz 0 0 2 F4

1.2 K 11.059 MHz 0 0 2 E8

135.5 11.059 MHz 0 0 2 1D

110 6 MHz 0 0 2 72110 12 MHz 0 0 1 FEEB

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Intel 8051: Interrupt Control Intel 8051: Interrupt Control

Part 1Part 1

EA: Enable/Disable all interrupts– If EA=0 no interrupts will be acknowledged– If EA=1 each interrupt source is individually enabled/disbled

ES: Serial Port interrupt enable bit ET: Timer interrupt enabled bit EX: External interrupt enable bit

7 6 5 4 3 2 1 0IE EA - - ES ET! EX1 ET0 EX0

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Part 2Part 2

• 5 interrupt sources

• 2 external(INT0, INT1)

• 2 timers(TF0, TF1)

• Serial Port(RI or TI)

T F0

IE0

IT 0=0

IT 0=1

INT 0

IE1

IT 1=0

IT 1=1

INT 1

T F1

RI

T I

INT ERRUPTSO URCE

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Part 3Part 3

External interrupts– Level-activated or transition-activated

depending on bits IT0, IT1 in register TCON

– The flags that generate these interrupts areIE0, IE1 in TCON

• Cleared by hardware if the interrupt was transition-activated

• if the interrupt was level-activated,external source controls request bits

– If external interrupt is level-activated, the external source has to hold request active,until the requested interrupt is actually generated.

– External source has to deactivate the requestbefore interrupt service is completed,or else another interrupt will be generated

IE0

IT0=0

IT0=1

INT0

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Part 4Part 4

Timer interrupts– Interrupts are generated by TF0 and TF1 in register TCON– When a timer interrupt is generated, the flag that generated it is

cleared by hardware when the service routine is vectored to Serial Port interrupt

– generated by the logical OR of bits RI and TI in register SCON

TI

R I

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Part 5Part 5

Priority bit=1: High Priority; Priority bit=0: Low Priority PS: Serial Port priority bit PT: Timer priority bit PX: External priority bit

7 6 5 4 3 2 1 0IP - - - PS PT1 PX1 PT0 PX0

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Part 6Part 6

A low-priority interrupt can be interrupted by a higher priority interrupt, but not by another low-priority interrupt

A high priority interruptcannot be interrupted by any other interrupt source

If two requests are received simultaneously,the request of higher priority level is serviced

If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced

– ``priority within level'' structure is only usedto resolve simultaneous requests of the same priority level.

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Part 7Part 7

Interrupt Prioritywithin Level Polling Sequence

1 (Highest) External Interrupt 0

2 Timer 0

3 External Interrupt 1

4 Timer 1

5 (Lowest) Serial Port

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Part 8Part 8

The INT0 and INT1 levels are inverted and latchedinto the Interrupt Flags IE0 and IE1 at S5P2 of every machine cycle

Serial Port flags RI and TI are set at S5P2 The Timer 0 and Timer 1 flags, TF0 and TF1,

are set at S5P2 of the cycle in which the timers overflow If a request is active and conditions are right,

a hardware subroutine call to the requested service routinewill be the next instruction to be executed

In a single-interrupt system, the response time is alwaysmore than 3 cycles and less than 9 cycles

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Intel 8051: Reset Intel 8051: Reset

The reset input is the RST pin, which has a Schmitt Trigger input Accomplished by holding the RST pin high

for at least two machine cycles (24 oscillator periods)while the oscillator is running

The RST pin is sampled during S5P2 of every machine cycle While the RST pin is high,

the port pins, ALE and PSEN are weakly pulled high Driving the ALE and PSEN pins to 0 while reset is active

could cause the device to go into an indeterminate state

Part 1Part 1

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Intel 8051: Reset Intel 8051: Reset

Part 2Part 2

S5 S6 S1 S2 S3 S4

ALE

PSEN

S5 S6 S1 S2 S3 S4

A0-A7 A0-A7INS .IN

S5 S6 S1

P0 INS .IN

INS .IN

A0-A7INS .IN

INS .IN

RST

INT ERNAL RESET SIG NAL

A0-A7 A0-A7INS .IN

INS .IN

INS .IN

SAM PLERST

SAM PLERST

S2 S3

11 O SC. PERIO DS 19 O SC. PERIO DS

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Intel 8051: Power On Reset Intel 8051: Power On Reset

RST pin must be held high long enough to allow the oscillator to start up plus two machine cycles

The oscillator start-up time depend on the oscillator frequency Port pins will be in a random state until the oscillator has started

and the internal reset algorithm has written 1s to them Powering up the device without a valid reset could cause the CPU

to start executing instructions from an indeterminate location

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Intel 8051: EPROM Versions Intel 8051: EPROM Versions

Electrically programmable by user Relative slow Limited number of erase/write cycles

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Intel 8051: OTP Versions Intel 8051: OTP Versions

One Time Programmable It is standard EPROM without erasing window It is used for limited production

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Intel 8051: FLASH VersionsIntel 8051: FLASH Versions

Supports in-system and in-board code changes Electrically erasable Reduces code inventory and scrap Simplifies the task of upgrading code and

reduces upgrade cycle time Provides just-in-time system software downloads Truly non-volatile

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Intel 8051: Intel 8051: The On-Chip OscillatorThe On-Chip Oscillator

Intel 8051 microcontrollers have an on-chip oscillator

resonators are connected between XTAL1 and XTAL2 pins

external oscillators (HMOS or CMOS)

8051

XTAL2

XTAL1

VSS

C1

C2

QUARTZ CRYSTAL ORCERAM IC RESONATOR

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Intel 8051: Power ManagementIntel 8051: Power Management

Low power devices Power saving Voltage monitoring

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Intel 8051: Intel 8051: Power Reduction ModesPower Reduction Modes

CHMOS versions provides power reduced modes of operations There are two power reducing modes Idle and Power Down In the Idle mode oscillator continues to ran

Interrupt, Timer and Serial Port blocks continue to be clockedclock signal is gated off to the CPU

In the Power Down mode the oscillator is frozen

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Intel 8051: Instruction Set Intel 8051: Instruction Set

Arithmetic OperationsADD AdditionADDC Addition with Carry FlagSUBB SubtractionINC IncrementDEC DecrementMUL MultiplyDIV DivideDA Decimal Adjust Accumulator

Part 1Part 1

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Logical OperationsAND AndORL OrXRL Exclusive-OrCLR A Clear (Accumulator)CPL A ComplementRL A Rotate LeftRLC A Rotate Left through Carry FlagRR A Rotate RightRLC A Rotate Right through Carry FlagSWAP A Swap nibbles within Accumulator

Part 2Part 2

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Data TransferMOV MoveMOVC Move Code byteMOVX Move External RAM byte/wordPUSH Push direct byte on stackPOP Pop direct byte from stackXCH ExchangeXCHD Exchange low order Digit

Part 3Part 3

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Boolean Variable ManipulationCLR Clear bit/flagSET Set bit/flagCPL Complement bit/flagANL AND bit and flagORL OR bit and flagMOV Move bit

Part 4Part 4

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Program and Machine Control #1ACALL Absolute Subroutine CallLCALL Long Subroutine CallRET Return from SubroutineRETI Return from interruptAJMP Absolute JumpLJMP Long JumpSJMP Short (Relative) JumpJMP @A+DPTR Jump indirect relative to the DPTR

Part 5Part 5

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Program and Machine Control #2JZ Jump if Accumulator is ZeroJNZ Jump if Accumulator is Not ZeroJC Jump if Carry flag is setJNC Jump if No Carry flagJB Jump if Bit setJNB Jump if Bit Not setJBC Jump if Bit set & Clear bitCJNE Compare and Jump if Not ZeroDJNZ Decrement and Jump if Not ZeroNOP No Operation

Part 6Part 6

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Instructions that affect Flag Settings #1C OV AC

ADD X X XADDC X X XSUBB X X XMUL 0 XDIV 0 XDA XRRC XRLC X

Part 7Part 7

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Instructions that affect Flag Settings #2C OV AC

SET C 1CLR C 0CPL C XANL XORL XMOV C, bit XCJNE XOperations on PSW X X X

Part 8Part 8

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Intel 8051: Intel 8051: Addressing ModesAddressing Modes

Immediate Addressing

Direct Addressing

Indirect Addressing

– refers to Internal RAM, never to an SFR

External Direct

– only two commands that use External Direct

– DPTR holds the correctexternal memory address

External Indirect

Code Indirect

MOV A,#20h

MOV A,30h

MOV A,@R0

MOVX A,@DPTR

MOVX @DPTR,A

MOVX @R0,A

MOVC A,@A+DPTR

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Intel 8051: Keil C Compiler Intel 8051: Keil C Compiler

Keil Compiler C51 includes extensions (for ANSI C) for:– Memory Types and areas on the 8051– Memory Models– Memory Type Specifiers– Variable Data Type Specifiers– Bit variables and bit-addressable data– Special Function Registers– Pointers– Function Attributes

Part 1Part 1

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Program Memory– code specifier refers to to the 64Kbyte code memory

char code text[] = “ENTER PARAMETER”; – Accessed by opcode MOVC @A+DPTR

Program Memory is read only; it cannot be written to It can reside within 8051 CPU, it may be external, or both Program code, including all functions and library routines are

stored in program memory

Part 2Part 2

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Data Memory– Up to 256 bytes of internal data memory are available

depending upon the 8051 derivate

– data refers to the first 128 bytes of internal memorychar data var1;

– idata refers to all 256 bytes of internal data memorygenerated by indirect addressingfloat idata x,y,z;

– bdata refers to 16 bytes of bit-addressable memoryin the internal data memory (20h to 2Fh)char bdata flags;

Part 3Part 3

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External Data Memory– xdata specifier refers to any location

in the 64KByte address space of external data memoryunsigned long xdata array[100];

– pdata specifier refers to only 1 page of 256 bytesof external data memoryunsigned char xdata vector[10][4][4];

Part 4Part 4

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Special Function Register Memory– SFRs are declared in the same fashion as other C variables

– sfr (rather then char or int)sfr P0 = 0x80; /*Port0, address 80h*/

– sfr16 access 2 SFRs as 16-bit SFR (8051 derivatives)sfr16 T2 = 0xCC /*Timer 2; T2L 0CCh, T2H 0CDh)

– sbit allows to access individual bits within an SFRsfr PSW=0xD0;sfr IE=0xA8;sbit EA=IE^7;sbit OV=0xD0^2;sbit CY=0xD7;

Part 5Part 5

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Unique C51 Data Types– bit

static bit done_flag=0;– sbit

sbit EA= oxAF; /*defines EA to be the SFR bit at 0xAF*/– sfr(Special Function Registers, 0x80-0xFF)

sfr P0 = 0x80; /* Port-0, address 80h*/sfr P2 = 0xA0; /* Port-2, address 0A0h */

– sfr16

sfr16 T2=0xCC; /* Timer 2: T2L 0CCh, T2H 0CDh

Part 6Part 6

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Memory Models– SmallModel -

all variables, by default, reside in the internal data memory• All objects, as well as stack must fit into internal RAM

– Compact Model -all variables, by default, reside in one page of external data memory

• Can accommodate a maximum of 256 variables• Slower then small model

– Large Model - all variables, by default, reside in external data memory

• The Data Pointer (DPTR) is used for addressing• Memory access is inefficient• Generates more code then small and compact model

Part 7Part 7

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Memory-specific Pointers– Include a memory type specification in the pointer declaration– May be used to access variables in the declared memory area only

char data *str;int xdata *numtab;long code *powtab;

Part 8Part 8

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Function Declarations Extensions allow to:– Specify a function as an interrupt procedure– Choose register bank used– Select the memory model

– Specify reentrancy[return_type] funcname ([args]) [{small|compact|large}]

[reentrant][interrupt n][using n]

• small, compact, large - memory model• reentrant - recursive function• interrupt - interrupt function• using - specify register bank

Part 9Part 9

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Function Parameters and the Stack– The stack pointer on the 8051 access internal data memory only– C51 locates the stack area immediately following

all variables in the internal data memory– The stack pointer access internal data memory inirectly– C51 assigns a fixed memory location for each function parameter– Only return address is stored on the stack– Interrupts fuctions switch register banks and

save the values of few registers on the stack– By default, the C51 compiler passes up to three arguments in registers

Part 10Part 10

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Passing Parameters in Registers

Part 11Part 11

ArgumentNumber

char1 byte ptr

int2 bytes ptr

longfloat

generic ptr

1 R7 R6&R7 R4-R7 R1-R3

2 R5 R4&R5 R4-R7 R1-R3

3 R3 R2&R3

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Function Return Values

Part 12Part 12

Return Type Register Description

bit Carry Flag

char R7

int R6&R7 MSB in R6, LSB in R7

long R4-R7 MSB in R4, LSB in R7

float R4-R7 32-bit IEEE format

generic ptr R1-R3Memory type in R3, MSB R2, LSB R1

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Specifying the Memory Model for a Function#pragma small /*default small model */

extern int calc (char i, int b) large reentrant;extern int func (char i, float f) large;extern void *tcp (char xdata *xp, int ndx) small;

int mtest (int i, int y){ /*small model*/return (i*y + y*i + func(-1, 4.75);}

int large_func (int i, int k) large { /*large model*/return (mtest(i,k) * 2)}

Part 13Part 13

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Specifying the RegisterBank for a Functionvoid rb_function (void ) using 3 { ... }

– The using attribute affects object code as follows:• The currently selected register bank is saved on stack• The specified register bank is set • The former register bank is restored before the function is exited

– Register banks are useful when processing interrupts orwhen using a real-time operating system

– The using attribute may not be used infunctions that returns a value in registers

Part 14Part 14

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Register Bank Access The REGISTERBANK control directive allows you to specify which

default register bank to use Upon reset, 8051 loads the PSW with 00h, which selects register

bank 0. To change this, you sholud:– Modify the startup code to select a different bank– Specify the REGISTERBANK control directive along with the new

register bank number By default, C51 generates code that accesses the registers R0-R7

using absolute addresses To make a function insensitive to the current bank, it must be

compiled using the NOAREGS control directive

Part 15Part 15

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Interrupt Functions void timer0 (void) interrupt 1 using 2 {

if (++interruptcnt == 4000){second++;Interruptcnt=0; }

}– The interrupt attribute takes an argument

an integer constant in the 0 to 31 value range– The interrupt attribute affects object code as follows:

• The contains of SFR ACC, B, DPH, DPL and PSW,when required, are saved on stack

• All working registers are stored on stack if a register bank is not specified

• SFRs and working registers are restored before exiting function• The function is terminated by 8051 RETI instruction

Part 16Part 16

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Reentrant Function can be shared by several processes at the same time.

When a reentrant function is executing, another process can interrupt it and then begin to execute that same function. The reentrant functions may be called recursively:

int calc (char i, int b) reentrant {

int x;

x=table[i];

return (x*b);

} Reentrant functions can be called simultaneously by two or more

processes. Reentrant functions are often required in real-time applications or

when interrupt and non-interrupt code must share a function.

Part 17Part 17

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Functions may be selectively defined as reentrant, using the reentrant attribute.

For each reentrant function, a reentrant stack area is simulated in internal or external memory.

The following rules apply to reentrant functions:– bit type arguments or local variables may not be used– must not be called from alien functions or using alien attribute– may have other attributes like using or interrupt– return addresses are stored in the 8051 hardware stack– functions using different memory models may be intermixed– each of three reentrant models (small, compact and large) contains its

own reentrant stack and SP

Part 18Part 18

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Control directives are used to control the operation of the compiler and can be specified after the filename on the command line or within a source file using the #pragma directive:

C51 testfile.c SYMBOLS CODE DEBUG

or

#pragma SYMBOLS CODE DEBUG

Directive categories:– source controls define macros on the command line and determine the

name of the file to be compiled)– object controls affect the form and content of the generated object

module; allow you to specify the optimizing level or include debugging information in the object file

– listing controls govern various aspects of the listing file (format and specific content)

Part 19Part 19

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The C51 is an optimizing compiler. The C51 provides six different levels of optimizing:

– constant folding, simple access optimizing, jump optimizing– dead code elimination, jump negation– data overlaying– peephole optimizing– register variables, extended access optimizing, local common

subexpression elimination, case/switch optimizing– global common subexpression elimination, simple loop optimizing– loop rotation

Part 20Part 20

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General optimizations:– constant folding: several constant values occurring in an expression

or address calculation are combined as a constant– jump optimizing: jumps are inverted or extended to the final target

addresses when the program efficiency is thereby increased– dead code elimination: code which cannot be reached is removed– register variables: automatic variables and function arguments are

located in registers when possible– parameter passing via registers: a maximum of three function

arguments can be passed in registers– global common subexpression elimination: identical subexpressions

or address calculations that occur multiple times in a function are calculated only once

Part 21Part 21

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8051 - specific optimizations– peephole optimization: complex operations are replaced by simplified

operations when memory space or execution time can be saved as a result

– extended access optimizing: constants and variables are included directly in operations

– data overlaying: data and bit segments of functions are overlaid with other data and bit segments by the linker/locator

– case/switch optimization: any switch and case statements are optimized by using a jump table or string of jumps

Part 22Part 22

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Options for code generation:– OPTIMIZE(SIZE): common C operations are replaced by subprograms,

thereby reducing the program code– NOAREGS: C51 no longer uses absolute register access; program

code is independent of the register bank– NOREGPARAMS: parameter passing is always performed in local data

segments

Part 23Part 23

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You can easily interface C51 to routines written in 8051 assembler For an assembly routine to be called form C, it must be aware of

the parameter passing and return value conventions used in C

Function parameters By default C functions pass up to three parameters in registers.

The remaining parameters are passed in fixed memory locations. Functions that pass parameters in registers are prefixed with the

underscore character (_functionName)

Part 24Part 24

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Parameter passing in registers

arg.no. char, 1byte ptr. Int, 2byte ptr long,float gen.ptr

1 R7 R6&R7 R4-R7 R1-R3

2 R5 R4&R5 R4-R7 R1-R3

3 R3 R2&R3 R1-R3

func1 (int a) - a is passed in R6 and R7

func2 (int b, int c, int *d) - b is passed in R6&R7, c in R4 & R3, d in R1, R2 & R3

func3 (long e, long f) - e is passed in R4, R5, R6 & R7, f cannot be located in registers

func4(float g, char h) - g is passed in R4, R5, R6 & R7, h cannot be passed in registers

Part 25Part 25

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Parameter passing in fixed memory locations Parameters passed to assembly routines in fixed memory locations use

segments named ?function_name?BYTE and ?function_name?BIT to hold the parameter values passed to the function function_name.

Function return values Function return values are always passed using CPU registers:

return type registerbit carry flag

char/unsigned char/1-byte pointer R7

int/unsigned int/2-byte pointer R6 & R7

long/unsigned long/float R4 - R7

generic pointer R1-R3

Part 26Part 26

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Example:

#pragma SRC

#pragma SMALL

unsigned int asmfunc1(unsigned int arg) { return (1+arg); }

NAME ASM1

?PR?_asmfunc1?ASM1 SEGMENT CODE

PUBLIC _asmfunc1

RSEG ?PR?_asmfunc1?ASM1 USING 0

_asmfunc1: mov A,R7

add A,#10h

MOV R7,A

CLR A

ADDC A,R6

MOV R6,A

?C0001: RET END

Part 27Part 27

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Intel 8051: ManufacturersIntel 8051: Manufacturers

AMD

ARM Microcontrollers ARC Cores Atmel Dallas

Hitachi semiconductors

Intel

ISSI

Matra

Microchip

OKI Philips

Siemens

SMC

SSI

Texas Instruments ZiLog etc.

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Intel 8051: Additional FeaturesIntel 8051: Additional Features

Watch Dog Timers Clock Monitor Resident Program Loader Software protection P Supervisory Circuit

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Watch Dog TimersWatch Dog Timers

Provides a means of graceful recovery from a system problem If the program fails to reset the watchdog at some predetermined

interval, a hardware reset will be initiated Especially useful for unattended systems

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Clock MonitorClock Monitor

If the input clock is too slow, a clock monitor can shut the microcontroller down

Usually software controlled status (on/off)

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Resident Program LoaderResident Program Loader

Loads a program by initializing program/data memory from either a serial or parallel port

Eliminates the erase/burn/program cycle (typical with EPROM’s) Allows system updating from an offsite location

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Software protectionSoftware protection

Protect unauthorized snooping (reverse engineering, modifications, piracy, etc.

Only OTPs and Windowed devices option

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P Supervisory CircuitP Supervisory Circuit

Functions: P reset (active low or high)– Manual reset input– Two stage power fall warning– Backup-battery switchover– Write protection of RAM– 2.275 threshold detector– Battery OK flag indicator– Watch Dog timer

Part 1Part 1

2

1

3

4

5

6

7

8

15

16

14

13

12

11

10

9

M AXIMM AX807

PF1

PF0

Vcc

W DI

G ND

M R

LO W LINE

RESET

O UT

BAT T O K

BAT T

BAT T O N

CE IN

CE O UT

W DO

RESET

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Part 2Part 2

PIN NAME FUNCTION

1 PFI Power-Fall Input

2 PFO Power-Fall Output

3 VCC Input Supply Voltage

4 WDI Watchdog Input

5 GND Ground

6 MR Manual-Reset Input

7 LOW LINE Low-Line Comparator Input

8 RESET (H) Active-High Reset Output

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Part 3Part 3

PIN NAME FUNCTION

9 RESET (L) Active-Low Reset Output

10 WDO Watchdog Output

11 CE OUT Chip-Enable Output

12 CE IN Chip-Enable Input

13 BATT ON Battery On Output

14 BATT Backup-Battery Input

15 BATT OK Battery OK Signal Output (Vbatt>2.265)

16 OUT Output Supply Voltage to CMOS RAM

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Part 4Part 4

M AXIMM AX807

Vcc OUTBATTONBATT

0.1uF 0.1uF

CM OSRAM

REALTIM E

CLOCKCE OUT

ADDRESSDECODE

CE IN

uP

ADDRESS

I/ONM I(INT)

RESETINT

RESET

RESET

LOW LINEWDI

BATT OK

M R

WDOPFO

GND

PFI

+12V

+12V FAILUREWATCHDOG FAILURE

+5V

OTHERSYSTEMRESETSOURCES

PUSHBUTTONSWITCH

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Comparative CharacteristicsComparative Characteristics

ManufacturerClock[MHz]

V[V]

ROM[KB]

RAM[bytes]

I/OTimers/

Counterscommuni-

cationAdditionalFeatures

Atmel 242.7 to

62 to 8

128 to256

32 Up to 3full duplexserial port

Dallas 25 to 33 0 to 16256-byte

to 1.2kbyte

3two serialUSARTs

watchdog,power monitor,

address anddata encryption

Intel 0.5 to24

2.7 to6

0 to 32128 to

25624 to

562 to 3 serial port

4 to 8 channel 8-bit ADC,

watchdog,PWM

Matra 422.7 to

64 to 32

128 to256

32 2 to 3serial port,

I2C

ROMprotection and

secret tag,watchdog

Oki 242.7 to

5.50 to 16

128 to256

32 2 to 3 serial port

Siemens 18 to 40 8 to 32256-byteto 2.2-kbyte

56 3 to 4two serial

ports

two watchdogtimers, 16-bit

MPY/DIV unit

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Intel 8051-Design ExampleIntel 8051-Design Example

The complete design project using the 8051 microcontroller will be presented here. All design phases mentioned earlier will be shown:

– specification

– circuit diagram

– pcb layout

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SpecificationSpecification

The idea is to design a small, simple PCB for test purposes. The device will have:

– 8 driver outputs (ie. LEDs, relays)

– a speaker output

– a light sensor input

– 3 extra inputs

– optional serial port

The device will be based on Atmel AT89C2051microprocessor, a 20

pin 8051 variant with FLASH program memory.

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Circuit DiagramCircuit Diagram

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Circuit DescriptionCircuit Description The battery power supply is connected on terminals T1 &T2. While the circuit diagram specifies 3v/4.5v battery, the part ULN2803 needs 4.5v-5v

battery to get proper operation.

Switch SW2 allows the PCB to be turned on and off.

Capacitor C1 provides a reset signal to the microprocessor. XTAL1 provides the oscillator timing component for the microprocessor. It is important to use a crystal for XTAL1, not a ceramic resonator -

prototype testing shows that a ceramic resonator gives problems unless capacitors to ground are placed on X1 & X2.

Diode D1 provides some protection for the microprocessor in case of transients or misconnection of the battery

Optodarlington TR1 is the light sensor

Pot VR1, as labelled, adjusts the sensitivity of the light sensor Resistor R9 provides current limiting when full illumination is on TR1 at max sensitivity

The symbol PCB LAM#1 is a record of the PCB laminate ID number, and ensures the PCB laminate appears in the parts list

The symbol SKT1 is a record of the need for a socket for IC1, and ensures that the socket appears in the parts list

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Circuit DescriptionCircuit Description

TR2 is a switch used to sense illumination (On=TR1 illuminated)

Pin 6 of the micro is the LiteOn input (Low=TR1 illuminated)

SW1 is in parallel with the LiteOn input - pushing SW1 is like illuminating TR1

Resistors R12 & R13 pull up the open collector outputs P1.0 and P1.1 of IC1

IC2 is the driver IC, with several hundred milliamps drive capability on each output

R1-R8 limit the current that can be taken from each output of IC2, and are most useful when LEDs are connected directly to pins L1-L8. If other

devices are used, such as relays, the values may of R1-R8 may have to be changed, or replaced with links.

R10 limits the current from IC1 into the base of TR3 TR3 is a switch transistor that drives the sounder output (P3.7 Low=Sounder driven high)

R11 provides the class A load resistor for the sounder output

C2 Capacitively couples the speaker to TR3 and R11.

C3 provides some supply decoupling.

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PCB DiagramPCB Diagram

Central to the board are the two IC's: The AT89C2051 (in an IC socket) and ULN2803 driver. The bank of resistors to the right of the ULN2803 are primarily for limiting the current through LEDs, when they are being driven direct from the outputs. You may wish to use another value instead of the 27 ohm shown on the circuit. The circuitry to the left of the CPU is primarily for the light sensor - this is just a simple darlington phototransistor, sensitivity pot and switch

transistor.

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PCB Artwork, overlayPCB Artwork, overlay

The overlay diagram is used for the silkscreen (legend) of the

circuit board.

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PCB Artwork, top layerPCB Artwork, top layer

The top layer diagram is used for the tracks that go on the component side of the circuit

board.

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PCB Artwork, bottom layerPCB Artwork, bottom layer

The bottom layer diagram is used for the tracks that go on the solder side of the circuit board. The layer is printed as if you are viewing through the circuit board (this is a convention used so that the layers line up) and will have to be reversed left-for-right before the copper tracks are

printed.

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PCB Art, Hole drilling diagramPCB Art, Hole drilling diagram

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Parts descriptionParts description

RB.06/.15 - Radial polarised capacitor, 0.060 inch pitch lead space, 0.15 inch diameter

RB.1/.2 - Radial polarised capacitor, 0.1 inch (2.5mm) pitch lead spacing, 0.2 inch (5mm) diameter

DIODE0.3 - Axial diode, 0.3 inch (7.5mm) pitch lead spacing

DIP20 - IC, standard 0.3 inch pitch 20 pin DIP package

DIP18 - IC, standard 0.3 inch pitch 18 pin DIP package

TP - Test point or terminal

PCLAMINATE - The part being specified here is the etched PCB laminate

AXIAL0.4 - 0.4 inch pitch unpolarised component (eg resistor)

TV-06A - Push button switch, zippy brand

S2020SMT - Slide switch

TO-92A - Standard TO-92 package, with staggered leads, 0.1 inch pitch spacing

VR4 - Adjustable pot, staggered leads, 0.1 inch pitch spacing

XTAL2 - Crystal, HC49/4H (also called HC49Small) package

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Parts notesParts notes

2.2UF50VMM - Radial polarised capacitor, Microminiature style, eg Rubycon, elna

AT89C2051 - Atmel microprocessor, see Atmel site for data and a programmer

ULN2803A - Manufacturer: Allegro (formerly known as Sprague)

27E - Resistor, value 27 ohm - substitute if required for different outputs

MEL12 - Phototransistor - many substitutes will work, but darlington types offer the best sensitivity. We have used BP103B

(Farnell 212-763 in Australia). Flat goes toward TR2 for two leaded devices. 3.57945Mhz - Frequency depends on application program. Use a crystal, rather than a ceramic resonator (otherwise fit extra

capacitors to gnd on X1 and X2).

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Using the DeviceUsing the Device

The diagram on the left shows a typical circuit using the HSETI PCB, with the optional serial port in place also. The serial port does not have strict RS232 level signals, but will work with just about all PC clones with reasonable

cable lengths.

microcontrollers

Documents

data memory port

io port pins

bidirectional io port

duplex serial port

external memory locations

6ad6 p0

vcc p0

2ad2 p0